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Lecture 6 final

The PIC-18 microcontroller features a distinct separation between data memory and program memory, allowing simultaneous access to both. It includes a 21-bit program counter for up to 2MB of program memory and a 12-bit address bus for 4KB of data memory, organized into banks. Additionally, it supports various I/O ports, timers, and special features like sleep mode and watchdog timers.

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4 views

Lecture 6 final

The PIC-18 microcontroller features a distinct separation between data memory and program memory, allowing simultaneous access to both. It includes a 21-bit program counter for up to 2MB of program memory and a 12-bit address bus for 4KB of data memory, organized into banks. Additionally, it supports various I/O ports, timers, and special features like sleep mode and watchdog timers.

Uploaded by

vinod SALUNKHE
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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PIC-18 MEMORY ORGANIZATION

Data Memory and Program Memory are separated.

Separation of Data memory and Program memory makes possible the


the simultaneous access of data and instruction.

Data memory are used as general purpose registers or special function


registers.

On-chip Data EPROM are provided in some PIC-18 MCUs


Separation of Data Memory and Program Memory

21-bit program 12-bit Register


address address

Program Data
PIC-18 Memory
Memory CPU
Space Space
8-bit Data Bus
16-bit instruction
bus

Fig:- The PIC-18 Memory Spaces


PIC18FMemory
 Program memory with  Data memory with
addresses (Flash) addresses
 Also called Data
Register or File
Register

FFF=212=16x256=4096=4K
PIC18F – MCU and Memory

16 bit

2 MB
221

8 bit

4 KB
212
PIC18F Memory
 Program Memory: 32 K (215)
 Address range: 000000 to 007FFFH
 16-bit registers

Data Memory: 4 K (212)


 Address range: 000 to FFFH
 8-bit registers

 Data EEPROM
 Not part of the data memory space
 Addressed through special function registers
Microprocessor Unit
 Registers
 Bank Select Register (BSR)
 4-bit register used in direct
addressing the data memory

 File Select Registers (FSRs)


 16-bit registers used as memory
pointers in indirect addressing data
memory

 Program Counter (PC)


 21-bit register that holds the
program memory address while
executing programs
Microprocessor Unit
 Control unit
 Provides timing and control signals to various
Read and Write operations
PIC-18 DATA
MEMORY
 It consist of General purpose register and Special function registers.
Both are referred to as Data Registers.

 PIC-18 has 4KB Data Memory.

 Data Memory is Divided into Banks and each Bank has 256 bytes.

 General purpose registers are used to hold dynamic data.

 Special function register are used to control the Operation of Peripheral functions.
Only on bank is active at any time.
Fig : Data Memory map for PIC-18 Device
PIC18F - Address Buses
 Address bus
21-bit address bus for program
memory addressing capacity:
(221) = 2 MB of memory.

 12-bit address bus for data


memory
addressing capacity: (212) = 4 KB
of memory
Data Bus and Control Signals
 Data bus
 16-bit instruction/data
bus for program memory
 8-bit data bus for data
memory
 Control signals
 Read and Write
PIC18F – Data Memory with Access Banks

 Three ways to access data registers:


 Direct using Bank Select Registers (BSR)
 Bank address (4-bit) + Instruction (8-bit)
 Indirect using File Select Registers (FSR)
 FSR contains the address of the data register
 Hence, MPU uses FSR
 Access Bank using General Purpose Registers
(GPR)
Data Memory 000h
Access RAM

Organization
07Fh
080h
Bank 0 GPR
0FFh
100h
Bank 1
GPR
FFF=212=16x256=4096=4K 1FFh
200h
Bank 2
 Data Memory up to 4k bytes GPR Access Bank
 Data register map - with 12-bit 2FFh
00h
Access RAM (GPR)
address bus 000-FFF 7Fh
80h
 Divided into 256-byte banks D00h
Access SFR
FFh
Bank 13
 There are total of F banks GPR
256 Bytes

 Half of bank 0 and half of DFFh


E00h GPR=General Purpose Reg.
bank 15 form a virtual bank Bank 14 SFR=Special Function Reg.
that is accessible no matter GPR
EFFh
which bank is selected F00h
Bank 15 GPR
F7Fh
F80h
FFFh Access SFR
PROGRAM MEMORY ORGANIZATION
 The program counter (PC) is 21-bit long, which enables the user program to
access up to 2MB program memory.

 After Power On it starts to execute the instruction from address 0.

 The Location 0x08 is reserved for high-priority interrupt service routine.

 The Location 0x18 is reserved for low-priority interrupt service routine.

 Up to 128 KB of Program Memory is inside the MCU chip.

 Rest Part of the program memory is located outside of the MCU chip.
Fig: Program Memory Organization for PIC-18 Device
PIC-18 PIPELINING
 The PIC18 Divide most of the instruction execution into two
stages: instruction fetch and instruction execution.
 Up to two instructions are overlapped in their execution. One instruction
is inexecution fetch stage while the second instruction is in execution stage.
 Because of pipelining, each instruction appears to take one instruction
cycle to complete.

TCY0 TCY1 TCY2 TCY3 TCY4 TCY5

Fetch 1 Execute 1

Fetch 2 Execute 2

Fetch 3 Execute 3

Fetch 4 Flush

Fetch sub_1 Execute sub_1


Fig : An Example of Instruction Pipeline flow
PIC18F I/O Ports
 Five I/O ports
 PORT A through PORT E
 Most I/O pins are multiplexed
 Generally have eight I/O pins with
a few exceptions
 Addresses already assigned to
these ports in the design stage
 Each port is identified by its
assigned Special Function
Registers (SFR)
 PORTA (address of F80)
 PORTB (address of F81)
  these are part of data memory or
register file
TRISB must be set to specify signal direction of
PORT B.
Support Devices
Support Devices
 Timers
 A value is loaded in the register and continue changing at every clock
cycle – time can be calculated
 Can count on rising or falling edge
 There are several timers: 8-bit, 16-bit
 Controlled by SFR

 Master Synchronous Serial Port (MSSP)


 Serial interface supporting RS232

 Addressable USART
 Another serial data communication
 A/D converter
 Parallel Slave Port (PSP)
 Capture, Compare and PWM (CCP Module)
PIC18F Special Features
 Sleep mode
 Power-down mode
 Watchdog timer (WDT)
 Able to reset the processor if the program is caught in
unknown state (e.g., infinite loop)
 Code protection
 EEPROM can be protected through SFR
 In-circuit serial programming
 In-circuit debugger

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