PRIME VLSI

If their is AND gate and i want it to define as exception, which one you will select false path or disable timing
arc?
False path Disable timing arc
Point to point timing exception Pin to pin timing exception

Declaring as FP removes all timing Disable timing analysis for a specific

constraints from the path but prime pin/cell/port and don’t calculate path
time still calculates path delay but not delay
reported even though that path delay
is more or less.
Removing timing constraints on that Using this we can remove
particular path affected/unwanted cell/pin/port from
timing analysis. related arc itself is
removed timing analysis
EP= o/p port (or) register data in Disable a particular arc within a cell
SP= i/p port (or) register clock pin sometimes its also defined with SP
and EP disables timing arcs from a
start port to an end port of a cell. This
constraints is from Pin to Pin of a
cell.
CROSS CORNERS

In fabrication, a process corner represents a three or six sigma variation from nominal doping concentrations
and other parameters in transistors on a wafer. This variation can cause significant changes in the duty cycle
and slew rate of digital signals, and can sometimes result in total failure of the entire system.
Variation may occur for many reasons, such as minor changes in the humidity or temperature changes or due
to the position of the die relative to the center of the wafer.

Types of corners

1. FEOL
These corners will affect the performance of devices,
The front-end-of-line (FEOL) is the first portion of IC fabrication where the individual devices (transistors,
capacitors, resistors, etc.) are patterned in the semiconductor.
FEOL generally covers everything but not including the deposition of metal interconnect layers.

2. BEOL
back end of line is the second portion of IC fabrication where the individual devices (transistors, capacitors,
resistors, etc.) get interconnected with wiring on the wafer, the metallization layer.
Three corners exist: typical, fast and slow.
Fast and slow corners For example, a corner designated as FS denotes fast NFETs and slow PFETs.

There are five possible corners

1. typical-typical (TT)
2. fast-fast (FF)
3. slow-slow (SS)
4. fast-slow (FS)
5. slow-fast (SF)
The first three corners (TT, FF, SS) are called even corners, because both types of devices are affected evenly,
and generally do not adversely affect the logical correctness of the circuit. The resulting devices can function at
slower or faster clock frequencies.

The last two corners (FS, SF) are called "skewed" corners, and are cause for concern. This is because one type
of FET will switch much faster than the other, and this form of imbalanced switching can cause one edge of the
output to have much less slew than the other edge.

Cross corner means if we run even and odd corners at a time.

Cross corner Is considered due to temperature inversion in lower technologies.
MULTI CYCLE PATH

By default in timing checks what

happen setup is checked at next clock
edge of same cycle and hold is
checked for zeroth cycle i.e. same
clock edge .
Data has to propagate in one time
period cycle.
Here time period is 10ns if we do setup check after one time
cycle by default i.e. 10ns its incorrect because for complete
analysis of tcomb is 12 ns which is greater than one clock
cycle (10 ns)
In this case we go for MCP here we need to define where to
do setup and hold check.
If we don’t define set/hold it will do default check as in
previous slide.
The clock pessimism shows the absolute amount of extra clock skew introduced due to source and
destination clocks are reported with different types of delay even on their common circuitry. In
reality, it is not possible for common circuitry to be analyzed with 2 different delays (occurred due to
OCV) at the same time.
 CPPR is primarily due to OCV variations while CRPR is an architectural
artifact.

Clock reconvergence pessimism (CRP) is a difference in delay along the

common part of the launching and capturing clock paths.

the most common causes of CRP are reconvergent paths in clock network,
and different min and max delay of cells in the clock network.

CRP is an undesired effect.

Difference between max and min delay

is CRPR

14
3D TIMING ARC

All timing arc

information is
present in .lib file

15
 ON CHIP VARIATION
Fabrication issue
After fabrication all IC inside the same wafer and all transistor inside the same IC
may or may not have same electrical behaviour. We can see slight variations.
These variations is due to PVT conditions.
Here we can see two types of variations
[1] Local Variation
Inter chip variation i.e. die to die
[2] Global Variation
Intra chip variation
Sources Of OCV.
[1] Etching
[2] Oxide Thickness
 Process variation
[1] systematic variation Global Variation
Predictable and can be fixed
[2] random variation Local Variation
Highly unpredictable and difficult to fix
Voltage variation O
PVT
[1] supply voltage variation C
ANALYSIS
External supply voltage
[2]Internal voltage variation
v
IR drop
Temperature variation
[1] ambient temperature variation
[2]junction temperature variation
Temp increases due to power dissipation
REMEDY FOR THIS VARIATION
On Chip Variation could lead to post-silicon failure i.e. chip failue if it is not taken
care while designing.
Fabrication process variations could either increase or decrease the delay of a cell.
So we need to set early and late values while setting the derate factor.
To take care of OCV we need to add some pessimism in the timing of standard cells.
We basically apply ±x% of additional delay to all the standard cells. Which is called
OCV derate.
 ISSUES IN OCV
 Same shirt does not fit all like that fixed derate factor does not fit to all cells because not all the
cell in the path is simultaneously become varied it may vary from one path to another
 Its highly pessimistic
 Its inaccurate for lower technologies (<20nm)
AOCV
 Its introduced for below 20nm technology node.
 Instead of applying fixed derate for all ,the derate factor is calculated based on
[1]path depth (cell delay)
Derate is Inversely proportional to depth.
[2]distance(net delay)
As distance increases system variation increases.
[3]cell type [optional]
[4]drive strength [optional]

Table is of two types

1D (either depth or distance is considered)
2D(both distance and depth are considered)
Issues in AOCV
 Inaccurate for below 10nm
 Not reduces the pessimism
 POCV
POCV are more realistic than AOCV and OCV
In POCV derate is calculated based on delay standard variation (σ) of the cell.
It uses delay sigma to calculate derate factor.
The information of POCV variation is directly provided in the library itself in
LVF format. In LVF format there are two indexes used one for input transition and
other for output load. 3sigma = cell delay + net delay+ switching.
In normal distribution 68% of data falls within the 1σ range, 95% data falls within 2σ and 99.7% data fall
within the range of 3σ.
 Switching strength of N1 is greater than N2 & N3

Switching strength of N2 is greater than N3 so its VN for

N1 and AN for N3

Switching strength of N3 is smaller than N2 and N3

1 REAL
0 IDEAL

Due to this functionality of AND gate

changes

 glitch directly proportional to coupling capacitance.

 Glitch is indirectly proportional to slew(transition)
 Glitch is indirectly proportional to victim net ground
capacitance(store 0 strongly)
 Glitch is indirectly proportional to driving strength
Aggressor net which is switching from low to high and
victim is in steady high, extra pulling on victim net to
logic high in SAME DIRECTION

Aggressor net is switching from low to

high and victim is at steady low but pulling
victim net to logic high in OPPOSITE
DIRECTION from steady low to high
when victim is in steady low level vice
versa
Aggressor net (RIVER)
Victim net (BOAT)
When boat and river flow in same direction then it reaches fast
i.e. delay is less vice versa.
35
36
How To fix Crosstalk Issue
[1] Double spacing=>more spacing=>less capacitance=>less cross talk.
[2] Multiple vias=>less resistance=>less RC delay
[3] Shielding=> constant cross coupling capacitance =>known value of
crosstalk
[4] Buffer insertion=>boost the victim strength.
[5] upsizing, swaping (lvt to hvt viceversa).
[6] re routing.
[7] Maintain proper NDA rules.

37
 CHECK_TIMING
Shows possible timing problems for design.
-verbose Shows detailed information about potential problems.
clock_crossing
Checks clock interactions when there are multiple clock domains.
If a clock launches one or more paths, which are captured by
other clocks, it will have an entry in clock crossing report. If
all paths between two clocks are false paths or they are exclu-
sive/asynchronous clocks, the path is marked by *. If only part
of paths are set as false paths or exclusive/asynchronous
clocks, the path is marked by #.
generated_clocks
Checks generated clock network. The master must be driven by a
clock source. There cannot be loops of generated clocks. For
example, the source of generated clock CLK1 cannot be used to
generate clock CLK2 if CLK2 also is used to generate CLK1.

generic
Warns about generic (unmapped) cells in the design. The timing
of paths through generic cells is inaccurate because generic
cells have zero delay.
ideal_clocks
Shows the clocks that are not defined as propagated using the
/set_propagated_clock. Generally, all clocks should
be propagated so that the clock network timing is accurately
calculated. Especially, in presence of crosstalk, the delay
changes induced by other nets on the clock network are not
reflected in the calculated slacks in the design.

latch_fanout
Checks fanout of level-sensitive latches. A warning is issued if
a level-sensitive latch fans out to itself. An information mes-
sage also appears for a latch that fans out to a latch of the
same clock .

latency_override
Warns of clock latency specification conflicts. If clock source
latency is defined for both a clock and its port (source pin),
the source latency for clock object is ignored. If input_delay
is set on clock port, which also has source latency specified,
the input_delay is ignored as a source latency. Also warns if
more than one clock latency fan out to any latch clock pin.
ms_separation
Checks minimum separation of master and slave clock pulses on
master/slave latches.
multiple_clock
Warns if multiple clocks reach a register clock pin. If more
than one clock signal reaches a register clock pin, and tim-
ing_enable_multiple_clocks_per_reg is set to FALSE, then it is
undefined which one is used for analysis. In this case, use
set_case_analysis so only one clock can propagate from its
sources to the register clock pin. Using this check and the
no_clock check run significantly faster than other checks.
Hence, to save time, user may want to issue these checks sepa-
rately from other checks.

no_clock
Warns if no clock reaches a register clock pin. In this case, no
setup or hold checks are performed on data pins related to that
clock pin, and the path starting at the clock pin is not rela-
tive to a clock. For performance of this check, see the
description in the multiple_clock check.
no_driving_cell
Warns if a port does not have any driving cell. This warning is
issued only when the net connected to the port has parasitics.
In such case, the accuracy of delay calculation could be
impacted, as a default strong driver is assumed in absence of
driving cell definition. Especially, in presence of crosstalk, a
port with no driving cell could act as a strong aggressor which
could lead to significant amount of pessimism in the analysis.
Also, a port with no driving cell could act as a string victim,
which could underestimate the crosstalk effect.

no_input_delay
Warns if no clock related delay specified on an input port,
where it propagates to a clocked latch or output port. With
-verbose, the port name will be listed. Note that with tim-
ing_input_port_default_clock set to 'true', a default clock will
be assumed for the input port. Otherwise it will not be clocked,
and the paths are unconstrained. In this case, if there is no
input delay specified, check_timing will not generate warnings.
partial_input_delay
Warns if any port has partially defined input delay. This hap-
pens when set_input_delay -min is applied on a port to set the
min input delay with respect to a clock, however no
set_input_delay -max is applied to that port to specify the max
delay, or vice versa. As a result, some paths starting from the
port with partially defined input delay may become unconstrained
and some potential violations could be missed.

pll_configuration
Warns if a problem is detected in the configuration of any phase
locked loop (PLL) cells. For a PLL to be correctly configured,
the PLL output clock should reach the PLL feedback pin. If a PLL
is not correctly configured, it will not show any phase adjust-
ment on the PLL output clock.
signal_level
Checks that the driver signal level matches the load signal
level. The signal levels are determined from the cell specific
operating conditions and rail voltages (or UPF), and from the
following library attributes: input_signal_level, output_sig-
nal_level, input_voltage, output_voltage. The check is performed
on all input pins that have input_voltage defined in the timing
library. If the driver pin does not have output_voltage defined
in the library then the voltage of the rail powering the driver
pin is used as the output signal level.
supply_net_voltage
Checks that each segment of UPF supply nets has voltage assigned
to it by set_voltage command.

unconnected_pins
Checks that each power and ground pin is connected to a UPF sup-
ply net. The connection can be implicit (e.g., power domain) or
explicit (for example, connect_supply_net).

unconstrained_endpoints
Warns about unconstrained timing endpoints. This warning identi-
fies timing endpoints (output ports and register data pins) that
are not constrained for maximum delay (setup) checks. If the
endpoint is a register data pin, it can be constrained by using
create_clock for the appropriate clock source. You can constrain
output ports using the set_output_delay or set_max_delay com-
mands.
unexpandable_clocks
Warns if there are sets of clocks for which periods are not
expandable with respect to each other. The checking is only done
for the related clock domains, such as ones where there is at
least one path from one clock domain to the other. This could be
because of an incorrectly defined clock period for one or more
of the clocks. Another possibility is when asynchronous clocks
with unexpandable periods are interacting where they should have
been defined in different clock domains.
pulse_clock_non_pulse_clock_merge
Warns if pulse clock and normal clock propagate to the same
network.
pulse_clock_no_pulse_generator
Warns if the pulse clock constraints cannot be honored. This
could be because pulse clock constraints have been set on clocks
that do not drive pulse generators or the design may not have
any pulse generators.
 INPUT AND OUTPUT DELAYS

Between input and output we have to set margins as input 60% and output 40%
with respect to clk frequency because the design is hierarchy(different blocks)

Input delay-The time at which the data arrives at the input pin of the
block from external ckt with respect to reference ckt.
Output delay-The minimum time required to obtain a valid output at an
output pin.
set_input_delay -clock name min/max [get_ports x]
set_output_delay -clock name min/max [get_ports x]

47
Input and output delays
 Consider your chip is going to be placed in a board and input comes from pre block(assume a chip) and your
output goes to other chip.
 Then if u operate all this three chips as same clock. Then from the previous chip it takes time to reach your chip
considering delay of i/o delays of previous block.
 If you don’t give input delay then at rising clock edge your chip then due to this external delay data will arrive
late this leads to fault logic.
Example=If you don’t set the timing for class to attend before then everyone will attend the class as per their
interest and its useless

 If u give delay then you chip makes some delay within it such that the data reaches the input register(not input
pin) at next rising edge and you logic works.

 Similarly to output pin also so that next module prepare themselves..

Input delay --> Sets input delay on pins or input ports relative to a clock signal.
means time given to outer world to reach our own design.
Example =time we need to fix before starting the session so that everyone (outsiders from different location will
attend on that fix time without miss)

Output delay --> Sets output delay on pins or output ports relative to a clock signal means time taken by my
design.
Example=(fixing the duration of the class to be taken considering every students requirement and issues)
CELL DELAY AND NET DELAY
All cells have their own delay information in .lib file.
Delay depends on three factors
1. input transition of cell (how signal is rising and falling)
2. Output capacitance (wire/net capacity + input capacitance)
3. Operating conditions(PVT)
 i/p transition, o/p capacitance are directly proportional to cell delay.
PVT condition
 If p=slow delay is more
 If P = fast delay is less.
 Voltage is indirectly proportional to delay
 Temperature is directly proportional to delay (higher technology)
 Final delay = 6ns+ (P + V + T values all defined in .lib)

1 2 3 4 5 6 7 Input transition
0.1
0.2 6ns
0.3
0.4
0.5

O/p
capa out of cell delay and net delay which is more effective as we
citan
ce move from higher technology to lower technology?
Virtual clock

Suppose we have no clocks in in the current design which is purely combinational logic at this time we
use a dummy clock to set input and output delay/slave clock.
 Recovery and Removal Checks

 Recovery and removal analysis are done on asynchronous signals like resets.
 These specify the requirement of these signals with respect to clock.
 Recovery Time is the minimum required time to the next active clock edge the after the reset is released.
 Removal Time is the minimum required time after the clock edge after which reset can be released.
 If we don’t use Reset for asynchronous it creates functional/metastability(quasi state) issues.
Difference between 14nm and 7nm

As we move from higher to lower nodes due to shrinking technology different issues evolves and existing
issues get stronger.
 Crosstalk increases
 More DRV
 More IR drop
 Congestions issue because of reducing area
 More power dissipation (waste of heat in form of heat)
References
 Recorded session of Anji sir

YouTube channels.

 Back to basics
 Digital shri
 VLSI team

websites
 VLSI physical design
 Backend VLSI adventure
 Team VLSI
 Micro-ip.com