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Timing Diagram

The document provides an overview of the timing diagram for the 8085 microprocessor, detailing the execution time for each instruction represented in T-states. It explains key concepts such as instruction cycles, machine cycles, and various types of cycles including opcode fetch, memory read/write, I/O read/write, and interrupt acknowledge cycles. Each cycle is associated with a specific number of T-states that define the timing for operations performed by the microprocessor.

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Mei Arul
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13 views20 pages

Timing Diagram

The document provides an overview of the timing diagram for the 8085 microprocessor, detailing the execution time for each instruction represented in T-states. It explains key concepts such as instruction cycles, machine cycles, and various types of cycles including opcode fetch, memory read/write, I/O read/write, and interrupt acknowledge cycles. Each cycle is associated with a specific number of T-states that define the timing for operations performed by the microprocessor.

Uploaded by

Mei Arul
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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TIMING DIAGRAM OF MICROPROCESSOR 8085

TIMING DIAGRAM

• IT IS A GRAPHICAL REPRESENTATION.
• IT REPRESENTS THE EXECUTION TIME
TAKEN BY EACH INSTRUCTION IN A
GRAPHICAL FORMAT.
• THE EXECUTION TIME IS
REPRESENTED IN T-STATE.
INSTRUCTION CYCLE
INSTRUCTION CYCLE

• TIME REQUIRED TO EXECUTE AND


FETCH AN ENTIRE INSTRUCTION IS
CALLED AS INSTRUCTION CYCLE
MACHINE CYCLE

• IT IS THE TIME REQUIRED BY THE


MICROPROCESSOR TO COMPLETE THE
OPERATION OF ACCESSING THE MEMORY
DEVIES (OR) I/O DEVICES.
T – STATE

• ONE TIME PERIOD OF FREQUENCY OF


MICROPROCESSOR IS CALLED T – STATE
• A T – STATE IS MEASURED FROM THE
FALLING EDGE OF ONE CLOCK PULSE TO
THE FALLING EDGE OF NEXT CLOCK PULSE
OPCODE FETCH CYCLE
• IT FETCHES THE INSTRUCTION FROM
MEMORY AND DELIVERS IT TO THE
INSTRUCTION REGISTER OF THE
MICROPROCESSOR
• IT HAS 4 (OR) 6 T – STATES
MEMORY READ CYCLE
• THE MICROPROCESSOR READS THE
CONTENT OF THE MEMORY LOCATION
• THE CONTENT IS PLACED EITHER IN THE
ACCUMULATOR (OR) ANY OTHER REGISTER
OF THE CPU
• IT HAS 3 T – STATES
MEMORY WRITE CYCLE
• IN A MEMORY CYCLE THE CPU SENDS DATA
FROM THE ACCUMULATOR (OR) ANY OTHER
REGISTER TO THE MEMORY
• IT HAS 3 T – STATES
I/O READ CYCLE
• IN AN I/O READ CYCLE THE MICROPROCESSOR
READS THE DATA AVAILABLE AT AN INPUT
PORT (OR) INPUT DEVICE.
• THE DATA IS PLACED IN THE ACCUMULATOR
• IT HAS 3 T – STATES
I/O WRITE CYCLE
• IN AN I/O WRITE CYCLE, THE CPU SENDS
DATA TO AN I/O PORT (OR) I/O DEVICE FROM
THE ACCUMULATOR.
• AN I/O WRITE CYCLE IS SIMILAR TO A
MEMORY WRITE CYCLE
• IT HAS 3 T – STATES
INTERRUPT ACKNOWLEDGE CYCLE

• IT IS A MACHINE CYCLE EXECUTED BY 8085


PROCESSOR TO GET THE ADDRESS OF THE
INTERRUPT SERVICE ROUTINE IN ORDER TO
SERVICE THE INTERRUPT DEVICE
• IT HAS 6 (OR) 12 T – STATES
BUS IDLE CYCLE

• THE OPCODE FETCH CYCLE TAKES 4 T – STATES AND


THE REMAINING 6 T – STATES, DIVIDED INTO TWO
MACHINE CYCLES FOR THE INSTRUCTION
EXECUTION.
• DURING, THESE 6 T – STATES NO BUS OPERATION
ARE PERFORMED.
• HENCE, THEY ARE CALLED BUS IDLE MACHINE
CYCLE.

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