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Datapath Microroutine

The document provides an overview of the datapath within a processor, detailing its components such as the ALU, registers, and buses, which facilitate data movement. It outlines the basic steps in instruction execution, including fetching, incrementing the program counter, and executing instructions, as well as the operations involved in memory read and write. Additionally, it explains the advantages of a multi-cycle datapath architecture, which allows for more efficient instruction execution by using multiple buses and enabling access to multiple registers in a single clock cycle.

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Nivedita Murugan
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3 views20 pages

Datapath Microroutine

The document provides an overview of the datapath within a processor, detailing its components such as the ALU, registers, and buses, which facilitate data movement. It outlines the basic steps in instruction execution, including fetching, incrementing the program counter, and executing instructions, as well as the operations involved in memory read and write. Additionally, it explains the advantages of a multi-cycle datapath architecture, which allows for more efficient instruction execution by using multiple buses and enabling access to multiple registers in a single clock cycle.

Uploaded by

Nivedita Murugan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Datapath

Introduction
• Movement of data within a processor from one component to another
• Registers, ALU, and the interconnecting bus collectively form the
datapath
• ALU
• Performs arithmetic and logical operations
• Contains control lines to select one of the possible ALU
operations
• Registers
• General purpose registers to store data, memory address register
(MAR), memory data register (MDR), program counter (PC),
instruction register (IR), temporary registers (optional)
• Buses
• Internal (one or more) and external to carry the data from one
component to another 2
Single Bus
Organization of
Datapath

3
Basic Steps in Instruction Execution
• Fetch the contents of the memory location pointed to by the PC.
Load these contents into the IR to be interpreted.
IR  [PC]

• Assuming that the memory is byte addressable, increment the


contents of the PC by 4.
PC  PC + 4

• Carry out the actions specified by the instruction.

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 4
Basic Steps in Instruction Execution
• Most instructions involve the following operations:
• Transfer a word of data from one processor register to another
or the ALU
• Perform an arithmetic or logical operation and store the result
in a processor register
• Fetch the contents of a memory location and load them into a
processor register
• Store a word of data from a processor register into a memory
location

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 5
Register Transfer
MOV R1, R4

• Enable the output of by


setting to 1. This places the
contents of on the processor
bus.
• Enable the input of the
register b setting to 1. This
loads data from the processor
into register .

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 6
Arithmetic and Logic Operations
ADD R1, R2,
R3

•,
•,,,
•,

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 7
Memory Read and Write
• Memory Read
MOV (R1),
R2

• Memory Write
MOV R2,
(R1)

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 8
Execution of a Complete Instruction

ADD (R3), R1

9
Multi Cycle Data Path Architecture

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 10
Why Multi Cycle Data Path ?
• In a single cycle data path architecture , exclusively single data word
could be moved through the bus in a given clock cycle

• Because of this no of steps needed to execute the inst increases

• To decrease the no of steps needed to execute the inst and to transfer


more than one word in a clock cycle we go for multicycle

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 11
How Multi Cycle Data Path Works
• Three buses are used to link reg and ALU of the CPU

• All GPR ,
R1, R2…Rn are presented in one block known as reg files

• Figure 2. shows the register files has three ports

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 12
Multi Cycle Data Path
Architecture

Add R6, R4, R5

13
Add R6, R4, R5

14
How Multi Cycle Data Path Works
• One input and two output ports

• Therefore data of three registers are possible to access in single clk


cycle

• Through Bus C, the value could be put in one reg

• Data from two regs is available through Bus A and Bus B

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 15
How Multi Cycle Data Path Works

• Bus A and B are used to move the source operands to i/ps of the ALU
A and B

• After ALU process is executed the resultant is moved to destination


operand through the bus C

• Separate incremental unit is provided to increment the value of PC


after every instruction is executed

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 16
Execution of Instruction using Multi Cycle Data Path
Add R6, R4, R5 Control Sequence

• The inst adds the values of register R4 & R5 and stores the resultant in
R1

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 17
Multi Cycle Data Path Add R1, R2,
R3 Control Sequence Explanation

• Step 1: The value of the PC are moved to MAR by means of Bus


B to begin Read operation. PCMAR

• Parallelly PC is incremented point towards the next instruction


PCPC+1

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 18
Multi Cycle Data Path Add R1, R2, R3 Control
Sequence Explanation

• Step 2: The processor waits for WMFC signal from the memory

• Step 3: The inst code is moved from MDR to IR MDR IR

• Step 4: The inst decoder decodes the IR contents

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 19
Multi Cycle Data Path Add R6, R4,
R5 Control Sequence Explanation

• Step 4: Two values from reg R4 & R5 are made accessible at inputs A
and B of ALU by means of Bus A & B

• By activating the Add signal two inputs are added

• Through Bus C the resultant is stored in R1

Prepared by Dr. R.V. Aswiga, Dr. K.M. Monica, Dr. G. Anushiya Rachel 20

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