BOOLEAN

ALGEBRA

UNIT
2
INTRODUCTION TO
BOOLEAN
ALGEBRA

1
 BOOLEAN
ALGEBRA
• Also known as Switching Algebra
› Invented by mathematician George Boole in 1849
› Used by Claude Shannon at Bell Labs in 1938
• To describe digital circuits built from relays
• Digital circuit design is based on
› Boolean Algebra
• Attributes
• Postulates
• Theorems
› These allow minimization and manipulation of logic gates
for optimizing digital circuits

2
 BOOLEAN ALGEBRA
ATTRIBUTES

• Binar • AND
y operation
› A3a: 0•0=0 X Y X•Y
› A1a: X=0 if
› A4a: 1•1=1 0 0 0
X=1
› A5a: 0•1=1•0=0 0 1 0
• Complement
› A1b: X=1 if
X=0 - The dot • means 1 0 0
› aka invert, NOT
AND 1 1 1
› A2a: if X=0,
X’=1 - Other symbol
› A2b: if X=1, X’=0 forAND:
- The tick mark ’ X•Y=XY (no symbol) X Y X+Y
means • OR 0 0 0
X X’
complement, Operation 0 1 1
0 1 › A3b: 1+1=1
invert, or NOT 1 0 1
1 0 - Other symbolfor › A4b: 0+0=0
complement: X’= X › A5b: 1+0=0+1=1 1 1 1
- The plus +
means OR
3
 BOOLEAN ALGEBRA
ATTRIBUTES
• Variable: Variables are the different symbols in a Boolean expression
• Literal: Each occurrence of a variable or its complement is called a
literal
• Term: A term is the expression formed by literals and operations at
one
level

– A, B, C are three variables

– Eight Literals
– Expression has five terms including four AND terms and the OR
term
that combines the first-level AND terms.

4
 BOOLEAN ALGEBRA
POSTULATES
OR
operation
X Y X+0 X+Y Y+X X’ X+X’
• Identity 0 0 0 0 0 1 1
Elements 0 1 0 1 1 1 1
› P2a: X+0=X 1 0 1 1 1 0 1
› P2b: X•1=X 1 1 1 1 1 0 1
• Commutativit
› P3a:
X+Y=Y+X y
AND
• Complement
› P3b:
operation
s›X•Y=Y•X
P6a:
X+X’=1 X Y X•1 X•Y Y•X X’ X•X’
› P6b: 0 0 0 0 0 1 0
X•X’=0 0 1 0 0 0 1 0
1 0 1 0 0 0 0
1 1 1 1 1 0 0

5
 BOOLEAN ALGEBRA
POSTULATES
• Associativity
› P4a: (X+Y)+Z=X+
(Y+Z)
› P4b:
(X•Y)•Z=X•(Y•Z)
X Y X+Y (X+Y)+Z Y+Z X+(Y+Z) X•Y (X•Y)•Z Y•Z X•(Y•Z)
Z
0 0 0 0 0 0 0 0 0 0
0
0 0 0 1 1 1 0 0 0 0
1
0 1 1 1 1 1 0 0 0 0
0
0 1 1 1 1 1 0 0 1 0
1
1 0 1 1 0 1 0 0 0 0
0
1 0 1 1 1 1 0 0 0 0
1
6
 BOOLEAN ALGEBRA
POSTULATES
• Distributivity
› P5a: X+(Y•Z) =
(X+Y)•(X+Z)
› P5b: X•(Y+Z) = (X•Y)+
(X•Z)
(X+Y)• X+ X•Y+ X•
X Y Z X+Y X+Z (X+Z) Y•Z (Y•Z) X•Y X•Z X•Z Y+Z (Y+Z)
0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0 1 0
0 1 0 1 0 0 0 0 0 0 0 1 0
0 1 1 1 1 1 1 1 0 0 0 1 0
1 0 0 1 1 1 0 1 0 0 0 0 0
1 0 1 1 1 1 0 1 0 1 1 1 1
1 1 0 1 1 1 0 1 1 0 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1

7
 BOOLEAN ALGEBRA
THEOREMS
• Idempotency
› T1a:
X+X=X
› T1b:
X•X=X
› T2a:
• Null elements
X+1=1 OR
X Y X+Y
AND X•Y X+X X•X X+1 X•0 X’ X’’
› T2b:
• Involution 0 0 0 0 0 0 1 0 1 0
X•0=0
› T3: 0 1 1 0 0 0 1 0 1 0
(X’)’=X 1 0 1 0 1 1 1 0 0 1
1 1 1 1 1 1 1 0 0 1

8
 BOOLEAN ALGEBRA
•
THEOREMS
Absorption (aka
covering)
› T4a: X+(X•Y)=X
› T4b: X•(X+Y)=X
› T5a: X+
(X’•Y)=X+Y
› T5b:
X•(X’+Y)=X•Y
OR
AND X+ X• X+ X•
X Y X+Y X•Y (X•Y) (X+Y) X’ X’•Y (X’•Y) X’+Y (X’+Y)
0 0 0 0 0 0 1 0 0 1 0
0 1 1 0 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0 1 0 0
1 1 1 1 1 1 0 0 1 1 1

9
BOOLEAN ALGEBRA
THEOREMS

• Absorption (aka
combining)
› T6a: (X•Y)+
(X•Y’)=X
› T6b:
(X+Y)•(X+Y’)=X
(X•Y)+ (X+Y)•
X X+Y X•Y Y’ X•Y’ (X•Y’) X+Y’ (X+Y’)
Y
OR AND
0 0 0 1 0 0 1 0
0
0 1 0 0 0 0 0 0
1
1 1 0 1 1 1 1 1
0
1 1 1 0 0 1 1 1
1

10
 BOOLEAN ALGEBRA
THEOREMS
• Absorption (aka combining)
› T7a: (X•Y)+(X•Y’•Z)=(X•Y)+
(X•Z)
› T7b: (X+Y)•(X+Y’+Z) =
(X+Y)•(X+Z) (XY)+ (XY)+ X+Y’ (X+Y)• (X+Y)•
X Y Z Y’ XY XY’Z (XY’Z) XZ (XZ) X+Y +Z (X+Y’+Z X+Z (X+Z)
)
0 0 0 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 0 0 0 0 0 0 1 0 1 0
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1 1 1 1 1
1 0 1 1 0 1 1 1 1 1 1 1 1 1
1 1 0 0 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 0 1 1 1 1 1 1 1 1

11
 BOOLEAN ALGEBRA
• THEOREMS
DeMorgan’s theorem (very
important!)
› • X+Y T8a:=(X+Y)’= X’•Y’
break (or connect) the bar & change
X•Y sign the
› T8b: (X•Y)’=
X’+Y’• X•Y = X+Y break (or connect) the bar &
change the
sign
› Generalized DeMorgan’s theorem:
• GT8a: (X1+X2+…+Xn-1+Xn)’= X1’•X2’•…•Xn-1’•Xn’
• GT8b: (X1•X2•…•Xn-1•Xn)’= X1’+X2’+…+Xn-1’+Xn’

OR AND
X Y X+Y X•Y X’ Y’ (X+Y)’ X’•Y’ (X•Y)’ X’+Y’
0 0 0 0 1 1 1 1 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 1 0 0 0 0 0 0

12
 BOOLEAN ALGEBRA
•
THEOREMS
Consensus Theorem
› T9a: (X•Y)+(X’•Z)+(Y•Z) = (X•Y)+
(X’•Z)
› T9b: (X+Y)•(X’+Z)•(Y+Z) =
(X+Y)•(X’+Z) (XY)+ (X+Y)•
(X’Z)+ (XY) (X’+Z)• (X+Y)
X Y Z X’ XY X’Z YZ (YZ) + X+Y X’+Z Y+Z (Y+Z) •
(X’Z) (X’+Z)
0 0 0 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 0 1 0 1 1 0 1 1 0 0
0 1 0 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 0 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 0 0 0 0 1 1 1 1 1
1 1 0 0 1 0 0 1 1 1 0 1 0 0
1 1 1 0 1 0 1 1 1 1 1 1 1 1

13
 MORE
THEOREMS?
• Shannon’s expansion theorem (also very important!)
• › T10a: f(X1,X2,…,Xn-1,Xn)=
• (X1’•f(0,X2,…,Xn-1,Xn))+(X1•f(1,X2,…,Xn-1,Xn))
• Can be taken further:
• - f(X1,X2,…,Xn-1,Xn)= (X1’•X2’•f(0,0,…,Xn-1,Xn))
• + (X1•X2’•f(1,0,…,Xn-1,Xn)) +
(X1’•X2•f(0,1,…,Xn-1,Xn))
• +(X1•X2•f(1,1,…,Xn-1,Xn))
• Can be taken even further:
• - f(X1,X2,…,Xn-1,Xn)= (X1’•X2’•…•Xn-
1’•Xn’•f(0,0,…,0,0))

• + (X1•X2’•…•Xn-1’•Xn’•f(1,0,…,0,0)) +
…
• + (X1•X2•…•Xn-1•Xn•f(1,1,…,1,1))
• › T10b: f(X1,X2,…,Xn-1,Xn)=
• (X1+f(0,X2,…,Xn-1,Xn))•(X1’+f(1,X2,…,Xn-1,Xn))
• Can be taken further as in the case of T10a
• We’ll see significance of Shannon’s expansion theorem later 14
 BOOLEAN ALGEBRA
THEOREMS
• Idempotency
› T1a:
X+X=X
› T1b:
X•X=X
› T2a:
• Null elements
X+1=1 OR
X Y X+Y
AND X•Y X+X X•X X+1 X•0 X’ X’’
› T2b:
• Involution 0 0 0 0 0 0 1 0 1 0
X•0=0
› T3: 0 1 1 0 0 0 1 0 1 0
(X’)’=X 1 0 1 0 1 1 1 0 0 1
1 1 1 1 1 1 1 0 0 1

15
 BOOLEAN ALGEBRA
•
THEOREMS
Absorption (aka
covering)
› T4a: X+(X•Y)=X
› T4b: X•(X+Y)=X
› T5a: X+
(X’•Y)=X+Y
› T5b:
X•(X’+Y)=X•Y
OR
AND X+ X• X+ X•
X Y X+Y X•Y (X•Y) (X+Y) X’ X’•Y (X’•Y) X’+Y (X’+Y)
0 0 0 0 0 0 1 0 0 1 0
0 1 1 0 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0 1 0 0
1 1 1 1 1 1 0 0 1 1 1

16
BOOLEAN ALGEBRA
THEOREMS

• Absorption (aka
combining)
› T6a: (X•Y)+
(X•Y’)=X
› T6b:
(X+Y)•(X+Y’)=X
(X•Y)+ (X+Y)•
X X+Y X•Y Y’ X•Y’ (X•Y’) X+Y’ (X+Y’)
Y
OR AND
0 0 0 1 0 0 1 0
0
0 1 0 0 0 0 0 0
1
1 1 0 1 1 1 1 1
0
1 1 1 0 0 1 1 1
1
17
 BOOLEAN ALGEBRA
THEOREMS
• Absorption (aka combining)
› T7a: (X•Y)+(X•Y’•Z)=(X•Y)+
(X•Z)
› T7b: (X+Y)•(X+Y’+Z) =
(X+Y)•(X+Z) (XY)+ (XY)+ X+Y’ (X+Y)• (X+Y)•
X Y Z Y’ XY XY’Z (XY’Z) XZ (XZ) X+Y +Z (X+Y’+Z X+Z (X+Z)
)
0 0 0 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 0 0 0 0 0 0 1 0 1 0
0 1 0 0 0 0 0 0 0 1 0 0 0 0
0 1 1 0 0 0 0 0 0 1 1 1 1 1
1 0 0 1 0 0 0 0 0 1 1 1 1 1
1 0 1 1 0 1 1 1 1 1 1 1 1 1
1 1 0 0 1 0 1 0 1 1 1 1 1 1
1 1 1 0 1 0 1 1 1 1 1 1 1 1

18
 BOOLEAN ALGEBRA
• THEOREMS
DeMorgan’s theorem (very
important!)
› • X+Y T8a:=(X+Y)’= X’•Y’
break (or connect) the bar & change
X•Y sign the
› T8b: (X•Y)’=
X’+Y’• X•Y = X+Y break (or connect) the bar &
change the
sign
› Generalized DeMorgan’s theorem:
• GT8a: (X1+X2+…+Xn-1+Xn)’= X1’•X2’•…•Xn-1’•Xn’
• GT8b: (X1•X2•…•Xn-1•Xn)’= X1’+X2’+…+Xn-1’+Xn’

XORY X+Y AND

X•Y X’ Y’ (X+Y)’ X’•Y’ (X•Y)’ X’+Y’
0 0 0 0 1 1 1 1 1 1
0 1 1 0 1 0 0 0 1 1
1 0 1 0 0 1 0 0 1 1
1 1 1 1 0 0 0 0 0 0

19
 BOOLEAN ALGEBRA
•
THEOREMS
Consensus Theorem
› T9a: (X•Y)+(X’•Z)+(Y•Z) = (X•Y)+
(X’•Z)
› T9b: (X+Y)•(X’+Z)•(Y+Z) =
(X+Y)•(X’+Z) (XY)+ (X+Y)•
(X’Z)+ (XY) (X’+Z)• (X+Y)
X Y Z X’ XY X’Z YZ (YZ) + X+Y X’+Z Y+Z (Y+Z) •
(X’Z) (X’+Z)
0 0 0 1 0 0 0 0 0 0 1 0 0 0
0 0 1 1 0 1 0 1 1 0 1 1 0 0
0 1 0 1 0 0 0 0 0 1 1 1 1 1
0 1 1 1 0 1 1 1 1 1 1 1 1 1
1 0 0 0 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 0 0 0 0 1 1 1 1 1
1 1 0 0 1 0 0 1 1 1 0 1 0 0
1 1 1 0 1 0 1 1 1 1 1 1 1 1

20
 MORE
THEOREMS?
• Shannon’s expansion theorem (also very important!)
• › T10a: f(X1,X2,…,Xn-1,Xn)=
• (X1’•f(0,X2,…,Xn-1,Xn))+(X1•f(1,X2,…,Xn-1,Xn))
• Can be taken further:
• - f(X1,X2,…,Xn-1,Xn)= (X1’•X2’•f(0,0,…,Xn-1,Xn))
• + (X1•X2’•f(1,0,…,Xn-1,Xn)) +
(X1’•X2•f(0,1,…,Xn-1,Xn))
• +(X1•X2•f(1,1,…,Xn-1,Xn))
• Can be taken even further:
• - f(X1,X2,…,Xn-1,Xn)= (X1’•X2’•…•Xn-
1’•Xn’•f(0,0,…,0,0))

• + (X1•X2’•…•Xn-1’•Xn’•f(1,0,…,0,0)) +
…
• + (X1•X2•…•Xn-1•Xn•f(1,1,…,1,1))
• › T10b: f(X1,X2,…,Xn-1,Xn)=
• (X1+f(0,X2,…,Xn-1,Xn))•(X1’+f(1,X2,…,Xn-1,Xn))
• Can be taken further as in the case of T10a
• We’ll see significance of Shannon’s expansion theorem later 21
 SWITCHING
FUNCTIONS
• Objective:
Understand the logic functions of the digital circuits

• Course Outcomes(CAEC020.05):
Describe minimization techniques and other
optimization techniques for Boolean formulas in general
and digital circuits.

22
 SWITCHING
FUNCTIONs
• For n variables, there are 2n possible combinations of
values
› From all 0s to all 1s

• There are 2 possible values for the output of a function of a given

combination of values of n variables
› 0 and 1

• There are 22n different switching functions for

n variables

23
 SWITCHING FUNCTION
EXAMPLES

• n=0 (no inputs) 22n = 220 = 21 switc

output
=2 h
function
n=
› Output can be either 0 or 1 0
• n=1 (1 input, A) 22n = 221 = 22
=4
› Output can be 0, 1, A, or A’
f0 =
A switch outpu A f0 f1 f2 f3 0 f1
function t 0 0 1 0 1 = A’
n=1 1 0 0 1
f32==
1 1A

24
 SWITCHING FUNCTION
EXAMPLES

• n=2 (2 inputs, A and 22n = 222 = 24 =16

B)
A A
switch output f f f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 0
B 00 11 0 10 10 1 0 1 0 1 0 1 0 01
B function 01 0 0 1 10 01 1 0 0 1 1 0 0 1 1
n=2
10 0 0 0 01 11 1 0 0 0 0 1 1 1 1
11 0 0 0 00 00 0 1 1 1 1 1 1 1 1
f0 = 0 logic 0
f1 = A’B’= (A+B)’ NOT-OR or NOR
f2 =A’B
f3 = A’B’+A’B = A’(B’+B) =A’ invertA
Most frequently used Less frequentlyused Least frequentlyused
5

25
 SWITCHING FUNCTION
EXAMPLES

• n=2 (2 inputs, Aand B) 22n = 222 = 24 =

A 16
switch
A f f f f f f f f f f f f f f f f
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0
output B 0 1 0 10 10 1 0 1 0 1 0 1
B function 0 1 01 01 01 1 0 0 1 1 0 0 1 1
n=2 01 0 0 0 01 11 1 0 0 0 0 1 1 1 1
1 10 0 0 0 0 0 00 0 1 1 1 1 1 1 1 1
f4 =AB’
f5 = A’B’+AB’= (A’+A)B’= B’ invert B
f6 =A’B+AB’ exclusive-OR
f7 = A’B’+A’B+AB’=A’(B’+B)+(A’+A)B’
= A’+B’ =(AB)’ NOT-AND or NAND
Most frequently used Less Least frequentlyused
6
frequentlyused
26
 SWITCHING FUNCTION
EXAMPLES

• n=2 (2 inputs, A andB) 22n = 222 = 24 =

A 16
switch
A f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15
output B 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
B function 0 01 10 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
n=2
10 0 0 0 01 11 1 0 0 0 0 1 1 1 1
11 0 0 0 00 00 0 1 1 1 1 1 1 1 1
f8 =AB AND
f9 =A’B’+AB exclusive-
f10 = A’B+AB = (A’+A)B =B NOR buffer B
f11 = A’B’+A’B+AB = A’(B’+B)+(A’+A)B=A’+B
Most frequently used Less frequentlyused Least frequentlyused
7

27
 SWITCHING FUNCTION
EXAMPLES

• n=2 (2 inputs, A andB) 22n = 222 = 24 =

A 16
switch
A f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 f10 f11 f12 f13 f14 f15 0 0
output B 0 1 0 10 10
B function
0 1 0 0 1 110 0 1 10 0 0 11 1 0 00 1 1
n=2
1 0 0 0 0 011 1 1 10 0 0 01 0 1 10 1 1
1 1 0 0 0 010 0 0 0 1 1 1 1 1 1 1 1
f12 = AB’+AB = A(B’+B) = A bufferA
f13 = A’B’+AB’+AB = A(B’+B)+A’B’= A+A’B’=A+B’
f14 = A’B+AB’+AB = A(B’+B)+(A’+A)B =A+B OR
f15 = A’B’+A’B+AB’+AB =A’(B’+B)+A(B’+B)
= A’+A = 1 logic
Most frequently used Less frequentlyused Least frequentlyused
1
8

28
 CANONICAL AND STANDERED
FORMS
• Logical functions are generally expressed in terms of different
combinations of logical variables with their true forms as well as the
complement forms. Binary logic values obtained by the logical functions
and logic variables are in binary form. An arbitrary logic function can be
expressed in the following forms.

• Sum of the Products (SOP)

• Product of the Sums (POS)

29
 CANONICAL AND STANDERED
FORMS
• Product Term: In Boolean algebra, the logical product of several
variables on which a function depends is considered to be a product
term. In other words, the AND function is referred to as a product term
or standard product.
• Sum Term: An OR function is referred to as a sum term

• Sum of Products (SOP): The logical sum of two or more logical

product
terms is referred to as a sum of products expression

• Product of Sums (POS): Similarly, the logical product of two or

more
logical sum terms is called a product of sums expression

• Standard form: The standard form of the Boolean function is when it

is 30
expressed in sum of the products or product of the sums fashion
 CANONICAL AND STANDERED
FORMS
• Nonstandard Form: Boolean functions are also sometimes expressed
in nonstandard forms like , which is neither a
sum of products form nor a product of sums form.

• Minterm: A product term containing all n variables of the function in

either true or complemented form is called the minterm. Each minterm is
obtained by an AND operation of the variables in their true form or
complemented form.

• Maxterm: A sum term containing all n variables of the function in

either true or complemented form is called the Maxterm. Each Maxterm
is obtained by an OR operation of the variables in their true form or
complemented form.

31
 CANONICAL SUM OF
PRODUCTS

• When a Boolean function is expressed as the logical sum of all the

minterms from the rows of a truth table, for which the value of the
function is 1, it is referred to as the canonical sum of product expression
• For example, if the canonical sum of product form of a three-variable logic
function F has the minterms , , and , this can be expressed as the sum of
the decimal codes corresponding to these minterms as below..

32
 CANONICAL SUM OF
PRODUCTS
• The canonical sum of products form of a logic function can be obtained
by
using the following procedure:
• Check each term in the given logic function.
Retain if it is a
minterm, continue to examine the next term in the same manner.

• Examine for the variables that are missing in each product which
is not a minterm. If the missing variable in the minterm is X,
multiply that minterm with (X+X’).

• Multiply all the products and discard the redundant terms.

33
 CANONICAL SUM OF
PRODUCTS
• Example: Obtain the canonical sum of product form of the
following
function

• Solution:

• Hence the canonical sum of the product expression of the given function
is

34
 CANONICAL SUM OF
PRODUCTS
The product of sums form is a method (or form) of simplifying the Boolean
expressions of logic gates. In this POS form, all the variables are ORed, i.e. written
as sums to form sum terms. All these sum terms are ANDed (multiplied) together to
get the product-of-sum form. This form is exactly opposite to the SOP form. So this
can also be said as ―Dual of SOP form‖.

(A+B) * (A + B + C) * (C

+D) (A+B) ̅ * (C + D + E )̅

35
 CANONICAL SUM OF
PRODUCTS
POS form can be obtained by
• Writing an OR term for each input combination, which produces LOW
output.
• Writing the input variables if the value is 0, and write the complement of
the variable if its value is AND the OR terms to obtain the output
function.

36
 CANONICAL SUM OF
PRODUCTS
Example:
Boolean expression for majority function F = (A + B + C) (A + B + C ‘) (A + B’ + C) (A’ + B +
C)

Now write the input variables combination with high output. F = AB + BC +

AC.

37
 KARANAUGH
MAP
• Boolean algebra helps us simplify expressions and circuits
• Karnaugh Map: A graphical technique for simplifying a
Boolean
expression into either form:
– minimal sum of products (MSP)
– minimal product of sums (MPS)
• Goal of the simplification.
– There are a minimal number of product/sumterms
– Each term has a minimal number of literals

38
 KARANAUGH
MAP
 A two-variable function has four possible minterms. We can
re- arrange
these minterms into a Karnaugh map
x y m i n t er m Y
0 0 x’ y’
0 1
0 1 x’ y x’y’ x’y
0
1 0 xy’ X
1 xy’ xy
1 1 xy

 Now we can easily see which minterms contain

commonliterals
◦ Minterms on the left and right sides contain y’ and y respectively
◦ Minterms in the top and bottom rows containY’x’ and Yx
respectively 0 1
X’ x’y’ x’y
0 x’y’ Y x’y
X
1 xy’ xy X xy’ xy

85
5
 KARANAUGH
•
MAP
Make as few rectangles as possible, to minimize the number of
products in the final expression.
• Make each rectangle as large as possible, to minimize the
number of literals in each term.
• Rectangles can be overlapped, if that makes them larger
• The most difficult step is grouping together all the 1s in the K-
map
• Make rectangles around groups of one, two, four or eight 1s
• All of the 1s in the map should be
included in at least one
rectangle. Do not include any Y
of the 0s
• Each group corresponds
0 1 to
0 one0productterm
X 0 1 1 1
Z

86
6
 KARANAUGH
MAP
• Maxterms are grouped to find minimal
PoS
expressio 00 01
yz
11 10
n 0
x x +y+z x+y+z’ x+y’+z’ x+y’+z
1 x’ +y+z x’+y+z’ x’+y’+z’ x’+y’+
z

87
7
 3 Variable k-
Map
• Let’s consider simplifying f(x,y,z) = xy + y’z + xz
• You should convert the expression into a sum of
mintermsform,
• The easiest way to do this is to make a truth table for the
function, and then read off the minterms
• You can either write out the literals or use the minterm
shorthand
• Herex
isy thez truth table and sum of minterms for our
f( x, y, z)
example:
0 0 0 0
f(x,y,z) = x’y’z + +
0 0 1 1
xy’z + xyz xyz’
0 1 0 0
0 1 1 0
= m1 + m5 + m6 + m7
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 1

83
8
 3 VARIABLE K-
MAP
 For a three-variable expression with inputs x, y, z, the
arrangement of
YZ
minterms is more tricky:
YZ 00 01 11
0 100
m m1 m3 m2
00 0 1 1 X
x’y’z’ 1
x’y’z 1
x’yz 0
x’yz’ 1 m4 m5 m7 m6
0
X
1 xy’z’ xy’z xyz xyz’
Y
Y m0 m1 m3 m2
x’y’z’ x’y’z x’yz x’yz’ X m4 m5 m7 m6
X xy’z’ xy’z xyz xyz’ Z
Z

84
9
 3-VARIABLE K-
• MAP
Here is the filled in K-map, with all groups shown
– The magenta and green groups overlap, which makes
eachof them as
large as possible
– Minterm m6 is in a group all by itslonesome
Y
0 1 1 0
X 0 1 0 1
Z

• The final MSP here is x’z + y’z +

xyz’

90
 3-VARIABLE K-
MAP
• There may not necessarily be a unique MSP. The K-map below
yields
two
valid and equivalent MSPs, because there are two possible
waysto Y
0 1 0 1
include minterm m7 X 0 1 1 1
Z

Y Y
0 1 0 1 0 1 0 1
X 0 1 1 1 X 0 1 1 1
Z Z

y’z + yz’ + xy

y’z + yz’ + xz

• Remember that overlapping groups is possible, as shown

96
above 1
 3-VARIABLE K-
MAP
• Maxterms are grouped to find minimal
PoS
expressio 00 01
yz
11 10
n 0
x x +y+z x+y+z’ x+y’+z’ x+y’+z
1 x’ +y+z x’+y+z’ x’+y’+z’ x’+y’+
z

97
2
 4-VARIABLE K-
MAP
• We can do four-variable expressions too!
– The minterms in the third and fourth columns, and in
thethird
and
fourth rows, are switched around.
– Again, this ensures that adjacent squares have common
literals

• Grouping minterms is similar to the three-variable case, but:

– You can have rectangular groups of 1, 2, 4, 8 or 16
minterms
– You can wrap around all four sides

93
 4-VARIABLE K-
MAP

Y Y
w’x’y’z’ w’x’y’z w’x’yz w’x’yz’ m0 m1 m3 m2
w’xy’z’ w’xy’z w’xyz w’xyz’ m4 m5 m7 m6
X X
wxy’z’ wxy’z wxyz wxyz’ m12 m13 m15 m14
W W
wx’y’z’ wx’y’z wx’yz wx’yz’ m8 m9 m11 m10
Z
Z

94
4
 4-VARIABLE K-
• The MAP
Y
o her e’sthe K map
isalread y a sum of minterms, -
ion Y
express
1 0 0 1
s m0 m1 m3 m2
:
0 1 0 0 m4 m5 m7 m6
X X
0 1 0 0 m12 m13 m15 m14
W W
1 0 0 1 m8 m9 m11 m10
Z
Z
• We can make the following groups, resulting in the MSP x’z’ +
xy’z Y Y
1 0 0 w’x’y’z’ w’x’y’z w’x’yz w’x’yz’
0 1
1 0 w’xy’z’ w’xy’z w’xyz w’xyz’
0 X X
wxy’z’ wxy’z wxyz wxyz’
W 0 1 0 W
1 0 0 wx’y’z’ wx’y’z wx’yz wx’yz’
0
1 Z Z

Example: Simplify
m0+m2+m5+m8+m10+m13

95
5
 4-VARIABLE K-
MAP
• F(W,X,Y,Z)= ∏ M(0,1,2,4,5)
x +y+z x+y+ x+y’+z x+y’+
0 z’ ’ z
x y
x’ x’+y+0 zx’+y’+z 1
1 0+0y+z x’+y’+z
10
z1’ ’1

F(W,X,Y,Z)= Y . (X + Z)

0 0 0 0
00 01 z 1
x y 11
1 0 1 1
100

96
6
 5-VARIABLE K-
MAP
• Objective:
Understand the 5-Variable K-map
• Course Outcomes(CAEC020.06):
Evaluate the functions using various types of minimizing
algorithms like Karanaugh map method.

97
 5-variable K-
map

V= 1Y
V= 0 Y
m16 m17 m19 m8
m 0 m 1 m 3 m 2

m 4 m 5 m 7 m 6 m20 m21 m23 m22 X

X
m 12 m 13 m 15 m 14 m28 m29 m31 m30
W W
m 8 m 9 m 11 m 10 m25
m24 m27 m26
Z
Z

93
8
 5-VARIABLE K-
•
MAP
In our example, we can write f(x,y,z) in two
equivalentways
f(x,y,z) = x’y’z + xy’z + xyz’
f(x,y,z) = m1 + m5 + m +
+ 6 7

xyz Y m Y
x’y’z’ x’y’z x’yz x’yz’ m0 m1 m3 m2
X m4 m5 m7 m6
X xy’z’ xy’z xyz xyz’
Z
Z
• In either case, the resulting K-map is shown
below
0 1 0 Y 0
X 0 1 1 1
Z

94
9
 5-VARIABLE K-
MAP

1 1 1

1 1 1 1 1

1 1 1 1 1

1
V= V= 1
0
f = XZ’
Σm(4,6,12,14,20,22,28,30)
+ V’W’Y’ Σm(0,1,4,5)
+ W’Y’Z’ Σm(0,4,16,20)
+ VWXY Σm(30,31)
+ m11
V’WX’YZ
105
0
 DON’T CARE
CONDITION
• You don’t always need all 2n input combinations in ann-
variable
function

– If you can guarantee that certain input combinations

never
occur x
0
y
0
z
0
f(x,y,z)
0

– If some outputs aren’t

0
0
0
1
used
1
0
in the
1
X
rest of the circuit
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 X
1 1 1 1

• We mark don’t-care outputs in truth tables and K-maps with

Xs.

103
1
 DON’T CARE
CONDITION
• Find a MSP for

f(w,x,y,z) =  m(0,2,4,5,8,14,15), d(w,x,y,z) =  m(7,10,13)

This notation means that input combinations wxyz = 0111, 1010

and 1101(corresponding to minterms m7, m10 and m13) are
unused.
Y
1 0 0 1
1 1 x 0
X
0 x 1 1
W
1 0 0 x
Z

104
1
 DON’T CARE
CONDITIONS
• Find a MSP for:
f(w,x,y,z) =  m(0,2,4,5,8,14,15), d(w,x,y,z) =
 m(7,10,13)
1 Y
1
X
1 x 1 1x 1
W
1 x
Z

f(w,x,y,z)= x’z’ + w’xy’

+ wxy

105
1
 NAND NOR
•
IMPLEMENTATION
The objectives of this lesson are to learn about:
1. Universal gates - NAND and NOR.
2. How to implement NOT, AND, and OR gate using NAND gates
only.
3. How to implement NOT, AND, and OR gate using NOR gates
only.
4. Equivalentgates.

58
NAND NOR
IMPLEMENTATION

59
60
NAND NOR
IMPLEMENTATION

61
NAND NOR
IMPLEMENTATION

62
 TWO LEVEL
Implementation
OR NAND
Function:
Implement the following
function
Since ‘F’ is in POS form Z can be implemented by using NORNOR
circuit. Similarly complementing the output we can get F,or by using
NOR –OR Circuit as shown in figure

63
TWO LEVEL
Implementation

64
 TWO LEVEL
Implementation

It can also be implemented using OR-NAND circuit as it is

equivalent
to NOR-OR circuit

65
 Two Level
Implementation
• Example1: implement the following function F = AB
+CD
• The implementation of Boolean functions with NAND gates
requires that the functions be in
• sum of products (SOP) form.
• The Rule
• This function can This function can be implemented bythree
different ways as shown in the circuit diagram a, b, c

66
 Two Level
Implementation
Example 2: Consider the following Boolean function,
implement the
circuit diagram by using
multilevel NOR gate. F = (AB ′ + A′B )i(C + D′)

67
 Two Level
Implementation
Exclusive‐OR (XOR)
Function:
XOR: x y = xy’ + x’y

68
 Two Level
Implementation
Exclusive‐NOR =
equivalence
(x y)’ = (xy’ + x’y)’
= (x’ + y)(x + y’) = x’y’ + xy

69
TWO LEVEL
Implementation

70
 TWO LEVEL
Implementation
OR NAND
Function:
Implement the following
function
Since ‘F’ is in POS form Z can be implemented by using NORNOR
circuit. Similarly complementing the output we can get F,or by using
NOR –OR Circuit as shown in figure

71
TWO LEVEL
Implementation

72
 TWO LEVEL
Implementation

It can also be implemented using OR-NAND circuit as it is

equivalent
to NOR-OR circuit

73
 Two Level
Implementation
• Example1: implement the following function F = AB
+CD
• The implementation of Boolean functions with NAND gates
requires
that the functions be in
• sum of products (SOP) form.
• The Rule
• This function can This function can be implemented by
three different ways as shown in the circuit diagram a, b,
c

74
 Two Level
Implementation
Example 2: Consider the following Boolean function,
implement the
circuit diagram by using
multilevel NOR gate. F = (AB ′ + A′B )i(C + D′)

75
 Two Level
Implementation
Exclusive‐OR (XOR)
Function:
XOR: xy’ + x’y

76
 Two Level
Implementation
Exclusive‐NOR =
equivalence
= (x’ + y)(x + y’) = x’y’ + xy

77
COMBINATIONAL
CIRCUITS

UNIT 3

COMBINATIONA
L CIRCUITS

78
 Combinational
Circuits
• Combinational circuit is a circuit in which we combine the
different gates in the circuit, for example encoder, decoder,
multiplexer and demultiplexer.
Some of the characteristics of combinational circuits are following:
• The output of combinational circuit at any instant of time,
depends
only on the levels present at inputterminals.
• The combinational circuit do not use any memory. The
previousstate
of input does not have any effect on the present state of the circuit.
• A combinational circuit can have an n number of inputs and m
number
of outputs.

79
 COMBINATIONAL
• CIRCUITS
Block diagram:
possible combinations of input
values.

• Specific functions :of combinationalcircuits

Adders,subtractors,multiplexers,comprators,encoder,Decoder.
MSI Circuits and standard cells

80
 ANALYSIS
PROCEDURE
Analysis procedure
To obtain the output Boolean functions from a logic diagram,
proceed as follows:
1. Label all gate outputs that are a function of input variables with
arbitrary symbols. Determine the Boolean functions for
eachgate output.
2. Label the gates that are a function of input variables and
previously labeled gates with other arbitrary symbols. Find
the Boolean functions for these gates.
3. Repeat the process outlined in step 2 until the outputs of
the
circuit are obtained.

81
 DESIGN
PROCEDURE
Design Procedure
1.The problem is stated
2.The number of available input variables and requiredoutput
variables is determined.
3.The input and output variables are assigned lettersymbols.
4.The truth table that defines the required relationship
betweeninputs
and outputs is derived.
5.The simplified Boolean function for each output isobtained.
6.The logic diagram is drawn.

82
 BINARY
ADDERS ADDERS
Half Adder
A Half Adder is a combinational circuit with two binary inputs (augends
and addend bits and two binary outputs (sum and carry bits.) It adds
the two inputs (A and B) and produces the sum (S) and the carry (C)
bits.

Fig 1:Block Fig 2:Truth

diagram table
Sum=A′B+AB′=A
B
Carry=AB

83
 BINARY
ADDERS
Full Adder
The full-adder adds the bits A and B and the carry from the
previous column called the carry-in Cin and outputs the sum bit S
and the carry bit called the carry-out Cout .

Fig 3: block Fig 4:Truth

diagram table

84
 BINARY
SUBTRACTORS
Half Subtractor
A Half-subtractor is a combinational circuit with two inputs A and
B
and two outputs difference(d) and barrow(b).

Fig 5:Block Fig 6: Truth

diagram table
d=A′B+AB′=A
B
b=A′B

85
 BINARY
SUBTRACTORS
Full subtractor
The full subtractor perform subtraction of three input bits: the
minuend , subtrahend , and borrow in and generates two output
bits difference and borrow out .

Fig 7:Block Fig 8: Truth

diagram table

86
 PARALLEL ADDER AND
SUBTRACTOR
A binary parallel adder is a digital circuit that adds two binary
numbers in parallel form and produces the arithmetic sum of
those numbers in parallel form

Fig 9:parallel
adder

Fig 10:parallel
subtractor
87
 CARRY LOOK-A- HEAD
• ADDER
In parallel-adder , the speed with which an addition can be
performed is governed by the time required for the carries
to propagate or ripple through all of the stages of the
adder.

• The look-ahead carry adder speeds up the process by

eliminating
this ripple carry delay.

88
CARRY LOOK-A- HEAD
ADDER

Fig:1 block
diagram

89
 BINARY
MULTIPLIER
A binary multiplier is an electronic circuit used in digital electronics,
such as a computer, to multiply two binary numbers. It is built
using binary adders.
Example: (101 x 011)
Partial products are: 101 × 1, 101 × 1, and 101 × 0
1 0 1
× 1 1

0
1 0 1
1 0 1
0 0 0
0 0 1 1 1 1

90
 BINARY
MULTIPLIER
• We can also make an n × m “block” multiplier and use that
to
form partial products.
• Example: 2 × 2 – The logic equations for each partial-
product
binary digit are shown below
• We need to "add" the columns to get the product bits P0,
P1,
P2, and P3.

91
BINARY
MULTIPLIER
A0
B1 B0

A1
B1 B0

HA HA

P3 P2 P1 P0

Fig 1: 2 x 2 multiplier
array

92
 MAGNITUDE
COMPARATOR
Magnitude comparator takes two numbers as input in binary form
and determines whether one number is greater than, less than or
equal to the other number.
1-Bit Magnitude Comparator
A comparator used to compare two bits is called a single bit
comparator.

Fig :1 Block
diagram

93
MAGNITUDE
COMPARATOR

Fig 2:Logic diagram of 1-bit

comparator

94
 MAGNITUDE
COMPARATOR
• 2 Bit magnitude
comparator

Fig :3 Block diagram

Fig :4 Truth
table

95
MAGNITUDE
COMPARATOR

Fig 5:Logic diagram of 2-bit

comparator

96
 BCD
BCD Adder ADDER
• Perform the addition of two decimal digits in BCD, together with
an
input carry from a previousstage.
• When the sum is 9 or less, the sum is in proper BCD form
and no correction is needed.
• When the sum of two digits is greater than 9, a correction of
0110 should be added to that sum, to produce the proper BCD
result. This will produce a carry to be added to the next
decimal position.

97
 DECOD
ER
• A binary decoder is a combinational logic circuit that converts
binary information from the n coded inputs to a maximum of
2nunique outputs.
• We have following types of decoders 2x4,3x8,4x16….
2x4 decoder

Fig 1: Block Fig 2:Truth

diagram table

98
 DECODE
RS
Higher order decoder implementation using lower
order.
Ex:4x16 decoder using 3x8 decoders

99
 ENCOD
•
ERS
An Encoder is a combinational circuit that performs the
reverse operation of Decoder. It has maximum of 2n input
lines and ‘n’ output lines.
• It will produce a binary code equivalent to the input, which
is active
High.

Fig 1:block diagram of 4x2

encoder

100
 ENCOD
ERS
Octal to binary
encoder

Fig 2:Truth Fig 3: Logic

table diagram

101
 ENCOD
ER
Priority encoder
A 4 to 2 priority encoder has four inputs Y3, Y2, Y1& Y0and
two outputs A1 & A0. Here, the input, Y3has the highest
priority, whereas the input, Y0has the lowestpriority.

Fig 4:Truth
table
102
 MULTIPLE
XERS
• Multiplexer is a combinational circuit that has maximum of 2n data
inputs, ‘n’ selection lines and single output line. One of these data
inputs will be connected to the output based on the values of
selection lines.
• We have different types of multiplexers 2x1,4x1,8x1,16x1,32x1……

Fig 1: Block Fig 2: Truth

diagram table
103
 MULTIPLEX
ERS

Fig 3: Logic diagram

• Now, let us implement the higher-order Multiplexer
using lower-order Multiplexers.

104
 MULTIPLEX
• Ex: 8x1 ERS
Multiplexer

Fig 3: 8x1
Multiplexerdiagram
105
 MULTIPLEX
ERS
• Implementation of Boolean function using multiplexer
• f(A1 , A2 , A3 ) =Σ(3,5,6,7) implementation using 8x1
mux

106
 MULTIPLE
XERS
f(A1 , A2 , A3 ) =Σ(3,5,6,7) implementation using 4x1
mux
Method:1

Fig 1: Truth
table

107
 MULTIPLE
XERS
Method
:2

Fig 1: Truth
table

108
 DEMULTIPLE
XER
• A demultiplexer is a device that takes a single input line and
routes it to one of several digital output lines.
• A demultiplexer of 2n outputs has n select lines, which are used to
select which output line to send the input.
• We have 1x2,1x4,8x1…. Demultiplexers.

Fig:1 Block Fig :2 Truth

diagram table
109
 DEMULTIPLE
XER
Boolean functions for each output
as

Fig:3 Logic
diagram

110
 CODE
CONVERTERS
A code converter is a logic circuit whose inputs are bit patterns
representing numbers (or character) in one code and whose
outputs are the corresponding representation in a different code.
Design of a 4-bit binary to gray code converter

Fig :1 Truth
table

111
 CODE
CONVERTERS
K-map
simplification

112
CODE
CONVERTERS

Fig: 2 Logic
diagram

113
SEQUENTIAL LOGIC
CIRCUITS

UNIT 4

INTRODUCTION TO
SEQUENTIAL LOGIC
CIRCUITS

114
 SEQUENTIAL LOGIC CIRCUITS

SEQUENTIAL LOGIC CIRCUITS

Sequential logic circuit consists of a combinational circuit
with storage elements connected as a feedback to
combinationalcircuit
• output depends on the sequence of inputs (past and present)
• stores information (state) from past inputs

Figure 1: Sequential logic circuits

115
 SEQUENTIAL LOGIC CIRCUITS

• Output depends on
– Input
– Previous state of the circuit
• Flip-flop: basic memory
element
• State table: output for all
combinations of input and
previous states(Truth Table)

116
 SEQUENTIAL LOGIC CIRCUITS

1. Sequential circuit receives the binary informationfrom

external inputs and with the present state of the
storage elements together determine the binary value
of the outputs.
2. The output in a sequential circuit are a function of not
only the inputs, but also the present state of the
storage elements.
3. The next state of the storage elements is also afunction
of external inputs and the present state.
4. There are two main types of sequential circuits
1. synchronous sequential circuits
2. asynchronous sequential circuits
117
 SEQUENTIAL LOGIC CIRCUITS
Synchronous sequential circuits
It is a system whose behaviour can be
defined from the knowledge of its
signals at discrete instants of time

Asynchronous sequential circuits

It depends upon the input signals at any
instant of time and the order in which
the input changes

118
 Combinational vs. Sequential

COMBINATIONAL LOGIC CIRCUIT

Combinational logic circuit consists of input variables, logic

gates and output variables. The logic gate accepts signals from the
inputs
and generates signals to the outputs.
n input m output
variables
variables

For n input variables there are 2n possible combinations of binary input

variables

119
 Combinational vs. Sequential

SEQUENTIAL LOGIC CIRCUITS

Sequential logic circuit consists of a combinational circuit
with storage elements connected as a feedback to
combinationalcircuit
• output depends on the sequence of inputs (past and present)
• stores information (state) from past inputs

Figure 1: Sequential logic circuits

120
 Combinational vs. Sequential
Combinational Circuit
always gives the same output for a given set of inputs
ex: adder always generates sum and carry,
regardless of previous inputs

Sequential Circuit
stores information
output depends on stored information (state) plus
input so a given input might produce different
outputs, depending on the stored information
example: ticket counter
advances when you push the button
output depends on previous state
useful for building ―memory‖ elements and
―state machines‖ 121
Combinational vs. Sequential

122
 LATCHES
STORAGE ELEMENTS
Storage elements in a digital circuit can maintain a binary state
indefinitely, until directed by an input signal to switch states. The
major difference among various storage elements are the number of
input they posses and the manner in which the inputs affect the
binary state.There are two types of storage elements
1. Latches
2. Flipflops
Storage elements that operate with signal level are referred as latch
and those controlled by a clock transition are referred asflipflops.

123
 LATCHE
1. LATCHES:
S
A latch has a feedback path, so information can be retained by the device.
Therefore latches can be memory devices, and can store one bit of data
for as long as the device is powered. As the name suggests, latches are
used to "latch onto" information and hold in place. Latches are very
similar
to flip-flops, but are not synchronous devices, and do not operate on
clock edges as flip-flops do. Latch is a level sensitive device. Latch is a
monostable multivibrator

2. FLIPFLOPS:
A flip-flop is a circuit that has two stable states and can be used to store state
information. A flip-flop is a bistable multivibrator. The circuit can be made to
change state by signals applied to one or more control inputs and will have one
or two outputs. It is the basic storage element in sequential logic. Flip-flops and
latches are fundamental building blocks of digital electronics systems used in
computers, communications, and many other types of systems. Flipflop is a
edge sensitive device. 124
 LATCHE
S
SR LATCH

An SR latch (Set/Reset) is an asynchronous device: it works independently of control

signals and relies only on the state of the S and R inputs. In the image we can see that an
SR flip-flop can be created with two NOR gates that have a cross-feedback loop. SR
latches can also be made from NAND gates, but the inputs are swapped and negated. In
this case, it is sometimes called an SR latch.

R is used to ―reset‖ or ―clear‖ the element – set it to zero. S is used to ―set‖ the element –
set it to one.
If both R and S are one, out could be either zero or one. ―quiescent‖ state -- holds its
previous value. note: if a is 1, b is 0, and vice versa

125
 LATCHE
S
GATED D-LATCH
The D latch (D for "data") or transparent latch is a simple extension of the gated SR
latch that removes the possibility of invalid input states. Two inputs: D (data) and WE
(write enable)
when WE = 1, latch is set to value of
D S = NOT(D), R = D
when WE = 0, latch holds previous
value S = R = 1

126
 FLIPFLOPS:RS FLIPFLOP
Flip flops
A flip flop is an electronic circuit with two stable states that can be used to store
binary data. The stored data can be changed by applying varying inputs. Flip-flops
and latches are fundamental building blocks of digital electronics systems used in
computers, communications, and many other types of systems. Flip-flops and
latches are used as data storage elements. There are 4 types of flipflops

1. RS flip flop
2. Jk flip flop
3. D flip flop
4. T flip flop
Applications of Flip-Flops
These are the various types of flip-flops being used in digital electronic circuits and
the applications like Counters, Frequency Dividers, Shift Registers, Storage
Registers
127
 FLIPFLOPS:RS FLIPFLOP
EDGE-TRIGGERED FLIP FLOPS
Characteristics
- State transition occurs at the rising edge
or
falling edge of the clock pulse

Latches

respond to the input only during these periods

Edge-triggered Flip Flops (positive)

respond to the input only at this

time

128
FLIPFLOPS:RS FLIPFLOP
FLIP
FLOPS

129
 FLIPFLOPS:RS FLIPFLOP
SR Flip-Flop
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic
sequential logic circuit possible. This simple flip-flop is basically a one-bit memory bistable
device that has two inputs, one which will ―SET‖ the device (meaning the output = ―1‖), and
is labelled S and one which will ―RESET‖ the device (meaning the output = ―0‖), labelled
R.The reset input resets the flip-flop back to its original state with an output Q that will be
either at a logic level ―1‖ or logic ―0‖ depending upon this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back
to its opposing inputs and is commonly used in memory circuits to store a single data bit.
Then the SR flip-flop actually has three inputs, Set, Reset and its current output Q relating
to it’s current state or history.

Truth Table for this Set-Reset Function

130
 FLIPFLOPS:JK FLIPFLOP
JK Flip flop
The JK Flip-flop is similar to the SR Flip-flop but there is no change in state
when the J and K inputs are both LOW. The basic S-R NAND flip-flop circuit
has many advantages and uses in sequential logic circuits but it suffers from two
basic switching problems.
1. the Set = 0 and Reset = 0 condition (S = R = 0) must always be avoided
2.if Set or Reset change state while the enable (EN) input is high the correct
latching action may not occur
Then to overcome these two fundamental design problems with the SR
flip-flop
design, the JK flip Flop was developed by the scientist name Jack Kirby.
The JK flip flop is basically a gated SR flip-flop with the addition of a clock
input circuitry that prevents the illegal or invalid output condition that can occur
when both inputs S and R are equal to logic level ―1‖. Due to this additional
clocked input, a JK flip-flop has four possible input combinations, ―logic 1‖, ―logic
0‖, ―no change‖ and ―toggle‖. The symbol for a JK flip flop is similar to that of an SR
Bistable Latch as seen in the previous tutorial except for the addition of a clock
input.

131
 FLIPFLOPS:JK FLIPFLOP
 Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then thisequates
to: J = S and K = R.
 The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-
input NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = ―1‖ and R = ―1‖ state to be
used to produce a ―toggle action‖ as the two inputs are now interlocked.
 If the circuit is now ―SET‖ the J input is inhibited by the ―0‖ status of Q through the
lower NAND gate. If the circuit is ―RESET‖ the K input is inhibited by the ―0‖ status of Q through
the upper NAND gate. As Q and Q are always different we can use them to control the input.
When both inputs J and K are equal to logic ―1‖, the JK flip flop toggles as shown in the following
truth table.

132
 FLIPFLOPS:JK FLIPFLOP
The Truth Table for the JK Function

Then the JK flip-flop is basically an SR flip

flop with feedback which enables only one of
its two input terminals, either SET or RESET
to be active at any one time thereby
eliminating the invalid condition seen
previously in the SR flip flop circuit. Also
when both the J and
the K inputs are at logic level ―1‖ at the same
time, and the clock input is pulsed ―HIGH‖, the
circuit will ―toggle‖ from its SET state to a
RESET state, or visa-versa. This results in the
JK flip flop acting more like a T-type toggle flip-
flop when both terminals are―HIGH‖.

133
 FLIPFLOPS:T
FLIPFLOP
T FLIP FLOP
We can construct a T flip flop by any of the following methods. Connecting the output feedback
to the input, in SR flip flop. Connecting the XOR of T input and Q PREVIOUS output to the
Data input, in D flip flop. Hard – wiring the J and K inputs together and connecting it to T input,
in JK flip – flop.

134
 FLIPFLOPS:T
FLIPFLOP
Working
T flip – flop is an edge triggered device i.e. the low to high or high to low transitions
on a clock signal of narrow triggers that is provided as input will cause the change in
output state of flip – flop. T flip – flop is an edge triggered device.

Truth Table of T flip – flop

135
 FLIPFLOPS:T
FLIPFLOP
If the output Q = 0, then the upper NAND is in enable state and lower NAND gate is in
disable condition. This allows the trigger to pass the S inputs to make the flip – flop in
SET state i.e. Q = 1.
If the output Q = 1, then the upper NAND is in disable state and lower NAND gate is in
enable condition. This allows the trigger to pass the R inputs to make the flip – flop in RESET
state i.e. Q =0.
In simple terms, the operation of the T flip – flop is
When the T input is low, then the next sate of the T flip flop is same as the present state.
T = 0 and present state = 0 then the next state = 0
T = 1 and present state = 1 then the next state = 1
When the T input is high and during the positive transition of the clock signal, the next
stateof the T flip – flop is the inverse of present state.
T = 1 and present state = 0 then the next state =
1 T = 1 and present state = 1 then the next state
=0
Applications
Frequency Division Circuits.
2 – Bit Parallel Load Registers.

136
 FLIPFLOPS:D FLIPFLOP
D FLIP FLOP
The D-type flip-flop is a modified Set-Reset flip-flop with the addition of an inverter to prevent
the S and R inputs from being at the same logic level
One of the main disadvantages of the basic SR NAND Gate Bistable circuit is that the
indeterminate input condition of SET = ―0‖ and RESET = ―0‖ isforbidden.
This state will force both outputs to be at logic ―1‖,over-riding the feedback latching action and
whichever input goes to logic level ―1‖ first will lose control, while the other input still at logic
―0‖ controls the resulting state of the latch.
But in order to prevent this from happening an inverter can be connected between the ―SET‖ and
the ―RESET‖ inputs to produce another type of flip flop circuit known as a Data Latch, Delay
flip flop, D-type Bistable, D-type Flip Flop or just simply a D Flip Flop as it is more generally
called.
The D Flip Flop is by far the most important of the clocked flip-flops as it ensures that ensures
that inputs S and R are never equal to one at the same time. The D-type flip flop are
constructed from a gated SR flip-flop with an inverter added between the S and the R inputs to
allow for a single D (data) input.
Then this single data input, labelled ―D‖ and is used in place of the ―Set‖ signal, and the inverter
is used to generate the complementary ―Reset‖ input thereby making a level-sensitive D-type
flip-flop from a level-sensitive SR-latch as now S = D and R = not D as shown.
137
 FLIPFLOPS:D FLIPFLOP

D-type Flip-Flop Circuit

We remember that a simple SR flip-flop requires two inputs, one to ―SET‖ the output and one
to ―RESET‖ the output. By connecting an inverter (NOT gate) to the SR flip-flop we can
―SET‖ and ―RESET‖ the flip-flop using just one input as now the two input signals are
complements of each other. This complement avoids the ambiguity inherent in the SR latch
when both inputs are LOW, since that state is no longer possible. Thus this single input is
called the ―DATA‖input. If this data input is held HIGH the flip flop would be ―SET‖ and
when it is LOW the flip flop would change and become ―RESET‖. However, this would be
rather pointless since the output of the flip flop would always change on every pulse applied
to this data input.
138
 FLIPFLOPS:D FLIPFLOP
To avoid this an additional input called the ―CLOCK‖ or ―ENABLE‖ input is used to isolate the
data input from the flip flop’s latching circuitry after the desired data has been stored. The effect
is that D input condition is only copied to the output Q when the clock input is active. This then
forms the basis of another sequential device called a D Flip Flop.
The ―D flip flop‖ will store and output whatever logic level is applied to its data terminal so long
as the clock input is HIGH. Once the clock input goes LOW the ―set‖ and ―reset‖ inputs of the flip-
flop are both held at logic level ―1‖ so it will not change state and store whatever data was
present on its output before the clock transition occurred. In other words the output is ―latched‖ at
either logic ―0‖ or logic ―1‖.
Truth Table for the D-type Flip Flop

Note that: ↓ and ↑ indicates direction of

clock pulse as it is assumed D-type
flip flops are edge triggered

139
 FLIPFLOPS:MASTER SLAVE FLIPFLOP
MASTER SLAVE FLIPFLOP
Master-slave flip flop is designed using two separate flip flops. Out of these, one acts
as the master and the other as a slave. The figure of a master-slave J-K flip flop is
shown below.

From the above figure you can see that both the J-K flip flops are presented in a
series connection. The output of the master J-K flip flop is fed to the input of the
slave J-K flip flop. The output of the slave J-K flip flop is given as a feedback to the
input of the master J-K flip flop. The clock pulse [Clk] is given to the master J-K flip
flop and it is sent through a NOT Gate and thus inverted before passing it to the
slave J-K flip flop.

140
FLIPFLOPS:MASTER SLAVE FLIPFLOP

141
 FLIPFLOPS:MASTER SLAVE FLIPFLOP
The truth table corresponding to the working of the flip-flop shown in Figure is given by
Table I. Here it is seen that the outputs at the master-part of the flip-flop (data
enclosed in red boxes) appear during the positive-edge of the clock (red arrow).
However at this instant the slave-outputs remain latched or unchanged. The same
data is transferred to the output pins of the master-slave flip-flop (data enclosed in
blue boxes) by the slave during the negative edge of the clock pulse (blue arrow). The
same principle is further emphasized in the timing diagram of master-slave flip-flop
shown by Figure 3. Here the green arrows are used to indicate that the slave-output is
nothing but the master- output delayed by half-a-clock cycle. Moreover it is to be
noted that the working of any other type of master-slave flip-flop is analogous to that
of the master slave JK flip-flop explained here.

142
 FLIPFLOPS:MASTER SLAVE FLIPFLOP
.

143
 FLIPFLOPS:EXCITATION FUNCTIONS
In electronics design, an excitation table shows the minimum inputs that are necessary to generate a
particular next state (in other words, to "excite" it to the next state) when the current state is known.
They are similar to truth tables and state tables, but rearrange the data so that the current state and next
state are next to each other on the left-hand side of the table, and the inputs needed to make that state
change happen.
All flip-flops can be divided into four basic types: SR, JK, D and T. They differ in the number of
inputs and in the response invoked by different value of inputsignals.
The characteristic table in the third column of Table 1 defines the state of each flip-flop as a function of
its inputs and previous state. Q refers to the present state and Q(next) refers to the next state after the
occurrence of the clock pulse. The characteristic table for the RS flip-flop shows that the next state is
equal to the present state when both inputs S and R are equal to 0. When R=1, the next clock pulse
clears the flip-flop. When S=1, the flip-flop output Q is set to 1. The equation mark (?) for the next state
when S and R are both equal to 1 designates an indeterminate next state.
The characteristic table for the JK flip-flop is the same as that of the RS when J and K are replaced by S
and R respectively, except for the indeterminate case. When both J and K are equal to 1, the next state is
equal to the complement of the present state, that is, Q(next) = Q'.
The next state of the D flip-flop is completely dependent on the input D and independent of the present
state.
The next state for the T flip-flop is the same as the present state Q if T=0 and complemented if T=1.

144
FLIPFLOPS:EXCITATION FUNCTIONS

SR Flip
flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

145
FLIPFLOPS:EXCITATION FUNCTIONS

JK Flip flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

146
FLIPFLOPS:EXCITATION FUNCTIONS

D Flip
flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

147
FLIPFLOPS:EXCITATION FUNCTIONS

T Flip
flop

FLIP-FLOPSYMBOL CHARACTERISTIC TABLE

CHARACTERISTIC EQUATION EXCITATION TABLE

148
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF SR FLIP FLOP TO JK FLIPFLOP

J and K will be given as external inputs to S and R. As shown in the logic diagram below, S
and R will be the outputs of the combinational circuit.
The truth tables for the flip flop conversion are given below. The present state is represented
by Qp and Qp+1 is the next state to be obtained when the J and K inputs are applied.
For two inputs J and K, there will be eight possible combinations. For each combination of J,
K and Qp, the corresponding Qp+1 states are found. Qp+1 simply suggests the future values
to be obtained by the JK flip flop after the value of Qp. The table is then completed by
writing the values of S and R required to get each Qp+1 from the corresponding Qp. That is,
the values of S and R that are required to change the state of the flip flop from Qp to Qp+1
are written.

149
CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

150
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP
CONVERTION OF JK FLIP FLOP TO SR FLIPFLOP
This will be the reverse process of the above explained conversion. S and R will be the
external inputs to J and K. As shown in the logic diagram below, J and K will be the
outputs of the combinational circuit. Thus, the values of J and K have to be obtained in
terms of S, R and Qp. The logic diagram is shown below.
A conversion table is to be written using S, R, Qp, Qp+1, J and K. For two inputs, S and
R, eight combinations are made. For each combination, the corresponding Qp+1 outputs
are found ut. The outputs for the combinations of S=1 and R=1 are not permitted for an
SR flip flop. Thus the outputs are considered invalid and the J and K values are taken
as
―don’t cares‖.

151
CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

152
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF SR FLIP FLOP TO D FLIPFLOP

As shown in the figure, S and R are the actual inputs of the flip flop and D is the external
input of the flip flop. The four combinations, the logic diagram, conversion table, and the
K-map for S and R in terms of D and Qp are shown below.

153
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF D FLIP FLOP TO SR FLIPFLOP

D is the actual input of the flip flop and S and R are the external inputs. Eight possible
combinations are achieved from the external inputs S, R and Qp. But, since the
combination of S=1 and R=1 are invalid, the values of Qp+1 and D are considered as
―don’t cares‖. The logic diagram showing the conversion from D to SR, and the K-map for
D in terms of S, R and Qp are shown below.

154
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF JK FLIP FLOP TO T FLIP FLOP

J and K are the actual inputs of the flip flop and T is taken as the external input for
conversion. Four combinations are produced with T and Qp. J and K are expressed in
terms of T and Qp. The conversion table, K-maps, and the logic diagram are given below.

155
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF JK FLIP FLOP TO D FLIPFLOP

D is the external input and J and K are the actual inputs of the flip flop. D and Qp
make four combinations. J and K are expressed in terms of D and Qp. The four
combination conversion table, the K-maps for J and K in terms of D and Qp, and the
logic diagram showing the conversion from JK to D are given below.

156
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF D FLIP FLOP TO JK FLIPFLOP

In this conversion, D is the actual input to the flip flop and J and K are the external inputs.
J, K and Qp make eight possible combinations, as shown in the conversion table below. D
is expressed in terms of J, K and Qp.
The conversion table, the K-map for D in terms of J, K and Qp and the logic diagram
showing the conversion from D to JK are given in the figure below.

157
 CONVERTION OF ONE FLIP FLOP TO ANOTHER FLIP FLOP

CONVERTION OF T FLIP FLOP TO JK FLIP FLOP

We begin with the T-to-JK conversion table (see Figure 5), which combines the information
in the JK flip-flop's truth table and the T flip-flop's excitation table.

Next, we need to obtain the simplified Boolean expression for the T input in terms of J, K, and
Qn. The expression for the T input as JQ̅ n + KQn. This means that to convert the T flip-flop into a
JK flip-flop, the T input is driven by the output of a two-input OR gate which has as inputs
J ANDed with the negation of the present-state Qn, i.e., Q̅n
K ANDed with the present-state, Qn
158
 STATE MACHINES
State Machine
Another type of sequential circuit
Combines combinational logic with storage
―Remembers‖ state, and changes output (and state) based on inputs and current state

State
The state of a system is a snapshot of all the relevant elements of the system at the moment the
snapshot is taken.

Examples:
The state of a basketball game can be represented by the scoreboard.
Number of points, time remaining, possession, etc.
The state of a tic-tac-toe game can be represented by the placement of X’s and O’s on the
board.
159
State Tables and State Diagrams
STATE MACHINES
STATE TABLES AND STATE DIAGRAMS
In this model the effect of all previous inputs on the outputs is represented by a state of the
circuit. Thus, the output of the circuit at any time depends upon its current state and the
input. These also determine the next state of the circuit. The relationship that exists among
the inputs, outputs, present states and next states can be specified by either the state table or
the state diagram.
State Table
The state table representation of a sequential circuit consists of three sections labeled present
state, next state and output. The present state designates the state of flip-flops before the
occurrence of a clock pulse. The next state shows the states of flip-flops after the clock
pulse, and the output section lists the value of the output variables during the present state.

160
 STATE MACHINES
State Diagram
In addition to graphical symbols, tables or equations, flip-flops can also be represented
graphically by a state diagram. In this diagram, a state is represented by a circle, and the
transition between states is indicated by directed lines (or arcs) connecting the circles.
The binary number inside each circle identifies the state the
circle represents. The directed lines are labelled with two binary
numbers separated by a slash (/). The input value that causes the
state transition is labelled first. The number after the slash
symbol / gives the value of the output. For example, the directed
line from state 00 to 01 is labelled 1/0, meaning that, if the
sequential circuit is in a present state and the input is 1, then the
next state is 01 and the output is 0. If it is in a present state 00
and the input is 0, it will remain in that state. A directed line
connecting a circle with itself indicates that no change of state
occurs. The state diagram provides exactly the same information
as the state table and is obtained directly from the state table.
S
t
a
t 161
e
 STATE MACHINES
Example:
The behavior of the circuit is determined by
Consider a sequential
the
circuit
following Boolean expressions:
Z = x*Q1
D1 = x' + Q1
D2 = x*Q2' +
x'*Q1'

These equations can be used to form the state table. Suppose the present state (i.e. Q1Q2) = 00
and input x = 0. Under these conditions, we get Z = 0, D1 = 1, and D2 = 1. Thus the next state
of the circuit D1D2 = 11, and this will be the present state after the clock pulse has been
applied. The output of the circuit corresponding to the present state Q1Q2 = 00 and x = 1 is Z
=
0. This data is entered into the state table as shown in Table 2.

162
 STATE MACHINES
State table for the sequential
circuit

The state diagram for the sequential circuit

163
 STATE MACHINES
state diagrams of the four types of flip-
flops

164
 STATE REDUCTION
State Reduction
Any design process must consider the problem of minimising the cost of the final circuit. The
two most obvious cost reductions are reductions in the number of flip-flops and the number of
gates.
The number of states in a sequential circuit is closely related to the complexity of the resulting
circuit. It is therefore desirable to know when two or more states are equivalent in all aspects.
The process of eliminating the equivalent or redundant states from a state table/diagram is
known as state reduction.
Example: Let us consider the state table of a sequentialcircuit

State
table
165
 STATE REDUCTION
It can be seen from the table that the present state A and F both have the same next states, B
(when x=0) and C (when x=1). They also produce the same output 1 (when x=0) and 0 (when
x=1). Therefore states A and F are equivalent. Thus one of the states, A or F can be removed
from the state table. For example, if we remove row F from the table and replace all F's by
A's in the columns, the state table is modified

State F removed
It is apparent that states B and E are equivalent. Removing E and replacing E's by B's
results
in the reduce table
166
 STATE REDUCTION

Reduced state table

The removal of equivalent states has reduced the number of states in the circuit from six to
four. Two states are considered to be equivalent if and only if for every input sequence the
circuit produces the same output sequence irrespective of which one of the two states is the
starting state.

167
 STATE ASSIGNMENT
STATEASSIGNMENT
Each circuit state given in a state table has to be assigned a unique value, which
represents combinations of flip – flop output states.
 A circuit having 2 internal states requires one flip – flop in its implementation
 A circuit having 3 or 4 internal states requires two flip – flops in its implementation
 A circuit having 5→ 8 internal states requires three flip – flops in its implementation
etc.
It should be noted that although assignments are arbitrary, one assignment might be more
economical than another.
Consider the state table shown below for a circuit having two input pulses x1, x2 and a level
output Z.
Since the circuit has four internal states then two flip-flops are required. Let the two flip-flop
outputs be represented by variables y1 and y2, which can have combinations of values y1y2 =
00, 01, 11, 10. The state table can then be translated into a state table with secondary
assignments as shown. Note that this is just one of many possible assignments (in fact there are
24)

168
 STATE ASSIGNMENT

Example of state assignment

With y1y2 =0 (i.e. in state 1), if x1 is applied then y1y2must change to 01 (i.e. state 2). That is,
the flip/flop generating y1 must not disturbed, but the y2generating flip-flop requires an input
such that the circuit settles in state 2, (for example a SET input if using SR flip-flops).

169
MEALY AND MOORE STATE MACHINES
Mealy state machine
In the theory of computation, a Mealy machine is a finite state transducer that generates an
output based on its current state and input. This means that the state diagram will include
both an input and output signal for each transition edge. In contrast, the output of a Moore
finite state machine depends only on the machine's current state; transitions are not directly
dependent upon input. The use of a Mealy FSM leads often to a reduction of the number of
states. However, for each Mealy machine there is an equivalent Moore machine.

170
 MEALY AND MOORE STATE MACHINES
Moore state machine
In the theory of computation, a Moore machine is a finite state transducer where the outputs are
determined by the current state alone (and do not depend directly on the input). The state diagram
for a Moore machine will include an output signal for each state. Compare with a Mealy machine,
which maps transitions in the machine to outputs. The advantage of the Moore model is a
simplification of the behavior.

171
MEALY AND MOORE STATE MACHINES
Examples for Mealy and Moore machines
Derive a minimal state table for a single-input and single-output Moore-type FSM
that produces an output of 1 if in the input sequence it detects either 110 or 101
patterns. Overlapping sequences should be detected. (Show the detailed stepsof
your solution.)

172
MEALY AND MOORE STATE MACHINES
Sate Table (Moore
FSM)

173
 MEALY AND MOORE STATE MACHINES
State Assignment (Mealy
FSM):
state A: Got no
1 state B: Got‖1‖
state C: Got‖11‖
state D: Got‖10”
Sate Table
(Mealy FSM)

174
 MEALY AND MOORE MACHINES
Sequential Logic Implementation
 Models for representing sequential
circuits
Abstraction of sequential elements
Finite state machines and their state diagrams
Inputs/outputs
Mealy, Moore, and synchronous Mealy
machines
 Finite state machine design procedure
Verilog specification
Deriving state diagram
Deriving state transition
table
Determining next state and
output functions
Implementing combinational
logic
175
 MEALY AND MOORE MACHINES
Mealy vs. Moore Machines
Moore: outputs depend on current state only
Mealy: outputs depend on current state and
inputs
 Ant brain is a Moore Machine (Output does not
react immediately to input change)
 We could have specified a Mealy FSM (Outputs
have immediate reaction to inputs . As
inputs change, so does next state, doesn’t
commit until clocking event)
Specifying Outputs for a Moore Machine
Output is only function of state. Specify in state bubble in state diagram. Example:
sequence detector for 01 or 10

176
 MEALY AND MOORE MACHINES
Specifying Outputs for a Mealy Machine
Output is function of state and inputs .Specify output on transition arc between
states.
Example: sequence detector for 01 or 10

177
 MEALY AND MOORE MACHINES
Comparison of Mealy and Moore Machines
 Mealy Machines tend to have less states
Different outputs on arcs (n^2) rather than states (n)
 Moore Machines are safer to use
Outputs change at clock edge (always one cycle later)
In Mealy machines, input change can cause output change as soon as logic is done – a
big
problem when two machines are interconnected – asynchronous feedback
 Mealy Machines react faster to inputs
React in same cycle – don't need to wait for clock
In Moore machines, more logic may be necessary to decode state into outputs – more gate
delays after

178
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL
CIRCUITS
synchronous sequential circuits a clock signal consisting of pulses, controls the
state variables which are represented by flip-flops. they are said to operate in
pulse mode.
asynchronous circuits state changes are not triggered by clock pulses. they depend on
the values of the input and feedback variables.
two conditions for proper operation:
1.-inputs to the circuit must change one at a time and must remain constant until the
circuit reaches stable state.
2.-feedback variables should change also one at a time. when all internal signals stop
changing, then the circuit is said to have reached stable state when the inputs
satisfy condition 1 above, then the circuit is said to operate in fundamental mode.
Analysis of Clocked Sequential Circuits
The analysis of a sequential circuit consists of obtaining a table or a diagram for the
time sequence of inputs, outputs, and internal states. It is also possible to write
Boolean expressions that describe the behavior of the sequential circuit. These
expressions must include the necessary time sequence, either directly or indirectly.

179
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

State Equations
The behavior of a clocked sequential circuit can be described algebraically by means of
state equations. A state equation specifies the next state as a function of the present state and
inputs. Consider the sequential circuit shown in Fig. 5-15. It consists of two D flip-flops A
and B, an input x and an output y.

State equation
A(t+1) = A(t) x(t) + B(t) x(t)

B(t+1) = A`(t) x(t)

A state equation is an algebraic expression that specifies the condition for a flip-flop state
transition. The left side of the equation with (t+1) denotes the next state of the flip-flop one
clock edge later. The right side of the equation is Boolean expression that specifies the present
state and input conditions that make the next state equal to 1.
Y(t) = (A(t) + B(t)) x(t)`
180
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

State Table
The time sequence of inputs, outputs, and flip-flop states can be enumerated in a state
table
(sometimes called transition table). State Diagram

1/0 : means input =1

output=0
The information available in a state table can be represented graphically in the form
of a state
diagram. In this type of diagram, a state is represented by a circle, and the transitions
between
states are indicated by directed lines connecting the circles. 181
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

Flip-Flop Input Equations

The part of the combinational circuit that generates external outputs is descirbed
algebraically by a set of Boolean functions called output equations. The part of
the circuit that generates the inputs to flip-flops is described algebraically by a set
of Boolean functions called flip-flop input equations. The sequential circuit of
Fig. 5-15 consists of two D flip-flops A and B, an input x, and an output y. The
logic diagram of the circuit can be expressed algebraically with two flip-flop
input equations and an output equation:
DA = Ax + Bx,DB = A`x and y = (A + B)x`
Analysis with D Flip-Flop
The circuit we want to analyze is described by the input equation
The DA symbol implies a D flip-flop with output A. The x and y variables are the inputs to the
circuit. No output equations are given, so the output is implied to come from the output of the
flip-flop.

182
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

The binary numbers under A y are listed from 000 through 111 as shown
in Fig. 5-17(b). The next state values are obtained from the state equation

The state diagram consists of two circles-one for each state as shown in Fig.
5-17(c)

183
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

ASYNCHRONOUS SEQUENTIAL CIRCUIT

Analysis of asynchronous circuits
Procedure:
– Cut all feedback paths and insert a delay element at each point where cut was made
– Input to the delay element is the next state variable yi while the
output is the
present value yi .
– Derive the next-sate and output expressions from the circuit
– Derive the excitation table
– Derive the flow table
– Derive a state-diagram from the flow table
– Asynchronous circuits don’t use clock pulses
• State transitions by changes in inputs
– Storage Elements:
• Clock less storage elements or Delay elements
– In many cases, as combinational feedback
• Normally much harder to design
184
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

yi = Yi in steady state (but may be different during transition) Simultaneous

change in two (or more) inputs is prohibited. The time between two changes
than
must the time of stability.
be less Analysis

185
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

3.Draw a map by using rows: yi’s, columns: inputs, entries:

Yi’s

4.To have a stable state, Y must be = y (circled)

(Transition Table) Y1 Y2

At y1y2x = 000, if x: 0  1
then Y1Y2: 00  01
then y1y2 = 01 (2nd row):stable

186
 SYNCHRONOUS AND ASYNCHRONOUS SEQUENTIAL CIRCUITS

In general, if an input takes the circuit to an unstable state, yi’s change untila stable
state is found. State Table As
General state of circuit: synchronous
y1y2x:
There are 4 stable states:
000, 011, 110, 101
and 4 unstable states.
Flow Table
As Transition Table
(but with
symbolic states):
SYNTHESIS OF
ASYNCHROUNOU
S CIRCUITS
This topic is not covered in this course. it belongs to a more advanced logic design course.This it
is very important in todays digital systems design because clocks are so fast that they present
propagation delays making subsystems to operate out of synchronization.
Techniques for synthesis of asynchronous circuits include
The hoffman or classic synthesis approach 187
 SHIFT REGISTERS

Introduction :
Shift registers are a type of sequential logic circuit, mainly for storage of digital data. They
are a group of flip-flops connected in a chain so that the output from one flip-flop becomes
the input of the next flip-flop. Most of the registers possess no characteristic internal
sequence of states. All the flip-flops are driven by a common clock, and all are set or reset
simultaneously. Shift registers are divided into two types.
1. Uni directional shift registers
1.Serial in – serial out shift register
2.Serial in – parallel out shift
register 3.Parallel in – serial out
shift register
4. Parallel in – parallel out shift
register
2. Bidirectional shift registers
1. Left shift register
2. Right shift register

188
 SHIFT REGISTERS

1.Serial in – serial out shift register

A basic four-bit shift register can be constructed using four D flip-flops, as shown below. The
operation of the circuit is as follows. The register is first cleared, forcing all four outputs to
zero. The input data is then applied sequentially to the D input of the first flip-flop on the left
(FF0). During each clock pulse, one bit is transmitted from left to right. Assume a data word
to be 1001. The least significant bit of the data has to be shifted through the register from FF0
to FF3.

In order to get the data out of the register, they must be shifted out serially. This can be done
destructively or non-destructively. For destructive readout, the original data is lost and at the
end of the read cycle, all flip-flops are reset to zero.

189
 SHIFT REGISTERS

To avoid the loss of data, an arrangement for a non-destructive reading can be done by
adding two AND gates, an OR gate and an inverter to the system. The construction of
this circuit is shown below

The data is loaded to the register when the control line is HIGH (ie WRITE). The data can be
shifted out of the register when the control line is LOW (ie READ). This is shown in the
animation below.

190
 SHIFT REGISTERS

2.Serial in – parallel out shift register

The difference is the way in which the data bits are taken out of the register. Once the data
are stored, each bit appears on its respective output line, and all bits are available
simultaneously.

In the animation below, we can see how the four-bit binary number 1001 is shifted to the Q
outputs of the register.

191
 SHIFT REGISTERS

3.Parallel in – serial out shift register

A four-bit parallel in - serial out shift register is shown below. The circuit uses D flip-
flops
and NAND gates for entering data (ie writing) to the register.

D0, D1, D2 and D3 are the parallel inputs, where D0 is the most significant bit and D3 is
the least significant bit. To write data in, the mode control line is taken to LOW and the
data is clocked in. The data can be shifted when the mode control line is HIGH as
SHIFT is active high. The register performs right shift operation on the application of a
clock pulse, as shown in the animation below.

192
 SHIFT REGISTERS

4.Parallel in –parallel out shift register

For parallel in - parallel out shift registers, all data bits appear on the parallel outputs
immediately following the simultaneous entry of the data bits. The following circuit is a
four-bit parallel in - parallel out shift register constructed by D flip-flops.

The D's are the parallel inputs and the Q's are the parallel outputs. Once the register
is clocked, all the data at the D inputs appear at the corresponding Q outputs
simultaneously.

193
 SHIFT REGISTERS AND COUNTERS

Bidirectional Shift Registers

The registers discussed so far involved only right shift operations. Each right shift operation has
the effect of successively dividing the binary number by two. If the operation is reversed (left
shift), this has the effect of multiplying the number by two. With suitable gating arrangement a
serial shift register can perform both operations. A bidirectional, or reversible, shift register is one
in which the data can be shift either left or right. A four-bit bidirectional shift register using D
flip-flops is shown below

Here a set of NAND gates are configured as OR gates to select data inputs from the right
or left adjacent bitable, as selected by the LEFT/RIGHT control line.
The animation below performs right shift four times, then left shift four times. Notice the
order of the four output bits are not the same as the order of the original four input bits.
194
 SHIFT REGISTERS AND COUNTERS

COUNTERS
Two of the most common types of shift register counters are introduced here: the Ring counter
and the Johnson counter. They are basically shift registers with the serial outputs connected back
to the serial inputs in order to produce particular sequences. These registers are classified as
counters because they exhibit a specified sequence of states.
Ring Counters
A ring counter is basically a circulating shift register in which the output of the most significant
stage is fed back to the input of the least significant stage. The following is a 4-bit ring counter
constructed from D flip-flops. The output of each stage is shifted into the next stage on the
positive edge of a clock pulse. If the CLEAR signal is high, all the flip-flops except the first one
FF0 are reset to 0. FF0 is preset to 1 instead.

195
 SHIFT REGISTERS AND COUNTERS

Since the count sequence has 4 distinct states, the counter can be considered as a mod-4
counter. Only 4 of the maximum 16 states are used, making ring counters very inefficient in
terms of state usage. But the major advantage of a ring counter over a binary counter is that it
is self-decoding. No extra decoding circuit is needed to determine what state the counter is
in.

196
 SHIFT REGISTERS AND COUNTERS

Johnson Counters
Johnson counters are a variation of standard ring counters, with the inverted output of the last
stage fed back to the input of the first stage. They are also known as twisted ring counters. An n-
stage Johnson counter yields a count sequence of length 2n, so it may be considered to be a
mod- 2n counter. The circuit above shows a 4-bit Johnson counter. The state sequence for the
counter is given in the table as well as the animation on the left.

Again, the apparent disadvantage of this counter is that the maximum available states are not
fully utilized. Only eight of the sixteen states are being used.
Beware that for both the Ring and the Johnson counter must initially be forced into a valid state
in the count sequence because they operate on a subset of the available number of states.
Otherwise, the ideal sequence will not be followed.
197
RANDOM ACCESS
MEMORY

UNIT 5
RANDOM
ACCESS
MEMOR
Y
198
 RANDOM ACCESS
MEMORY
A memory unit is a collection of storage
cells together with associated circuits
needed to transfer information in and out
of the device.
Memory cells can be accessed for
information transfer to or from any desired
random location and hence the name
random access memory, abbreviated RAM.
 A memory unit stores binary information
in groups of bits calledwords.
1 byte = 8 bits
1 word = 2 bytes.
 The communication between a memory
and its environment is throug
achieved
data input and output h
selection
lines, lines, and control lines addres Fig 1: Block diagram of memory unit
specify the direction of that
s
transfer.

199
 RANDOM ACCESS
Content of MEMORY
a
memory
 Each in memory
word
assigne anis identification
d calle an
number, from d address,
to 2k-
starting
where 0 is the up number
1, of
k
address
 lines.
The of words in
memory
number witha one of
the
letters16 K=210, M=220, or G=230.
64K = 2 2M =
221
Fig 2: Content of a 1024 x 16
memory
4G = 232
200
 RANDOM ACCESS
Write andMEMORY
Read
operations
 Transferring a new word to be stored into memory:
1. Apply the binary address of the desired word to
the address lines.
2. Apply the data bits that must be stored memory to
in data input lines. the

3. Activate the write

input.

201
 RANDOM ACCESS
MEMORY
Write and Read
operations
 Transferring a stored word out of memory:
1. Apply the binary address of the desired word to the address
lines.
2. Activate the read input.
 Commercial memory sometimes provide the two control inputs for reading
and writing in a somewhat different configuration in table 1.

Table
1

202
 TYPES OF
ROM
READ ONLY MEMORY (ROM)
• Computers almost always contain a small amount of read-only
memory that holds instructions for starting up the
computer.Unlike RAM, ROM cannot be written to.
• Because data stored in ROM cannot be modified (at least not
very quickly or easily), it is mainly used to distribute firmware
(software that is very closely tied to specific hardware, and
unlikely to require frequent updates).
• It is non-volatile which means once you turn off the
computerthe
information is still there.

203
 TYPES OF
ROM
READ ONLY MEMORY (ROM)
• A type of memories that can only be read from any
selected address in sequence.
• Stored data cannot be changed at all or cannot be
changed without
specialized equipment.
• Writing a data is not permitted.
• Reading data from any address does not destruct the
content of
read address.
• Usually to store data that is used repeatedly in system
application.

204
 TYPES OF
ROM
Programmable ROM (PROM)
• Is a memory chip on which data can be written onlyonce.
• Once a program has been written onto a PROM, it remains
there forever.
• Nonvolatile memory - unlike RAM, PROM's retain their
contents
when the computer is turned off.
• The difference between a PROM and a ROM (read-only memory)
is that a PROM is manufactured as blank memory, whereas a
ROM is programmed during the manufacturing process.
• To write data onto a PROM chip, you need a special device
called a PROM programmer or PROM burner.
• PROM uses some type of fusing process to store bits. Fusible link
is programmed open or left intact to represent 0 or 1. The link
cannot be changed once it is programmed.
205
 TYPES OF
EPROM ROM
• Once it is erased, it can be reprogrammed.
• Two basic types
• Ultraviolet (UV) EPROM
UV EPROM can be recognized by transparent quartz lid on
the
package.
Entire UV EPROM data can be erased by exposing
the transparent quartz lid to the high intensity UV
light.
• Electrically EPROM (EEPROM)
Individual bytes in EEPROM can be erased and
programmed
206
by electrical pulses (voltage).
 TYPES OF
Mask ROMs ROM

• Usually referred to simply as ROM (the oldest type of solid state

ROM)

• The data are permanently stored in the memory during

the manufacturing process and it cannot be changed.
• Most IC ROMs utilize the presence or absence of a
transistor connection at a row/column junction to represent a 1
or 0.
• Mask ROM and PROM can be of either MOS or bipolartechnology.
• Despite the simplicity of mask ROM, economies of scale and field-
programmability often make reprogrammable technologies
more flexible and inexpensive.
207
 MEMORY
DECODING
MEMORY DECODING

• Decoder

– select the memory word specified by the input address

• 2-dimensional coincident decoding is a more
efficient decoding scheme for large memories

208
 MEMORY
DECODING
 The logi of a binary cell that stores one bit of
equivalent cshown
information
Read/Write = 0,isselect
below.
= 1, input data to S-R latch
Read/Write = 1, select = 1, output data from S-R
latch

Figure 1: Memory
cell

209
 MEMORY
DECODING
MEMORY
ARRAY

210
 MEMORY
4x4 DECODING
RAM
 There is a need for decoding circuits
to select the memory word specified
by the input address.
 During the read operation, the four
bits of the selected word go through
OR gates to the output terminals.
 During the write operation, the data
available in the input lines are
transferred into the four binary cells
of the selected word.
 A memory with 2k words of n bits per
word requires k address lines that go
into kx2k decoder.

Fig 2: Diagram of 4 x 4
RAM 211
 MEMORY
DECODING
Coincident decoding
 A decoder with k inputs
and
2k outputs requires 2
k

AND
gates with k inputs per gate.
 Two decoding in a
dimensional
two- selection scheme
can reduce the number of
inputs per gate.
 1K-word memory, instead
of using a single 10X1024
decoder, we use two
5X32 decoders. Figure 1: Two-dimensional
Decoding structure for a 1K word
memory

212
 MEMORY
DECODING
Address multiplexing
 DRAMs typically have four times the density of SRAM.

 The cost per bit of DRAM storage is three to four times

less
than SRAM. Another factor is lower power requirement.

213
 MEMORY
DECODING
Address multiplexing
 Address multiplexing will reduce the number of pins in the IC
package.

 In a two-dimensional array, the address is applied in two parts

at different times, with the row address first and the column
address second. Since the same set of pins is used for both
parts of the address, so can decrease the size of package
significantly.

214
 MEMORY
DECODING
Address Multiplexing of a 64K
DRAM
 After a time equivalent to
settling time of the
the
selection, row
RAS goes back to the
1 level.

Registers are used to store
the
addresses of the row
and
column.

CAS must go back to the 1 level
before initialing another memory
operation.
Fig 2: Address Multiplexing for a 64K
DRAM
215
 ADDRESS AND DATA
BUS
ADDRESS BUS AND DATA BUS

Memory structures are crucial in digital design. – ROM, PROM,

EPROM, RAM, SRAM, (S)DRAM, RDRAM,..
All memory structures have an address bus and a data bus –

Possibly other control signals to control outputetc.

E.g. 4 Bit Address bus with 5 Bit Data Bus

216
 ADDRESS AND DATA
BUS
ADDRESS BUS AND DATA
BUS

Internal organization
– ‘Lookup Table of values’
–For each address there is
a corresponding data
output

217
 ADDRESS AND DATA
BUS
ADDRESS
BUS
• Address signals are required to specify the location in the memory
from which information is accessed(read or written).
• A set of parallel address lines known as the address bus carry the
address
information.
• The number of bits (lines) comprising the address bus depends upon the
• size of the memory.
For example, a memory having four locations to store data has four
• unique
(00, 01, 10, 11) specified by a 2-bit addressbus.
The size of the address bus depends upon the total addressable locations
specified by the formula 2^n, where n is the number of bits. Thus 2^4 =
16 (n=4) specifies 4 bits to uniquely identify 16 different locations.
218
 ADDRESS AND DATA
BUS
DATA BUS
• Data lines are required to retrieve the information from the memor
y array during a read operation and to provide the data that is to
be stored in the memory during a write operation.
• A the memory read or writes one data unit
s time s at
a
to the
therefore
number of data bits
the stored
dataat each
lines addressable
should be location in
th e memory. equal
• A memory organized as a byte memory reads or writes byte data
values, therefore the number of data lines or the size of the data
bus should be 8-bits or 1 byte.
• A memory organized to store nibble data values requires a 4-bit
wide data bus. Generally, the wider the data bus more data can be
accessed at each read or write operation
219
 SEQUENTIAL
MEMORY
SEQUENTIAL MEMORY

• Output depends on stored information (current state) and may

be
on currentinputs
• Example:
• state = Score board of basket state = Score board of
basketball game (number of points time game (number of
points, time remaining, possession)
• input = which team scored the point
• output = point increase for the team that just scored.
• Sequential Circuits are built out of combinational logic and
one or
more memory/storage elements
• E.g. Registers, Memories, Counters, Control Unit .
220
 SEQUENTIAL
MEMORY
1-Bit memory element Characteristics

• Need a unit that can

• Retain/Remember a single bit with possible values ( ) state i.e. 0
or
1.
• This will allow us to read a previous value stored„
• Able to change the value (state). For a bit we can:
• Set the bit to 1
• Reset, or clear, the bit to 0
• To remember/retain their state values, rely on concept of
feedback
„
• Feedback digital circuits occurs when an output is looped back
to
the input „ 221
 SEQUENTIAL
Flip Flop MEMORY

Flip flop is a sequential circuit which generally samples its

inputs and changes its outputs only at particular instants of
time and not continuously. Flip flop is said to be edge
sensitive or edge triggered rather than being level triggered
like latches.
• S-R Flip Flop
It is basically S-R latch using NAND gates with an
additional enable input. It is also called as level triggered
SR- FF. For this, circuit in output will take place if and only
if the enable input (E) is made active. In short this circuit
will operate as an S-R latch if E = 1 but there is no change
in the output if E = 0.
222
 SEQUENTIAL
Flip Flop MEMORY

• Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback
from the output of second to input of first. Master is a
positive level triggered. But due to the presence of the
inverter in the clock line, the slave will respond to the
negative level. Hence when the clock = 1 (positive level) the
master is active and the slave is inactive. Whereas when
clock
= 0 (low level) the slave is active and master is inactive.

223
 SEQUENTIAL
Flip Flop MEMORY

• Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch
with a NAND inverter connected between S and R inputs. It
has only one input. The input data is appearing at the
output after some time. Due to this data delay between i/p
and o/p, it is called delay flip flop. S and R will be the
complements of each other due to NAND inverter. Hence S
= R = 0 or S = R = 1, these input condition will never appear.
This problem is avoid by SR
= 00 and SR = 1 conditions.

224
 SEQUENTIAL
Flip Flop MEMORY

• Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K
terminals permanently connected together. It has only
input denoted by T .

225
 CACHE
MEMORY
CACHE

• A small amount of fast memory that sits between normal

main
memory and CPU

• May be located on CPU chip or module

• Intended to allow access speed approaching register speed

• When processor attempts to read a word from memory,
cache is checked first

226
 CACHE
MEMORY
Cache Memory Principles

• If data sought is not present in cache, a block of memory of

fixed size is read into the cache
• Locality of reference makes it likely that other words in
the same block will be accessed soon

227
 CACHE
MEMORY
CACHE VIEW OF MEMORY

• N address lines => 2n words of memory

• Cache stores fixed length blocks of K words

• Cache views memory as an array of M blocks where M = 2^n/K

• A block of memory in cache is referred to as a line. K is the line

size

• Cache size of C blocks where C < M (considerably)

• Each line includes a tag that identifies the block being stored

• Tag is usually upper portion of memory address

228
 CACHE
Cache operation –MEMORY
overview

• CPU requests contents of memory location

• Check cache for this data
• If present, get from cache (fast)
• If not present, read required block from main
memoryto cache
• Then deliver from cache to CPU
• Cache includes tags to identify which block of main
memory is in each cache slot

229
 PROGRAMMABLE LOGIC
ARRAY
Programmable Logic Array
• A programmable logic array (PLA) is a type of logic device
that can be programmed to implement various kinds of
combinational logic circuits.
• The device has a number of AND and OR gates which are
linked together to give output or further combined with more
gates or logic circuits.

230
 PROGRAMMABLE LOGIC
ARRAY
Programmable LogicArray

Fig 1: Block diagram of

PLA

231
 PROGRAMMABLE LOGIC
PLA
ARRAY
F1 =AB’+AC+A’BC’
F2 = (AC+BC)’

Fig 2: PLA with 3-inputs 4 product terms

and 2
outputs

232
 PROGRAMMABLE LOGIC
ARRA Y
Programmable Logic Array
• Advantages
• PLA architecture is more efficient than a PROM.
• Disadvantage
• PLA architecture has two sets of programmable fuses due
to which PLA devices are difficult to manufacture, program
and test.
• Applications:
• PLA is used to provide control over data path.
• PLA is used as a counter.
• PLA is used as decoders.
• PLA is used as a BUS interface in programmed I/O

233
 PROGRAMMABLE LOGIC
ARRAY
Programming
Table
1. First: lists the product terms numerically
2. Second: specifies the required paths inputs and
between AND gates
3. Third: specifies the paths between the AND and OR
gates
4. For each output variable, we may have a T(ture)
or
C(complement) for programming the XOR gate

234
 PROGRAMMABLE LOGIC
ARRAY
Simplification of PLA
 Careful investigation must be undertaken in order to reduce
the number of distinct product terms, PLA has a finite
number of AND gates.
 Both the true and complement of each function should be
simplified to see which one can be expressed with fewer
product terms and which one provides product terms that
are common to other functions.

235
 PROGRAMMABLE LOGIC
ExampleARRAY
Implement the following two Boolean functions with a
PLA:
F1(A, B,C) = ? (0, 1, 2, 4)
F2(A, B, C) = ? (0, 5, 6,
7)

The two functions are

simplified in the maps
of given figure

236
 PROGRAMMABLE LOGIC
ARRA
PLA table Y
by simplifying the function
 Both the true and
complement of the functions
are simplified in sum of
products.
 We can find the same terms
from the group terms of the
functions of F1, F1’,F2 and F2’
which will make the minimum
terms.
F1 = (AB +AC + BC)’
F2 = AB + AC + A’B’C’
Fig 1: Solution to example

237
 PROGRAMMABLE LOGIC
ARRA Y
PLAimplementation

238
 MEMORY
HIAERARCHY
Memory Hierarchy
• For any memory:
— How fast?
— How much?
— How expensive?
• Faster memory => greater cost per bit
• Greater capacity => smaller cost / bit
• Greater capacity => sloweraccess
• Going down the hierarchy:
— Decreasing cost / bit
— Increasing capacity
— Increasing access time
— Decreasing frequency of access by
processor 239
 MEMORY
HIAERARCHY
Memory Hierarchy - Diagram

240
 MEMORY
HIAERARCHY
MEMORY HIAERARCHY
• Registers
— In CPU
• Internal or Main memory
— May include one or more levels of
cache
— “RAM”
• External memory
— Backing store

241
 MEMORY
HIAERARCHY
HIAERARCHY
LIST
• Registers
• L1 Cache
• L2 Cache
• Main memory
• Disk cache
• Magnetic Disk
• Optical
• Tape

242
 MEMORY
HIAERARCHY
Locality of Reference
• Two or more levels of memory can be used to produce
average
access time approaching the highest level
• The reason that this works well is called ―locality of reference‖
• In practice memory references (both instructions and data) tend to
cluster
— Instructions: iterative loops and repetitive subroutine calls
— Data: tables, arrays, etc. Memory references cluster in short run

243
 MEMORY
HIAERARCHY
Characteristics of Memory
Systems

244
 MEMORY
HIAERARCHY
Capacity
• Word size
—The natural unit of organisation
—Typically number of bits used to represent an integer in
the processor
• Number of words
—Most memory sizes are now expressed in bytes
—Most modern processors have byte-addressable
memory but some have word addressable memory
— Memory capacity for A address lines is 2A
addressable
units
245
 MEMORY
HIAERARCHY
Access Methods
• Sequential
—Start at the beginning and read through in order
—Access time depends on location of data and
previous location
— e.g. tape
• Direct
— Individual blocks have unique address
— Access is by jumping to vicinity plus sequential search
— Access time depends on location and previous location
— e.g. disk

246
 MEMORY
HIAERARCHY
Access Methods
• Random
— Individual addresses identify locations exactly
— Access time is independent of location or previous
access
— e.g. RAM
• Associative
—Data is located by a comparison with contents of a
portion of the store
—
— Access time is independent
All memory is of location or previous time
simultaneously;access
access
checked is
constant
— e.g. cache
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 MEMORY
HIAERARCHY
Performance
• Cycle Time
—Primarily applied to RAM; access time + additional
time before a second access can start
—Function of memory components and system bus, not
the processor
• Transfer Rate – the rate at which data can be transferred
into
or out of a memory unit
— For RAM TR = 1 / (cycle time)

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