Functional units of computer

1
 Harvard vs Von Neumann

2
3
 General internal architecture
of a Processor

4
 Address bus data bus and
cotrol bus

5
 An address bus: this determines the location
in memory or An I/O device that the
processor will read data from or write data to.
A data bus: this contains the contents that
have been read from the memory location or
I/O or are to be written into the memory
location or I/O.
A control bus: this manages the information
flow between components indicating whether
the operation is a read or a write and
ensuring that the operation happens at the
right time.
6
 RISC and CISC in Computer
Organization
RISC-Reduced Instruction Set Computing -
is the way to make hardware simpler
CISC-Complex Instruction Set Computing -
is the single instruction that handles
multiple work.

7
 Introduction: CISC
CISC means Complex Instruction Set
Computing.
Since the earliest machines were
programmed in assembly language and
memory was slow and expensive, the CISC
philosophy was commonly implemented in
large computers.

8
 Complex Instruction Set
Architecture (CISC)
The main idea is that a single instruction
will do all loading, evaluating, and storing
operations , hence it’s complex
The focus was on enhancing CPU speed by
minimizing the number of instructions per
program

9
 Most common microprocessor designs such
as the Intel 80x86 and Motorola 68K series
followed the CISC philosophy.

10
 CISC Attributes
CISC instructions sets have some common
characteristics:
 A 2-operand format, where instructions
have a source and a destination. Register
to register, register to memory, and
memory to register commands.
 Variable length instructions where the
length often varies according to the
addressing mode
 Instructions require multiple clock cycles
to execute.
11
  A small number of general purpose registers -
This is the direct result of having instructions
which can operate directly on memory.

 Several special purpose registers-Many CISC

designs set special registers for the stack
pointer, interrupt handling, and so on.
 Presence of 'Condition code" registers which is
set as a side-effect of most instructions-eg-:
PSW

12
 Major characteristics of a CISC
architecture
 A large number of instructions - typically
from 100 to 250 instruction
 Some instructions that perform
specialized tasks and are used infrequently
 A large variety of addressing modes -
typically from 5 to 20 different modes
 Variable-length instruction formats( 1 byte
, 2 byte, 3byte…)
 Instructions that manipulate operands in
memory

13
 What is RISC?
RISC, or Reduced Instruction Set
Computer, is a type of microprocessor
architecture that utilizes a small, highly-
optimized set of instructions, rather than
a more specialized set of instructions.

14
 History
The first RISC projects came from IBM,
Stanford, and UC-Berkeley in the late
70s and early 80s.
The IBM 801, Stanford MIPS, and
Berkeley RISC 1 and 2 were all designed
with a similar philosophy which has
become known as RISC.

Certain design features have been

characteristic of most RISC processors:
15
  One cycle execution time: RISC processors have
a CPI (clock per instruction) of one cycle. (This
is due to the optimization of each instruction on
the CPU and a technique called PIPELINING)
 PIPELINING : a technique that allows for
simultaneous execution of parts, or stages, of
instructions to more efficiently process
instructions;
 Large number of registers: the RISC design
philosophy generally incorporates a larger
number of registers to prevent in large amounts
of interactions with memory
16
 Pipeline Organization
3-stage pipeline: Fetch – Decode - Execute
Three-cycle latency,
one instruction per cycle throughput

i
n
s
t i Fetch Decode Execute
r
u Fetch Decode Execute
i+1
c
t
i i+2 Fetch Decode Execute
o cycle
n
17 t t+1 t+2 t+3 t+4
 Only use LOAD and STORE instruction
when communicating between memory
and CPU.

 All other instructions are executed

within the registers of the CPU without
referring to memory.

LOAD & STORE ARCHITECTURE

18
 Major characteristics of a RISC
architecture
Relatively few instructions
Relatively few addressing modes
 Memory access limited to load and
store instructions
 All operations done within the registers
of the CPU
 Fixed-length, easily decoded instruction
format
 Single-cycle instruction execution

19
RISC Disadvantages
There is still considerable controversy
among experts about the ultimate value
of RISC architectures.
 Its proponents argue that RISC machines
are both cheaper and faster, and are
therefore the machines of the future.
However, by making the hardware
simpler, RISC architectures put a greater
burden on the software.
Is this worth the trouble because
conventional microprocessors are
becoming increasingly fast and cheap
anyway?
 RISC processors work with more
instructions; however, the number of cycles
an instruction may take to execute is
minimized.
In general terms, a RISC machine takes one
CPU cycle to complete one instruction.

21
 CISC versus RISC

CISC RISC

Emphasis on hardware Emphasis on software

Includes multi-clock Single-clock,
complex instructions reduced instruction only
Memory-to-memory: Register to register:
"LOAD" and "STORE" "LOAD" and "STORE"
incorporated in instructions are independent instructions
Small code sizes, Low cycles per second,
high cycles per second large code sizes
Transistors used for storing Spends more transistors
complex instructions on memory registers
 CISC vs RISC code

CISC Approach
MULT 2:3, 5:2

RISC Approach
LOAD A, 2:3
LOAD B, 5:2
PROD A, B
STORE 2:3, A
 Performance

The CISC approach attempts to minimize the

number of instructions per program,
sacrificing the number of cycles per
instruction.

 RISC does the opposite, reducing the cycles

per instruction at the cost of the number of
instructions per program.
Summation
As memory speed increased, and high-level
languages displaced assembly language, the
major reasons for CISC began to disappear,
and computer designers began to look at
ways computer performance could be
optimized beyond just making faster
hardware.
One of their key realizations was that a
sequence of simple instructions produces the
same results as a sequence of complex
instructions, but can be implemented with a
simpler (and faster) hardware design.
(Assuming that memory can keep up.) RISC
(Reduced Instruction Set Computers)
processors were the result.
 CISC and RISC implementations are
becoming more and more alike. Many of
today’s RISC chips support as many
instructions as yesterday's CISC chips. And
today's CISC chips use many techniques
formerly associated with RISC chips.
To some extent, the argument is becoming
moot because CISC and RISC
implementations are becoming more and
more alike. Many of today's RISC chips
support as many instructions as yesterday's
CISC chips. And today's CISC chips use
many techniques formerly associated with
RISC chips
26
  RISC vs. CISC controversy is now 20 years old.
 After the initial enthusiasm for RISC machines, there has
been a growing realization that
 RISC designs may benefits from the inclusion of some CISC
features, and
 Vice-versa.

 The result is that more recent RISC design, PowerPC and

SPARC, are no longer "pure" RISC and the more recent
CISC designs, notably the Pentium, AMD, and Core Duo
incorporate core RISC characteristics.

27
 Example RISC ISA:
PowerPC

8 addressing modes: Operand sizes:

 Register direct.
• Four operand sizes: 1, 2, 4 or 8 bytes.
 Immediate.
 Register indirect.
 Register indirect with
immediate index (loads and
stores). Instruction Encoding:
 Register indirect with
register index (loads and • Instruction set has 15 different
stores). formats with many minor variations.
 Absolute (jumps).
•

 • All are 32 bits in length.

Link register indirect (calls).
 Count register indirect
(branches).

28
 Example RISC ISA:
HP Precision Architecture, HP-PA

7 addressing Operand sizes:

modes: • Five operand sizes ranging in powers
of two from 1 to 16 bytes.
 Register
 Immediate
 Base with displacement
 Base with scaled index and
Instruction Encoding:
displacement • Instruction set has 12 different
 Predecrement •
formats.
 Postincrement • All are 32 bits in length.
 PC-relative

29
 Example RISC ISA:
SPARC

5 addressing modes: Operand sizes:

 Register indirect with • Four operand sizes: 1, 2, 4 or 8 bytes.
immediate displacement.
 Register inderect indexed by
another register. Instruction Encoding:
 Register direct.
• Instruction set has 3 basic instruction
 Immediate. formats with 3 minor variations.
 PC relative.
• All are 32 bits in length.

30
 RISC-V(5)
The development of the RISC-V standard
began in 2010 when researchers at the
University of California, Berkeley created a
simple, yet powerful ISA that could be used
by anyone with minimal restrictions.
 It was released in 2015 as a free and open-
standard ISA that allows anyone to design,
manufacture and sell processors based on
the RISC-V specification — without royalties
or license fees.

31
 RISC-V cores applications
including:

Artificial intelligence (AI) image sensors,

Security management,
AI computing,
Machine control systems for 5G networks.
 More sophisticated storage, graphics and
machine learning applications.

32
  This opened the door for a variety of
companies to develop their own RISC-V
processors, allowing them to innovate in
ways that would have been impossible
before for a wide variety of product
categories and applications.

33
 ARM

34
 The History of ARM
Developed at Acorn Computers Limited,
of Cambridge, England,
between 1983 and 1985
Problems with CISC:
 Slower then memory parts

 MULTIPLE Clock cycles per instruction

35
 The History of ARM (2)
Solution – the Berkeley RISC I:
 Competitive

 Easy to develop (less than a year)

 Cheap

 Pointing the way to the future

36
 Arm was officially founded as a company in
November 1990 as Advanced RISC
Machines Ltd, which was a joint venture
between Acorn Computers, Apple
Computer (now Apple Inc.), and VLSI
Technology (now NXP Semiconductors N.V).

37
 The maturing of Arm as a company led to
the increased diversification of its product
line through the Cortex-A, Cortex-R, and
Cortex-M CPU processors it brought to
market in the 2000s.
Cortex-A continued the drive towards
high-performance and efficiency in mobile
device markets, and Cortex-R focused on
highly specialized real-time requirements
in an age of increasing connectivity.

38
 Meanwhile, Cortex-M provided extremely
low-power, low-cost cores for
microcontrollers that were starting to
proliferate across the growing Internet of
Things (IoT).
 Also, in 2006, Arm purchased Falanx
Microsystems A/S, a spin-off of a research
project from the Norwegian University of
Science and Technology, which led to the
development of the Mali GPU product line.

39
 What Is ARM?
Advanced RISC Machine

First RISC microprocessor

for commercial use

Market-leader for low-power

and cost-sensitive embedded applications

40
 ARM Powered Products

41
 Architecture Revisions
ARMv7

ARM1156T2F-S™
version

ARM1136JF-S™

ARMv6

ARM1176JZF-S™
ARM102xE XScaleTM ARM1026EJ-S™

ARMv5

ARM9x6E ARM926EJ-S™
SC200™
ARM7TDMI-S™ StrongARM
®
ARM92xT

V4

SC100™ ARM720T™

1994 1996 1998 2000 2002 2004 2006

time
XScale is a trademark of Intel Corporation
 Features
Architectural simplicity which allows
Very small implementations which result in

Very low power consumption

43
 ARM Architecture
Typical RISC architecture:
 Large uniform register file

 Load/store architecture

 Simple addressing modes

 Uniform and fixed-length instruction fields

44
 ARM Architecture (2)
Enhancements:
 Each instruction controls the ALU and shifter

 Auto-increment
and auto-decrement addressing modes
 Multiple Load/Store

 Conditional execution

45
 ARM Architecture (3)
Results:
 High performance

 Low code size

 Low power consumption

 Low silicon area

46
 Pipeline Organization
Increases speed –
most instructions executed in single cycle
Versions:
3-stage (ARM7TDMI and earlier)
5-stage (ARMS, ARM9TDMI)
6-stage (ARM10TDMI)

47
 ARM 7
 ARM: ARM (Advanced RISC Machine), owned by Acorn, Apple

and VLSI.

 The ARM7 family was released in 1993.

 Three stage pipeline architecture.

 Von Neman model, with single data and instruction buses.

 The ARM7 core family consists of ARM700, ARM710, ARM7DI,

ARM710a, ARM720T, ARM740T, ARM710T, ARM7TDMI,

ARM7TDMI-S,
sctce ARM7EJ-S.
sctce
 ARM 7 Consists of:
 Arithmetic Logic Unit (32-bit)

 One Booth multiplier(32-bit)

 One Barrel Shifter

 One Control Unit

 Register file of 37 registers each of 32 bits

sctce
 Contd….
In addition:

 Program Status Register of 32 bits.

 Special registers like the instruction register,

memory data read and write register and

memory address register.

 One Priority encoder (for Load/ Store)

 Multiplexers

sctce
 ARM Registers
 ARM has a total of 37 registers .

 31 are general-purpose registers of 32-bits, and six status registers.

 The processor state and operating mode decide which registers are
available to the programmer.
 At any time, among the 31 general purpose registers only 16
registers are available to the user.
 The remaining 15 registers are used to speed up exception
processing.
 Two program status registers: CPSR and SPSR (the current and
saved program status registers, respectively)
sctce
 Registers Available to the User

 r0-r12…….. any instruction you can apply

 r13 acts as a stack pointer register
 r14 acts as a link register
 r15 acts as a program counter register.
sctce
 CPSR: Current Program Status Register

 Four fields, each of 8 bits wide : flags, status, extension,

and control.

sctce
 Flag
V, C , Z , N are the Condition flags
V (Overflow) : Set if the result causes a signed
overflow
C (Carry) : Is set when the result causes an
unsigned carry
Z(Zero) : This bit is set when the result after an
arithmetic operation is zero, frequently used to indicate
equality.
N (Negative) : This bit is set when the bit 31 of the
result is a binary 1.

sctce
 Processor Modes

 There are seven processor modes.

 Six privileged modes: abort, fast interrupt request,
interrupt request, supervisor, system, and
undefined

 One non-privileged mode called user mode.

sctce
 Banked Registers :
 Out of the 32 registers , 20 registers are

hidden from a program at different times.

These registers are called banked registers.

 They are available only when the processor is

in a particular mode.

sctce
 PIPELINE
MECHANISM

sctce
sctce
 Programmer's Model
Helps the programmer, how to use the core components of the
processor to program it.
Mode When does ARM enters in pericular mode?
Abort Failed attempt to access memory.
Fast interrupt
Interrupt request arrives through FIQ channel (input).
request
Interrupt request Interrupt request arrives through IRQ channel (input).
After reset. It is generally the mode that an OS Kernel
Supervisor
operates in.
Special version of user mode that allows full read-write
System
access to the CPSR.
When processor encounters an instruction. That is
Undefined
undefined or not supported by the implementation.
sctce
User mode Used for programs & applications
 Programmer's Model Contd….

sctce
 Model contd…

sctce
 Pipeline Organization (2)
3-stage pipeline: Fetch – Decode - Execute
Three-cycle latency,
one instruction per cycle throughput

i
n
s
t i Fetch Decode Execute
r
u Fetch Decode Execute
i+1
c
t
i i+2 Fetch Decode Execute
o cycle
n
63 t t+1 t+2 t+3 t+4
 Pipeline Organization (3)
5-stage pipeline: Stages:
Reduces work per cycle =>
allows higher clock Fetch
frequency
Decode
Separates data and
instruction memory => Execute
reduction of CPI
(average number Buffer/data

of clock Cycles Per Write-back

Instruction)
64
 Pipeline Organization (4)
Pipeline flushed and refilled on branch,
causing execution to slow down
Special features in instruction set
eliminate small jumps in code
to obtain the best flow through pipeline

65
 Operating Modes
Seven operating modes:
User

Privileged:
 System (version 4 and above)

 FIQ

 IRQ

 Abort exception modes

 Undefined

 Supervisor

66
 Processor Modes
 The ARM has seven basic operating modes:

 User : unprivileged mode under which most tasks run

 FIQ : entered when a high priority (fast) interrupt is raised

 IRQ : entered when a low priority (normal) interrupt is raised

 Supervisor : entered on reset and when a Software Interrupt

instruction is executed
 Abort : used to handle memory access violations

 Undef : used to handle undefined instructions

 System : privileged mode using the same registers as user mode

 Operating Modes (2)
User mode: Exception modes:
Normal program
Entered
execution mode
upon exception
System resources
Full access
unavailable
to system resources
Mode changed
Mode changed freely
by exception only

68
 Exceptions
Exception Mode Priority IV Address
Reset Supervisor 1 0x00000000
Undefined instruction Undefined 6 0x00000004
Software interrupt Supervisor 6 0x00000008
Prefetch Abort Abort 5 0x0000000C
Data Abort Abort 2 0x00000010
Interrupt IRQ 4 0x00000018
Fast interrupt FIQ 3 0x0000001C

Table 1 - Exception types, sorted by Interrupt Vector addresses

69
 Exception Handling
 When an exception occurs, the ARM:
 Copies CPSR into SPSR_<mode>
 Sets appropriate CPSR bits
 Change to ARM state
 Change to exception mode 0x1C FIQ
 Disable interrupts (if appropriate) 0x18 IRQ
 Stores the return address in LR_<mode> 0x14 (Reserved)
 Sets PC to vector address
0x10 Data Abort
 To return, exception handler needs to:
0x0C Prefetch Abort
 Restore CPSR from SPSR_<mode>
0x08 Software Interrupt
 Restore PC from LR_<mode>
0x04 Undefined Instruction
0x00 Reset
Vector Table
Vector table can be at
0xFFFF0000 on ARM720T
and on ARM9/10 family
devices
 ARM Registers
31 general-purpose 32-bit registers

16 visible, R0 – R15

Others speed up the exception process

71
 ARM Registers (4)
System & User FIQ Supervisor Abort IRQ Undefined
R0 R0 R0 R0 R0 R0
R1 R1 R1 R1 R1 R1
R2 R2 R2 R2 R2 R2
R3 R3 R3 R3 R3 R3
R4 R4 R4 R4 R4 R4
R5 R5 R5 R5 R5 R5
R6 R6 R6 R6 R6 R6
R7 R7_fiq R7 R7 R7 R7
R8 R8_fiq R8 R8 R8 R8
R9 R9_fiq R9 R9 R9 R9
R10 R10_fiq R10 R10 R10 R10
R11 R11_fiq R11 R11 R11 R11
R12 R12_fiq R12 R12 R12 R12
R13 R13_fiq R13_svc R13_abt R13_irq R13_und
R14 R14_fiq R14_svc R14_abt R14_irq R14_und
R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC) R15 (PC)
CPSR CPSR CPSR CPSR CPSR CPSR
72 SPSR_fiq SPSR_svc SPSR_abt SPSR_irq SPSR_und
 ARM Registers (2)
Special roles:
Hardware
 R14 – Link Register (LR):
optionally holds return address
for branch instructions
 R15 – Program Counter (PC)

Software
 R13 - Stack Pointer (SP)

73
 ARM Registers (3)
Current Program Status Register (CPSR)

Saved Program Status Register (SPSR)

On exception, entering mod mode:

(PC + 4)  LR
CPSR  SPSR_mod
PC  IV address
R13, R14 replaced by R13_mod, R14_mod
In case of FIQ mode R7 – R12 also replaced

74
 Instruction Set
Two instruction sets:

ARM
 Standard 32-bit instruction set

THUMB
 16-bit compressed form

 Code density better than most CISC

 Dynamic decompression in pipeline

75
 ARM Instruction Set
Features:

Load/Store architecture

3-address data processing instructions

Conditional execution

Load/Store multiple registers

Shift & ALU operation in single clock cycle

76
 ARM Instruction Set (2)
Conditional execution:
Each data processing instruction
prefixed by condition code
Result – smooth flow of instructions through
pipeline
16 condition codes:
unsigned signed greater
EQ equal MI negative HI GT
higher than
positive or unsigned lower signed less
NE not equal PL LS LE
zero or same than or equal
unsigned
signed greater
CS higher or VS overflow GE AL always
than or equal
same
77CC unsigned signed less special
VC no overflow LT NV
lower than purpose
 ARM Instruction Set (3)

ARM instruction set

Data processing
instructions
Data transfer
instructions
Block transfer
instructions
Branching instructions

Multiply instructions
Software interrupt
instructions

78
 Data Processing Instructions
Arithmetic and logical operations

3-address format:
Two 32-bit operands
(op1 is register, op2 is register or immediate)
32-bit result placed in a register

Barrel shifter for op2 allows full 32-bit shift

within instruction cycle

79
 Data Processing Instructions
(2)
Arithmetic operations:
ADD, ADDC, SUB, SUBC, RSB, RSC

Bit-wise logical operations:

AND, EOR, ORR, BIC

Register movement operations:

MOV, MVN

Comparison operations:
TST, TEQ, CMP, CMN

80
 Data Processing Instructions
(3)
Conditional codes
+
Data processing instructions
+
Barrel shifter
=
Powerful tools for efficient coded programs

81
 Data Processing Instructions
(4)

e.g.:

if (z==1) R1=R2+(R3*4)

compiles to

EQADDS R1,R2,R3, LSL #2

( SINGLE INSTRUCTION ! )

82
 Data Transfer Instructions
 Load/store instructions

 Used to move signed and unsigned

Word, Half Word and Byte to and from registers
 Can be used to load PC
(if target address is beyond branch instruction range)

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word
LDRSH Load Signed Half Word STRSH Store Signed Half Word
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte STRSB Store Signed Byte
83
 Block Transfer Instructions

Load/Store Multiple
instructions (LDM/STM)
Mi
Whole register bank or a LDM
Mi+1
subset R0 Mi+2
R1
copied to memory or
R2
restored Mi+14
with single instruction Mi+15
R14 STM
R15
84
 Swap Instruction
Exchanges a word
between registers R0
Two cycles R1
R2
but
single atomic R7
action R8

Support for RT
semaphores R15

85
 Modifying the Status Registers
Only indirectly
R0
MSR moves contents R1
from CPSR/SPSR to MRS
selected GPR R7

MRS moves contents CPSR MSR R8

SPSR
from selected GPR
to CPSR/SPSR R14
R15
Only in privileged
modes

86
 Multiply Instructions
Integer multiplication (32-bit result)

Long integer multiplication (64-bit result)

Built in Multiply Accumulate Unit (MAC)

Multiply and accumulate instructions add

product to running total

87
 Multiply Instructions
Instructions:

MUL Multiply 32-bit result

MULA Multiply accumulate 32-bit result

UMULL Unsigned multiply 64-bit result

UMLAL Unsigned multiply accumulate 64-bit result

SMULL Signed multiply 64-bit result

SMLAL Signed multiply accumulate 64-bit result

88
 Software Interrupt
SWI instruction
Forces CPU into supervisor mode
Usage: SWI #n

31 28 27 24 23 0
Cond Opcode Ordinal


Maximum 224 calls

Suitable for running privileged code and
making OS calls

89
 Branching Instructions
Branch (B):
jumps forwards/backwards
up to 32 MB
Branch link (BL): same
+ saves (PC+4) in LR
Suitable for function call/return

Condition codes for conditional branches

90
 Branching Instructions (2)
Branch exchange (BX) and
Branch link exchange (BLX):
same as B/BL + exchange
instruction set (ARM  THUMB)
Only way to swap sets

91
 Thumb Instruction Set
Compressed form of ARM
Instructions stored as 16-bit,
Decompressed into ARM instructions and
Executed

Lower performance (ARM 40% faster)

Higher density (THUMB saves 30% space)

Optimal –
“interworking” (combining two sets) –
compiler supported
92
 THUMB Instruction Set (2)
More traditional:
No condition codes
Two-address data processing instructions

Access to R0 – R8 restricted to
 MOV, ADD, CMP

PUSH/POP for stack manipulation

Descending stack (SP hardwired to R13)

93
 THUMB Instruction Set (3)
No MSR and MRS, must
change to ARM to modify CPSR (change
using BX or BLX)
ARM entered automatically after RESET or
entering exception mode
Maximum 255 SWI calls

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 The Next Step
New ARM Cortex family of processors
New NEON™ media and
signal processing extensions
Thumb®-2 blended 16/32-bit instruction set
for performance and low power
Improved Interrupt handling

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 Summary
Adoption of ARM technology
has increased efficiency and lowered costs
ARM is the world’s leading architecture today
 3 billion ARM Powered chips and counting

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 References
 www.arm.com

 ARM Limited ARM Architecture Reference

Manual, Addison Wesley, June 2000
 Trevor Martin The Insiders Guide To The Philips
ARM7-Based Microcontrollers, Hitex (UK) Ltd.,
February 2005
 Steve Furber ARM System-On-Chip Architecture
(2nd edition), Addison Wesley, March
2000

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 The End

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