UNIT – I

Course Objective: Familiarize SOI technology with Fin-FET and Back

gate FET

Introduction to SOI Technology:

• Need of low power design
• Sources of power dissipation: Switching Power
Dissipation, Short Circuit Power Dissipation,
Leakage Power Dissipation, Glitching Power
Dissipation
• Power dissipation in CMOS circuits
• MOS transistor leakage components
• SOI technology, Fin-FET, Back gate FET
 Power and energy basics
 Energy-delay product as a metric
• Design strategies for low power.
References:
1. J.Rabaey, Low Power Design
Essentials,1stEdition,Springer Publications,2010.
2. Kaushik Roy, Sharat C. Prasad, “Low Power
CMOS VLSI Circuit Design”, John Wiley &
Sons,2000.
3. Abdellatif Bellaouar,Mohamed Elmasry, Low-
Power Digital VLSI Design, Springer Science
Business Media ,LLC1995.
4.AjithPal, Low Power
VLSICircuits&Systems,Springer,2014
 VLSI-Very Large Scale Integration- Very-large-scale integration
(VLSI) is the process of creating an integrated circuit (IC) by
combining hundreds of thousands of transistors or devices into a
single chip.
 Design for low power has become nowadays one of the major
concerns for complex, very-large-scale-integration (VLSI) circuits.
 Micron Technology ==> 1μm, 2μm, 3μm, etc
 Sub-Micron Technology ==> 0.8μm, 0.6μm, 0.35μm 0.25μm etc
 Deep Sub-Micron Technology ==> 0.18μm, 0.13μm
 Nanotechnology ==> 90nm, 65nm etc
 Landmark Years of Semiconductor Industry
 1947: Invention of transistor by William Shockley in Bell Laboratories.
 1959: Fabrication of several transistors on a single chip (IC).
 1965: Birth of Moore’s law; based on simple observation, Gordon Moore
predicted that the complexity of ICs, for minimum cost, would double every
year.
 1971: Development of the first microprocessor—“CPU on a chip” by Intel.
 1978: Development of the first microcontroller—“computer on a chip.”
 1975: Moore revised his law, stipulating the doubling in circuit complexity
to every 18 months.
 1995: Moore compared the actual performance of two kinds of devices,
dynamic random-access memory (DRAM) and microprocessors, and
observed that both technologies have followed closely.
NEED for low power design
 Until 1990’s, there was greater emphasis on performance and miniaturization
 Power dissipation is of little concern.
 Due to miniaturization, many applications were developed which are battery powered.
◦ Pocket calculators
◦ Hearing aids
◦ Implantable pace makers
◦ Portable military equipment
◦ Wrist watches………
 It is required to prolong battery life as much as possible in all the above applications.
 In late 1990’s, the trend was towards
◦ Portable computing
◦ Wireless communications
◦ Continuous developments in micro electronics
Power dissipation has become the most critical factor.
The reasons for this could be
 improving performance
 integrate more and more functions on a chip
 technological developments (Feature size)
no. of functions ↑ - density ↑ - feature size ↓- power /unit area ↑- heat removal and cooling problems↑
VDD →5V → 3.3V → 2.5V → PD does not ↓
 NEED for low power
design
 Power is dissipated mostly in the form of heat: Vacuum tubes watts…. Transistor
milliwatts of power.
 The cooling techniques, such as air conditioner, transfer the heat to the
environment.
 Computational requirements of portable battery operated applications
◦ People expect to have same
 Computing power
 Information resources
 Communication abilities
While on travel as they do at their desk
 According to an estimate of the US Environmental Protection Agency (EPA), 80 %
of the power consumption by office equipment is due to computing equipment and
a large part from unused equipment.
 Thus in late 1990’s, power efficiency has become an essential goal in importance
with miniaturization and performance. Thus minimizing power is a conscious effort
at each level of abstraction and at each phase of design process.
 ◦ Why Low Power design ?

 Important issue in the present day VLSI circuit realization

 Increasing Transistor Count
 Higher Speed of Operation
 Greater Device Leakage Currents
 Packaging and Cooling Cost
 Contemporary high performance processor consume heavy power
 Cost associated with packaging and cooling such devices is prohibitive
 Low power methodology to be used to reduce cost of packaging and cooling
 Reliability
 Every 10°C rise in temperature roughly doubles the failure rate
  POWER and ENERGY
 Power is the instantaneous power in the device, while energy is the
integration of power with time. Figure 1.2 illustrates the difference
between power energy. For example, in Fig. 1.2, we can see that
approach 1 takes less time but consumes more power than approach 2.
But the energy consumed by the two, that is, the area under the curve for
both the approaches is the same, and the battery life is primarily
determined by this energy consumed.

Fig. 1.2 Power versus Energy

 Power dissipation is measured commonly in terms of two types of
metrics:
 Peak power: Peak power consumed by a particular device is the highest amount
of power it can consume at any time. The high value of peak power is generally
related to failures like melting of some interconnections and power-line glitches.
 Average power: Average power consumed by a device is the mean of the
amount of power it consumes over a time period. High values of average power
lead to problems in packaging and cooling of VLSI chips.
 Types of Power Dissipations:
Dynamic power is the power consumed when the device is active,
that is, when the signals of the design are changing values. It is generally
categorized into three types:
 Switching Power
 Short-Circuit Power
 Glitching Power

 Static power is the power consumed when the device is powered up but
no signals are changing value. In CMOS devices, the static power consumption
is due to leakage mechanism.
 Sources of power
 dissipation
Dynamic Power dissipation in logic is
due to
1.Logic transition (nodes)
2.Short circuit currents
3. Leakage currents
1.Dynamic power (or switching power
dissipation due to logic transition):
◦ Requires charging and discharging of
parasitic capacitances
◦ CURRENT flows through channel
resistance
◦ Electrical energy → heat energy
This component is a function of supply
voltage, node voltage swing, and
average switched capacitance/ cycle.
 Sources of power
2. Short circuitdissipation
power:
◦ Due to current that flows from supply node to ground
◦ It’s a function of input and output transition times
3. Glitching Power Dissipation
 The third type of dynamic power dissipation is the
glitching power which arises due to finite delay of the
gates. Glitches often occur when paths with unequal
propagation delays converge at the same point in the
circuit. Glitches occur because the input signals to a
particular logic block arrive at different times, causing a
number of intermediate transitions to occur before the
output of the logic block stabilizes. These additional
transitions result in power dissipation, which is
categorized as the glitching power.
4.Leakage power:
◦ It is due to flow of current when both inputs and
therefore outputs of the circuits are not changing.
◦ As the supply is scaled, leakage current has become
considerable part of the total current in the circuit.
Designing for low power
Supply scaling
Threshold scaling
Transition component of power:
◦ Frequency of operation
◦ Probability of occurrence of input signals
Frequency maximization→ low VDD and Low
Vth devices → static power↑
Low Vdd → PDP ↓ and Delay ↑- which needs
to be compensated.
Delay can be compensated by increasing
w/L ratio
Dynamic power
consumption
Each time the capacitor CL gets charged
through the PMOS transistor, its voltage
rises from 0-VDD, and ascertain energy is
drawn from power supply.
Part of this energy is dissipated in PMOS,
while the remaining is stored in CL.
During a VDD-0 transition, this capacitor
discharges and stored energy is
dissipated in NMOS transistor.
•Power dissipation in CMOS circuits:
 Dynamic and static power dissipation
1. SWITCHING POWER DISSIPATION:
 Each switching cycle takes a fixed amout of energy equal to CLVDD2.
 In order to compute the power, we need to consider how often the device is switched
 If gate is switched on and off f0->1 times per second, the power consumption is given by

f
2
P Dyn C LV DD 0  1

•Advances in technology result in ever-higher values of f0->1

•At the same time total capacitance increases as more and more
gates are placed on a single die
•For a 0.25 micron tech CMOS chip with clock rate of 500MHz
and an average load capacitance of 15fF/gate and with a fanout of
4
•The power consumption per gate for a 2.5V supply equals 50
micro watts.
•For 1million gates, assuming transition on every clock edge,
results in power consumption of 50W!
 Computing the dissipation of complex circuit is complicated by f0->1,
called switching activity.
 Switching activity is a function of nature and statistics of input
signals
 If no switching happens, dynamic power is zero.
 When input changes rapidly, plenty of switching and therefore
dynamic dissipation comes.
 Activity is also a function of topology of network
 Reducing VDD has a quadratic effect on dynamic power.
 Reduction in switching activity can only be achieved at logic and
architectural abstractions only.
 Lowering the physical capacitance helps in performance
improvement.
 Capacitance can be minimized by using transistors of minimum size
where ever reasonable or possible.
 The effect on circuit performance can be compensated by
parallelization techniques.
 2. Short circuit power
 In actual designs, the assumption of zero rise and fall times
of input signals is not correct.
 The finite slope causes direct currents to flow between
supply and ground for short period of time during
switching at the point 0.5VDD.
 This direct path power dissipation is proportional to
switching activity similar to capacitive power dissipation.
 Short circuit path exists in dynamic circuits as precharge
and evaluation transistors.
3.Glitching Power Dissipation

 The third type of dynamic power dissipation is the glitching

power which arises due to finite delay of the gates. Since
the dynamic power is directly proportional to the number of
output transitions of a logic gate, glitching can be a
significant source of signal activity and deserves mention
here.
 Glitches often occur when paths with unequal propagation
delays converge at the same point in the circuit. Glitches
occur because the input signals to a particular logic block
arrive at different times, causing a number of intermediate
transitions to occur before the output of the logic block
stabilizes. These additional transitions result in power
dissipation, which is categorized as the glitching power.
Static power dissipation
In normal CMOS circuits static power is due
to leakage currents of transistors.
When input =0, leakage current is due to
nMOS, Id0n, and is due to pMOS when input
=1, Id0p.
 PS = Vdd (Id0p + Id0n )/2.
This component of power is normally very
low for LSI and VLSI with large channel
lengths.
 For the devices with low Vth, leakage
currents increase and became important.
For techniques other than CMOS, static
power is dominating.
Static power dissipation
 Leakage currents – due to reverse bias diode leakage at
transistor drains and sub-threshold leakage through the
channel of an OFF device.

Diode leakage:
• Occurs when Tr is turned off and
other active device charges
up/down the drain
• With the exponential
dependence, with small increase
in reverse voltage, leakage
current will equal reverse
saturation current
MOS transistor leakage components:
Components of ILeak
Tunneling currents : current
across the thin gate oxide
between gate and substrate
◦ It is due to high electric field in the
gate oxide
◦ Direct tunneling through oxide bands
occurs in nanometric devices.
◦ Also be called as gate oxide
tunneling
Components of ILeak
Sub-threshold conduction : Ileak
flow from drain to source.
◦ When Vgs <Vt, the device surface is
in weak inversion or depletion.
◦ Sufficient charge carriers are on the
surface region that can still create a
significant current flow.
◦ It is also called as weak inversion
current
Components of ILeak
Gate Induced Drain Lowering (GIDL):
currents flowing from gate-to-drain
Electrons tunnel through the gate-to-
drain overlap region
◦ Due to tunneling of electrons from valance to
conduction band in drain – substrate junction
below gate-drain overlap region where high
electric field exists.
◦ It occurs at low VG and high VD bias and
generates carriers into substrate and drain
from surface traps.
◦ It is localized along the channel width.
MOS TRANSISTOR leakage components include:
 Gate oxide tunneling: Electrons tunnel through the gate oxide from the substrate
to the gate, and vice versa.
 Subthreshold leakage current: A leakage current that occurs in an nMOS transistor

 Gate-Induced Drain Leakage (GIDL): Electrons tunnel through the gate-to-

drain overlap region
 Hot carrier injection: Hot carriers are injected from the substrate to the gate
oxide
 Junction leakage currents: Leakage currents that occur at the drain-substrate
and source-substrate junctions
 Band-to-Band Tunneling (BTBT) leakage: A leakage mechanism that occurs
when the 'n' and 'p' regions are heavily doped
 SOI (Silicon-On-Insulator) technology is a semiconductor fabrication process that uses an
insulating layer, typically silicon dioxide (SiO2), between a silicon substrate and the active silicon layer. This
architecture improves the performance of semiconductor devices by reducing parasitic capacitance and power
consumption, and by offering better isolation between the device and the substrate. SOI technology is often
used in advanced semiconductor manufacturing processes to improve the performance, power efficiency, and
reliability of integrated circuits, especially as transistor sizes continue to shrink.
 Advantages:
◦ Reduced Parasitic Capacitance: The insulating layer minimizes the interaction between the active layer
and the bulk silicon, reducing parasitic capacitance, which allows transistors to switch faster and consume
less power.
◦ Better Isolation: The insulating layer prevents leakage currents between the transistor and the substrate,
improving performance and reducing noise.
◦ Lower Power Consumption: By reducing leakage currents and improving overall efficiency, SOI
technology helps lower power consumption in integrated circuits.
◦ Faster Switching Speeds: With reduced capacitance and better isolation, devices in SOI technology tend
to switch faster than their bulk silicon counterparts.
◦ Heat Management: SOI can help with better thermal dissipation compared to bulk silicon, because the
insulating layer can allow for more controlled heat flow.
 Applications:
◦ Mobile Devices: The power efficiency and fast switching characteristics of SOI make it well-suited for
mobile processors.
◦ High-Performance Computing: Due to its performance benefits, SOI is often used in high-speed or
high-frequency circuits.
◦ RF (Radio Frequency) Circuits: SOI technology is used in RF applications because of its reduced
parasitic capacitance and better isolation.
◦ Space and Harsh Environments: SOI is more resistant to radiation, making it suitable for space and
aerospace applications.
FINFET
 Fin-FET (Fin Field-Effect Transistor)
 A Fin-FET is a type of 3D transistor used in advanced semiconductor technology,
particularly for smaller process nodes (such as 14 nm, 10 nm, and below). Unlike traditional
planar transistors, a Fin-FET has a 3D structure that provides better control over the flow
of current, leading to improved performance, reduced power consumption, and scalability
for smaller nodes.
 Advantages of Fin-FET:
 Better Control: The 3D gate structure provides better control over the current flow in the
channel, reducing leakage and improving performance at smaller process nodes.
 Reduced Short-Channel Effects: By improving electrostatic control, Fin-FETs mitigate the
short-channel effects that traditional planar MOSFETs experience as the channel length
shrinks.
 Lower Power Consumption: With better control and reduced leakage, Fin-FETs consume
less power, especially in low-voltage and high-frequency applications.
 Higher Performance: The enhanced gate control leads to higher drive currents, enabling
faster switching speeds.
 Scalability: As process nodes continue to shrink, Fin-FETs offer a more scalable solution
compared to traditional planar devices.
 Applications:
 Advanced Process Nodes: Fin-FET technology is commonly used in high-performance
CPUs, GPUs, and other integrated circuits at cutting-edge process nodes (14 nm and below).
 Low Power Devices: Its low leakage current and efficient power consumption make Fin-
FETs ideal for mobile devices and low-power applications.
FINFET
 Back-Gate FET (Back-Gate Field-Effect Transistor)
 A Back-Gate FET (or back-gated transistor) is a variation of the traditional field-
effect transistor (FET) where the transistor has an additional gate, often referred to
as the back gate, in addition to the regular front gate that controls the channel.
 Advantages of Back-Gate FET:
 Improved Control over Threshold Voltage: The back-gate can be used to fine-
tune the threshold voltage of the transistor, improving its switching characteristics.
 Better Isolation: The back gate can be used to improve isolation between different
parts of the circuit, reducing interference and noise.
 Reduced Short-Channel Effects: Like Fin-FETs, back-gate FETs help mitigate
some of the short-channel effects, as the back gate provides extra control over the
channel.
 Flexibility in Design: With two gates (front and back), designers have more
freedom to control the performance of the transistor, which is useful in advanced
semiconductor applications.
 Applications:
 Low-Power and High-Performance Devices: The back-gate provides an
additional layer of control that can be beneficial for fine-tuning devices in low-
power or high-performance applications.
 Advanced Semiconductor Nodes: As with Fin-FETs, back-gate FETs are also
often considered for smaller nodes where traditional FET technology faces
challenges.
Comparison and Relation:
Fin-FET: A 3D transistor that improves
electrostatic control over the channel and
reduces short-channel effects, ideal for
scaling down to smaller process nodes.
Back-Gate FET: A 2D or 3D transistor
where an additional gate (back gate) allows
further control over the device's
characteristics, useful for fine-tuning
performance, especially in advanced
designs
FINFET TECHNOLOGY
ADVANTAGES OVER CMOS

https://youtu.be/t6Y41zdO3Pc?
si=g0geTwLuxm7WFMeT
 Power and Energy: Basics
Power and energy are fundamental concepts in physics and engineering, especially in electrical and electronic systems. Though often used
interchangeably, they represent different quantities and are crucial to understanding how devices and systems operate.

1. Energy:Energy is the capacity to do work. It can exist in various forms, such as electrical, mechanical, thermal, chemical, and
more.
 Unit of Energy: The unit of energy in the International System of Units (SI) is the Joule (J).
o 1 Joule = 1 Newton meter (N·m).
 Common Forms of Energy:
o Electrical Energy: Stored in electric fields (batteries) or generated by power sources (generators).
o Mechanical Energy: Associated with the motion and position of objects.
o Thermal Energy: Related to temperature and heat.
 Energy Calculation in Electrical Systems:
o Electrical energy is calculated as: E=P×tE Where:
 E= Energy (in Joules)
 P = Power (in Watts)
 t= Time (in seconds)

2. Power: Power is the rate at which energy is transferred or converted. It measures how quickly work is done or energy is used.
 Unit of Power: The SI unit of power is the Watt (W).
o 1 Watt = 1 Joule per second (J/s).
 Power in Electrical Circuits:
o In electrical systems, power can be expressed as: P=V×IP Where:
 P = Power (in Watts)
 V = Voltage (in Volts)
 I = Current (in Amperes)
This equation shows that power is the product of the voltage across a component and the current flowing through it.
 Energy-Delay Product (EDP) as a Metric
 The Energy-Delay Product (EDP) is an important performance metric
used in the design and evaluation of digital circuits, particularly for
systems that require a balance between energy consumption and
performance (in terms of speed). It is used to quantify the trade-off
between the energy efficiency and the speed of a system or component,
such as a processor or a circuit.
 In simpler terms, the Energy-Delay Product provides a combined
measure of how much energy is consumed to perform a given amount of
computation within a specified time.
 Formula for Energy-Delay Product (EDP)
 EDP=Energy×Delay
 Where:
 Energy is the total energy consumed during the operation, typically
measured in Joules (J).
 Delay is the time it takes to complete the operation, usually measured in
seconds (s).
 Design Strategies for Low Power in Digital Circuits

 In modern electronics, minimizing power consumption is a critical

design goal, particularly in mobile devices, battery-powered
systems, and large-scale integrated circuits (like processors, SoCs,
and FPGAs). Power efficiency not only extends battery life but also
improves the overall performance, thermal management, and
reliability of systems.
 key design strategies for achieving low power in digital circuits:
 Voltage Scaling: Dynamic Voltage and Frequency Scaling (DVFS): DVFS
involves adjusting the voltage and frequency of the system based on workload
requirements. During periods of low activity, voltage and frequency can be
reduced, saving power.
 Multi-Vth (Multiple Threshold Voltages): Using transistors with
different threshold voltages in different parts of the circuit can help
balance speed and power consumption.
2. Clock Gating:Clock gating is a technique where the clock signal is selectively
disabled to portions of the circuit that are not actively switching. This reduces
dynamic power dissipation, as no activity (and hence no energy consumption)
occurs in the gated circuits.
3. Power Gating: Power gating involves turning off the supply voltage to certain
blocks of the circuit when they are not in use.
4. Clock Domain Partitioning: In systems with multiple clock domains (i.e., parts of
the system that operate on different clock signals), clock domain partitioning helps
to isolate sections of the circuit, reducing power consumption by ensuring that
inactive sections are not being clocked unnecessarily.
5. Reducing Switching Activity: Reducing the number of transitions or switching
events in a digital circuit can lower dynamic power dissipation, as power is
consumed during transitions between logic states.
6. Low Power Design Techniques
7. Reducing Leakage Power
8. Hardware Accelerators and Co-Processors:For certain computation-heavy tasks
(e.g., signal processing, machine learning), using specialized hardware
accelerators or co-processors (such as GPUs or dedicated ASICs) can significantly
reduce power consumption compared to general-purpose processors