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Presentation 3

The document discusses parallel computer structures, focusing on three main types: pipeline computers, array processors, and multiprocessor systems. It explains the functioning and performance metrics of pipelined execution, including speed up, efficiency, and throughput, as well as the characteristics and types of array and multiprocessor systems. Additionally, it highlights the importance of interconnection networks and performance metrics for parallel computers.

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19 views37 pages

Presentation 3

The document discusses parallel computer structures, focusing on three main types: pipeline computers, array processors, and multiprocessor systems. It explains the functioning and performance metrics of pipelined execution, including speed up, efficiency, and throughput, as well as the characteristics and types of array and multiprocessor systems. Additionally, it highlights the importance of interconnection networks and performance metrics for parallel computers.

Uploaded by

hibanahm12
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Module 1

presentation 3
Parallel Computer structures

 Parallel Computer systems that emphasize


parallel processing.
Division of parallel computers:
1. Pipeline computers
2. Array processors
3. Multiprocessor systems.
1. Pipeline computers :

 A pipeline computer performs overlapped computations to


exploit temporal parallelism.
Normally, the process of executing an instruction in a digital
computer
involves 5 major steps:
a) instruction fetch(IF) from the main memory.
b) instruction decoding(ID),identifying the operation to be performed.
c) operand fetch(OF),if needed in the execution, and
d) execution(IE) of the decoded arithmetic logic operation.
e) Output storage(OS)
 In a nonpipelined computer, these 4 steps must be completed
before the next instruction can be issued
 pipelined – successive instructions are executed in
overlapped fashion.
 2 ends – input end and the output end.
 Between these ends, there are multiple
stages/segments such that output of one stage is
connected to input of next stage with each
stage ,a specific operation.
 Interface registers are used to hold the
intermediate output between two stages. These
interface registers are also called latch or buffer.
 All the stages in the pipeline along with the
interface registers are controlled by a common
clock.
 If each stage takes one clock cycle, then we can
see that single instruction may take several
cycles to complete.
 Execution sequence of instructions in a pipelined
processor can be visualized using a space-time
diagram. (as above fig.)
Performance of Pipelined Execution

 parameters to estimate the performance of pipelined execution:


1. Speed Up :
It gives an idea of “how much faster” the pipelined execution is
as compared to non-pipelined execution.
Speed Up(S)=Non pipelined execution time/pipelined execution
time
2. Efficiency:
It gives an idea of “how much efficient” the pipelined execution
is as compared to non-pipelined execution.
Efficiency(ᵑ)=Speedup/Number of stages in Pipelined architecture
3. Throughput:
Throughput is defined as number of instructions executed per
unit time.
Throughput=Number of instruction executed/Total time taken
 Types of pipeline:
a) Uniform delay pipeline:
In this type of pipeline, all the stages will take same time to
complete an operation.
uniform delay pipeline supports,
Cycle Time (Tp) = Stage Delay
If buffers are included between the stages then,
Cycle Time (Tp) = Stage Delay + Buffer Delay
b) Non-Uniform delay pipeline:
In this type of pipeline, different stages take
different time to complete an operation
Non uniform delay pipeline supports,
Cycle Time (Tp) = Maximum(Stage Delay)
If buffers are included between the stages,
Tp = Maximum(Stage delay + Buffer delay)
2. Array processors:

 An array processor uses multiple synchronized


arithmetic logic units to achieve spatial
parallelism.
 An array processor is a synchronous parallel
computer with multiple arithmetic logic units,
called processing elements (PE) , that can operate
in parallel in a lockstep fashion.
 By replication of ALUs, one can achieve the
spatial parallelism .
 The PEs are synchronized to perform the same
function at the same time.
 An appropriate data –routing mechanism must
be established among the PEs.
 Array Processor performs computations on large
array of data.
 An eg.
adding two groups of 10 numbers together.
ie, ARRAY PROCESSING
Types of Array Processor :

 There are two types of Array Processors:


a) Attached Array Processor
b) SIMD Array Processor.
a) Attached Array Processor :
It is an auxiliary processor attached to a general
purpose computer, to improve the performance
of the host computer in specific numeric calculation
tasks.
b) SIMD Array Processor:
It is an array processor that has a single instruction multiple data
organization.
SIMD is the organization of a single computer containing multiple
processors operating in parallel.
The processing units are made to operate under the control of a
common control unit thus providing a single instruction stream
and multiple data streams.
 It contains a set of identical processing elements
(PE's), each of which is having a local memory M.
 Each processor element includes an ALU and
registers
 The master control unit controls all the
operations of the processor elements. It also
decodes the instructions and determines how the
instruction is to be executed.
 The main memory is used for storing the
program.
 The control unit is responsible for fetching the
instructions.
 Vector instructions are send to all PE's
simultaneously and results are returned to the
memory.
Array Processor-merits

1. Array processors increases the overall instruction


processing speed.
2. As most of the Array processors operates a CPU,
hence it improves the overall capacity of the
system.
3. Array Processors has its own local memory,
hence providing extra memory for systems
with low memory.
3. Multiprocessor systems:

 A multiprocessor system is defined as "a system


with more than one processor", and, more
precisely, "a number of central processing units
linked together to enable parallel processing
to take place".
 The key objective of a multiprocessor is to boost
a system's execution speed.
 These systems have m processors working in
parallel that share the computer clock, memory,
bus,peripheral devices etc
Multiprocessor architecture
Types of Multiprocessors

1. Symmetric multiprocessors :
each processor contains a similar copy of
the operating system and they all communicate
with each other.
All the processors are in a peer to peer
relationship
ie, no master - slave relationship exists
between them.
2. Asymmetric multiprocessors:
each processor is given a predefined task.
There is a a master processor that gives instruction
to
all the other processors.
Asymmetric multiprocessor system contains a
master slave relationship.
Asymmetric multiprocessor was the only type of
multiprocessor available before symmetric
multiprocessors were created
Characteristics of multiprocessors

1.
A multiprocessor system is an interconnection of two or
more CPUs with memory and input-output equipment.
2. Multiprocessors are classified as multiple instruction
stream, multiple data stream (MIMD) systems.
3. Multiprocessing improves the reliability of the system.
4. Multiprocessing can improve performance by
decomposing a program into parallel executable tasks.
5. Multiprocessor are classified by the way their memory is
organized.
 A multiprocessor system with common shared
memory is classified as a shared-memory or
tightly coupled multiprocessor.
 Each processor element with its own private local
memory is classified as a distributed-memory
or loosely coupled system
 There are several physical forms available for
establishing an interconnection
network.
a) Time-shared common bus
 A common-bus multiprocessor system consists of a
number of processors connected through a common
path to a memory unit.
b) Multiport memory
employs separate bus between each
memory module and each CPU.
The module must have internal control logic
to determine which port will have access to
memory at any given time.
Memory access conflicts are resolved by
assigning fixed priorities to each memory port.
c) Crossbar switch:
Consists of a number of crosspoints that are
placed at intersections between processor buses
and memory module paths.
The small square in each crosspoint is a
switch that determines the path from a
processor to a memory module.
Metrics for the performance of
parallel computers:
1.
P – processing unit

 2. Efficiency

E(p)=S(p)

p
O – opertions on P

 3. Redundancy

R(p)=O(p)

O(1)
 4. Utilization

U(p)=R(p) X E(p)
Data flow computers:

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