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Array Processor

Array processors are synchronous arrays of parallel processors that operate under a control unit and utilize SIMD (single instruction, multiple data) streams for vector computations. They can be organized in two main architectures: array processors with random-access memory and associative processors with content-addressable memory. Masking schemes enable selective activation of processing elements during instruction execution, allowing for efficient computation across multiple data streams.

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9 views

Array Processor

Array processors are synchronous arrays of parallel processors that operate under a control unit and utilize SIMD (single instruction, multiple data) streams for vector computations. They can be organized in two main architectures: array processors with random-access memory and associative processors with content-addressable memory. Masking schemes enable selective activation of processing elements during instruction execution, allowing for efficient computation across multiple data streams.

Uploaded by

jungkookietitli13
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Array Processors

• A synchronous array of parallel processors is called an array


processor, which consists of multiple processing elements (PEs)
under the supervision of one control unit (CU).
• An array processor can handle single instruction and multiple
data (SIMD) streams. In this sense, array processors are also
known as SIMD computers.
• SIMD machines are especially designed to perform vector
computations over matrices or arrays of data.
• SIMD computers appear in two basic architectural organizations:
 array processors, using random-access memory
 associative processors, using content-addressable (or associative)
memory.
SIMD Computer Organizations
Control Unit

PE1 PE2 PE3 PEn-1 PEn

PEM1 PEM2 PEM3 PEMn-1 PEMn

Interconnection Network

Configuration I (Used in Illiac IV machine)


SIMD Computer Organizations
Control Unit

PE1 PE2 PE3 PEn-1 PEn

Interconnection (or Alignment) Network

PEM1 PEM2 PEM3 PEMn-1 PEMn

Configuration II (Used in BSP)


SIMD Computer Organizations
• Masking schemes are used to control the status of each PE during
the execution of a vector instruction.
• Each PE may be either active or disabled during an instruction
cycle.
• A masking vector is used to control the status of all PEs.
• In other words, not all the PEs need to participate in the execution
of a vector instruction. Only enabled PEs perform computation.
• An array processor is normally interfaced to a host computer
through the control unit.
 The host computer is a general-purpose machine, which serves as the
"operating manager" of the entire system.
 Array processor is considered a back-end, attached computer.
Masking and Data-Routing Mechanisms
To CU

Ai Bi Ci

Di Ii Ri
PEi To other PEs via
interconnection
network
Si
ALU

PEM i
Masking and Data-Routing Mechanisms
• Each PEi is a processor with its own memory PEMi ; a set of working
registers and flags, namely Ai, Bi, Ci, and Si ; an arithmetic logic unit;
a local index register Ii; an address register Di; and a data-routing
register Ri.
• The Ri of each PEi is connected to the Rj of other PEs via the
interconnection network. When data transfer among PEs occurs, it
is the contents of the Ri registers that are being transferred.
• Some array processors may use two routing registers, one for input
and the other for output. Each PEi is either in the active or in the
inactive mode during each instruction cycle.
• If a PEi is active, it executes the instruction broadcast to it by the CU.
If a PEi is inactive, it will not execute the instructions broadcast to it.

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