CSE477 VLSI Digital Circuits Fall 2003 Lecture 27: System Level Interconnect

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

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The Nature of Interconnect

Local Interconnect

Global Interconnect

From Kang, 87
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Global Interconnect

Classes of global interconnects

System level signal interconnect - buses Global set and reset lines System clock(s) VDD and GND planes

Classes of parasitics

capacitive resistive inductive

Impacts of parasitics

Reduced reliability (crosstalk) Reduced performance

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System Level Signal Interconnect

Wout Xout Yout Zout Bus receivers Bus Tristate Bus drivers

Ain

Bin

Cin

Din

Many drivers - only one active at a time Many receivers - many may be active at a time

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Tristate Buffers

Three states - 0, 1, and Z (high impedance)

0
In 1 1

In En

Out

!En
En

!In Out Z (disconnected)

For driving large loads

avoid stacked transistors in the output gate (as in above) since it has to be sized to drive the load (thus stacked transistors would incur a large area overhead)

En 1

In !En 1 0

Z Out !In

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Reducing Effective Capacitance

Wout Xout

Wout

Xout

Yout

Zout

Ain

Bin

Yout
Ain Bin Cin Din

Zout

Cin

Din

Shared resources may also incur extra switching activity impacting the energy consumption
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Driving Large Capacitive Loads

Large fan out on-chip loads can be in the multi-picofarad range; off-chip loads can be as large as 50pF

Design techniques for driving large loads

Appropriately sized transistors in the driving gate Partitioning drivers into chains of gradually increasing (in size) buffers
- when optimizing for performance, the delay of a multi-stage driver should be divided equally over all stages - a fan-out (sizing) factor of 4 (FA4) per stage leads to the minimum delay for contemporary processes

Use better interconnect materials (like copper and low-K dielectrics) Introduce buffers (buffer (or repeater) insertion) into long wires to reduce the propagation delay
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Impact of Partitioned Drivers

For Ci of 2.5fF and CL of 20pF, F (overall effective fanout) = 8,000 leading to a 7 stage design with a scaling factor of f = 3.6 and a propagation delay (tp) of 0.76ns.
PMOS/NMOS ratio of 1.9

Stage

2
1.35 2.56

3
4.86 9.2

Wn (m) 0.375 Wp (m) 0.71

17.7 63 226.8 816.5 33.1 119.2 429.3 1545.5

Can trade-off performance for area and energy reduction. Setting tp,max to 2ns leads to a 3 stage design, f = 20, and tp = 1.8ns
Stage 1 2 3 Wn (m) 0.375 Wp (m) 0.71 7.5 14.2 150 284

Area savings of 7.5x; delay increased by ~ 2.5x; overall power dissipation reduced by ~24%
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Designing Large Transistors

Long polysilicon wires are highly resistive, degrading performance. So implement a wide transistor with many smaller transistors in parallel.
D(rain) D(rain)

2 more sections of diffusion

S(ource) G(ate) S(ource)

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G(ate)

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Impact of Better Interconnect Materials

Use better interconnect materials

As processes shrink, wires get shorter (reducing C) but they get closer together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse.
- Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner (reducing C) without increasing R

Use silicides (WSi2, TiSi2, PtSi2 and TaSi)

- Conductivity is 8-10 times better than poly alone

Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO2
- must also be suitable thermally and mechanically compatible with (copper) interconnect

Only buys one generation!

Drive long poly wires from both ends or use extra metal bypass wires

providing a bypass line every 16 cells for a poly word line driving 1024 cells in a memory core reduces the WL delay by ~4,000
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Impact of Buffer Insertion

The most popular design approach to reducing the propagation delay of long wires is to introduce intermediate buffers (repeaters) in the interconnect line.

making a wire m times shorter reduces its propagation delay quadratically and is sufficient to offset the extra delay of the repeaters (tpbuf) when the wire is sufficiently long mopt = L ((0.38rc)/tpbuf) = (tpwireunbuffered/tpbuf) tp,opt = 2 (tpwireunbuffered tpbuf)

For example, for a 10 cm long, 1 m wide wire and a tpbuf of 0.1ns, partitioning a AL1 wire into 18 sections would give an overall delay time of 3.5 ns (compared to the unbuffered delay of 32.4 ns). For poly the delay reduces to 212 ns (from 112 s) with 1,058 sections and for AL5 to 1.3 ns (from 4.2 ns) with 6 sections

Repeater insertion is an essential tool in combating long wire delays CSE477 L27 System Interconnect.12 Irwin&Vijay, PSU, 2003

Capacitive Coupling (Cross Talk)

Unwanted coupling with adjacent signal wires injects noise into a signal depending on the transient values of the other signals routed in the neighborhood
Crosstalk vs. Technology
Pulsed Signal 0.12m CMOS 0.16m CMOS

Black line quiet Red lines pulsed Glitches strength vs technology 0.25m CMOS 0.35m CMOS

From Dunlop, Lucent, 2000

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Dealing with Capacitive Cross Talk

Design Techniques

Avoid floating nodes. Nodes sensitive weak to cross talk problems (like precharged buses) should be equipped with keeper devices to reduce the impedance Separate, in the layout, sensitive nodes from full-swing signals Make the rise (fall) times as large as possible (beware of increases in short circuit power!) Use differential signaling in sensitive low-swing signals turning cross talk into a common-mode noise source Keep capacitances between wires small. Dont run two parallel wires on the same layer at minimum wire pitch for long distances. Run wires on adjacent layers perpendicular to each other. Provide shielding wires GND or VDD between two signals turning the interwire capacitance into a capacitance-to-GND. Interleave every signal layer with a GND or VDD metal plane.
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Shielding to Reduce Cross Talk

shielding wire
GND

signal wire

Vdd
GND

shielding layer

substrate (GND)

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Power Distribution Network

Ohmic drops that degrade the signal level are especially important in the power distribution network where current levels can easily reach amperes. Such IR drops

affect reliability impact the performance as even a small drop in VDD can cause a significant increase in delay

Design techniques for power distribution networks

Reduce the maximum distance between the supply pins and the circuit supply connections by adopting a structured layout of the power distribution network
- route power and ground vertically (or horizontally) inter-digitized on the same layer bringing power in from two sides of the die - use two metal layers for power distribution bringing power in from four sides of the die - use two solid metal planes for distribution of VDD and GND

Size the power network appropriately

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Next Lecture and Reminders

Next (!last!) lecture

Design for test for your reference only

- Reading assignment Rabaey, et al, Design Insert H.1-H.4

Technology trends and scaling Greg will guest lecture

- Reading assignment Rabaey, et al, 2.5; 3.5; 4.6; 5.6

Reminders

Final grading negotiations/correction (except for the project prototype/final and the final exam) must be concluded by tomorrow, December 10th Final exam scheduled
- Tuesday, December 16th from 10:10 to noon in 118 and 113 Thomas

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