Topics

• Features of ARM processors

• ARM architecture variants and processor families
• ARM7-TDMI internal architecture
• Register organization
• Pipelining
• Operating modes
• Exception handling
• ARM bus architecture
• Debug architecture
• Interface signals
N. Mathivanan
 ARM Processors
• Advanced RISC Machine -
ARM Ltd. not a manufacturing Co., provides license to manufacturers
Used in high end applications involving complex computation
Hand held device, Robotic, Automation system, Consumer electronics

• Features
High performance, low power, small in size (ideal for embedded sys)
Large Register File, Small instruction set, Load-Store instructions,
Fixed length instructions, Conditional execution of instructions,
High code density, most instructions executable in single cycle,
32-bit in-line barrel shifter, built-in circuit for hardware debugging,
DSP enhanced instructions, Jazelle (Java byte code extn. 3rd state),
TrustZone (SoC approach to security)

N. Mathivanan
 ARM Architecture Variants (core), Processor Families
• Each family has its own instruction set, mem management, etc.
Architectur Processor
Processor Features Microcontroller
e version Families
ARM7TDMI ARM720T Von Neumann,
LPC2100 series
(1995) ARM740T 3-stage pipeline
ARM v4T ARM920T
MMU, Harvard, SAM9G, LPC29xx,
ARM9TDMI ARM922T
5-stage pipeline LPC3xxx, STR9
ARM942T

ARM926EJ-S, MMU, DSP, Jazelle, SAM9XE

ARM9E
ARM946E-S, MPU, DSP
(1997)
ARM v5TE,
ARM966HS MPU (optional), DSP
ARM v5TEJ
ARM10E ARM1020E MMU, DSP
(1999) ARM1026EJ-S MMU/MPU, DSP, Jazelle

ARM1136J(F)-S MMU, TrustZone, DSP, Jazelle MSM7000, i.MX3x

ARM1156T2(F)-S MPU, DSP

ARM11
ARM v6
(2003) ARM1176JZ(F)-S, MMU, TrustZone, DSP, Jazelle BCM2835
MMU, Multiprocessor cache
ARM11 MP core
N. Mathivanan
support, DSP, Jazelle
 Processo
Architectur
r Processor Features Microcontroller
e version
Families

LPC1200, 1100 series

Cortex-M0 NVIC
STM32F0x0, x1, x2
ARM v6-M Cortex

Cortex-M1 FPGA TCM Interface, NVIC STM32F1, F2, L1, W

ST32F512-M, LPC1300,
ARM v7-M Cortex Cortex-M3 MPU (optional), NVIC
1700, 1800

STA1095, SAM4L,
Cortex-R4 MPU, DSP
SAM4N, SAM4S

ARM v7-R Cortex

SAM4C, SAM4E,
Cortex-R4F MPU, DSP, Floating Point LPC40xx, 43xx, STM32
F3, F4

MMU, Trust Zone, DSP,

Cortex-A8 Freescale i.MX5X
Jazelle, Neon, Floating Point
ARM v7-A Cortex
MMU, Trust Zone,
Cortex-A9 Multiprocessor, DSP, Jazelle, Freescale i.MX6QP
Neon,
N. Floating Point
Mathivanan
 ARM Nomenclature
• A R M x y z T D M I E J F S (Example: ARM7-TDMI-S)
x – Series
y – MMU
z – Cache
T – Thumb
D – Debugger
M – Multiplier
I – Embedded In-Circuit Emulator (ICE) macrocell
E – Enhanced Instructions for DSP
J – JAVA acceleration by Jazelle
F – Floating-point
S – Synthesizable version
N. Mathivanan
 ARM7-TDMI – Internal Architecture
Address Bus
A[31:0]
• Von Neumann architecture
Address Register

Incrementer Bus
• Data bus – 32-bit

PC Bus
Address
• Address bus – 32-bit Incrementer

Instruction Decoder and

Addressable memory space – 4 Register Bank
(31 x 32-bit registers)
(6 status registers)
GB

Logic Control
• Register bank – (31+6) 32-bit regs. 32 x 8
multiplier

ALU Bus
• In-line barrel shifter

A Bus

B Bus
Barrel Shifter
• Multiplier
• ALU ALU

• Incrementer
• Address register Data Out Register Data In Register

• Instruction decoder & control logic Data Bus D[31:0]

N. Mathivanan
 Register Organization
User Mode
31 gen. purpose registers.
r0
Only 16 regs accessible
r1
15 registers are hidden r2

Named as r0 – r15 r3

r4
r13,r14, r15 are SP, LR, PC
r5
8-bit/16-bit/32-bit data can r6
Banked Registers
FIQ
r7
be read/write
r8 r8_fiq

6 status registers r9 r9_fiq

r10 r10_fiq
Only 1 is accessible
r11 r11_fiq
IRQ Undef Abort SVC
Named as CPSR, SPSR r12 r12_fiq

r13_sp r13_svc
Contains flags, control bits r13_fiq r13_irq r13_und r13_abt

r14_lr r14_fiq r14_irq r14_und r14_abt r14_svc

r15_pc
Register bank has
CPSR
2 read and 1 write port and
SPSR_fiq SPSR_irq SPSR_und SPSR_abt SPSR_svc
N. Mathivanan
1 read and 1 write port for PC
• Bit definitions of Program Status registers
B31 B24 B23 B16 B15 B8 B7 B0
N Z C V I F T M4 M3 M2 M1 M0

Mode
Overflow
Carry Thumb State Flag
Zero FIQ Interrupt Mask
Negative IRQ Interrupt Mask

• Barrel shifter
Combinational logic circuit
Shifts left/right any no. of bits position in one cycle
Preprocess one of data from source reg. before passed to ALU

• Multiplier

32-bit x 8-bit with early termination, Booth Algorithm

32-bit x 32-bit in 5 cycles
Non M type multiplies in 32x2-bit and for 32-bitx32-bit - 17 cycles
N. Mathivanan
• ALU
Connected to register bank using A-bus and B-bus
ALU and barrel shifter operations take place in same cycle
Result of ALU operation goes back to register bank thro’ ALU bus

• Address register
Holds the address of next instruction to be fetched

• Instruction decoder and control logic

Enables interfacing peripherals to processors
Has Thumb decompressor –
Decompresses 16-bit Thumb code to 32-bit ARM code

N. Mathivanan
• Data Types
o Word – 32-bit, Halfword – 16-bit, Byte – 8-bit
o Memory is byte addressable, can hold 2 32 bytes (= 4 GB)
o Word/ halfword /byte size data are placed at word/ halfword/
byte aligned addresses.
o 32-bit ARM instructions are placed at word aligned addresses

• Byte order – Endian format

o Word/halfword size data can be saved/retrieved in big endian
or little endian format.
o Big endian: MSB of word/halfword data are stored in lowest
address and the data is addressed by address of MSB
o Little endian: LSB of word/halfword data are stored in lowest
address and the data is addressed by address of LSB
N. Mathivanan
 Pipelining
• Executes instructions in Fetch, Decode, Execute cycles – 3
stages
Thumb - ARM ARM Decode Register Register
Instruction Fetch Shift ALU
Decompression Register Select Read Write

FETCH DEC ODE EX E CU T E

• Pipelining increases flow of instructions to processor

• Enables processor and memory to work continuously
• Performs Fetch, Decode, Execute operations
Memory
simultaneously
T1 T2 T3 T4 T5
Example: ORR F D E

• In T1 cycle, fetch 1st instruction ADD F D E

SUB F D E
• In T2, fetch 2nd, decode 1st instructions
CMP F D
• In T3, fetch 3rd, decode 2nd, execute 1st AND F
F - Fetch, D - Decode, E - Execute
instructions. -----
Time
• In each cycle one instruction is executed
N. Mathivanan
 Pipelining Continued……
• PC points to memory address of instruction currently fetched
• Address of instruction currently decoded is PC-4
• Address of instruction currently executed is PC-8
• Branch instruction break pipeline, LDR/STR instruction stall
Memory

pipeline
T1
----- T2 T3 T4 T5 T6 T7 T8 Memory T1 T2 T3 T4 T5 T6 T7 T8
0x8000 BL 0x8020 F D E
ORR F D E
0x8004 SUB F D
F D Calc. Addr Data
0x8008 CMP F STR Transfer

----- SUB F D E
-----
CMP F D E
0x8020 AND F D E
AND F D E
0x8024 ADD F D E
F - Fetch, D - Decode, E - Execute
0x8028 MOV F D E
Time
F - Fetch, D - Decode, E - Execute

• Solution: Harvard architect., adv. processors have deeper

Thumb - ARM ARM Decode Reg. Reg.
pipelining,
Instruction Fetch
Decompression Register Select Read Shift + ALU Memory Access Write

• ARM9F E–T 5
C Hstage, ARM10
DEC–
OD WR I T E
6EN.stage,
MathivananE X E C U T E
ARM11 – 8Mstage
E MOR Y
 Operating Modes
• ARM7 has 7 modes, classified into privileged and non-privileged
o In non-privileged mode processor can’t change control bits of CPSR

• Each mode has different subset of registers. (refer to reg.

organization)

• Switching between the modes requires saving / retrieving of

register values.
• Banked registers accessible in their respective modes

N. Mathivanan
 Operating Modes Continued….
User Mode

r0

r1
Mode Function r2

Normal programs and applications. r3

User
Only non-privileged mode. r4

Enters when highest priority interrupt occurs. Fast r5

FIQ
data transfer/processing mode. r6

Enters when normal interrupt occurs. r7

IRQ
General-purpose interrupt handling. r8

Enters when CPU is reset or SVC is executed. r9

SVC Protected mode for OS, default on startup or r10

reset. r11
Enters when illegal memory accesses occurs. r12 IRQ
ABT Implements virtual memory and/or memory r13_sp r13_irq
protection
r14_lr r14_irq
SYS Privileged user mode for OS (runs OS tasks) r15_pc

Enters when unknown/illegal instruction executed.

UND
Software emulation of hardware coprocessors CPSR

SPSR_irq
N. Mathivanan
 Exceptions
• Generated by external events or internal sources
• Seven types of exceptions
o Reset: Occurs when ‘Reset’ pin is asserted – power-up/reset
o Undefined: Occurs when currently executing instruction could
not be recognized
o SWI: Occurs if program in user mode executes SWI instruction
to request OS services that are available in supervisor mode.
o Prefetch Abort: Occurs if instruction fetched from invalid
address. Exception is generated at execution stage.
o Data Abort: Occurs if data load/store attempt at illegal address
o IRQ: Occurs if IRQ pin goes low (only if CPSR IRQ mask bit is 0)
o FIQ: Occurs if FIQ pin goes low (only if CPSR FIQ mask bit is 0)
N. Mathivanan
 Exception Handling
• Exception causes diversion of execution to a particular mem location

• Exception Vector Table holds instructions at exception vector

locations to branch processor to actual exception handler routine.

• The addresses assigned for the 7 exceptions and one reserved

exception are from 0x0000 0000 to 0x0000 001C at 4 bytes interval.

• Response of the processor to exceptions: (automatically performed)

o Copies CPSR to SPSRexception

o Changes CPSR bits (enable ARM state, change mode bits, disable
interrupts)
o Saves return address i.e. (current PC–4) in LRexception
o Places vector address of exception mode in PC.

N. Mathivanan
• Execution branches to exception handler routine and executes
Exception handler has codes to return back to previous mode at
correct loc
Restores CPSR from SPSRexception

Restores PC from LRexception

Above two are performed using instruction like (MOVS PC,LR)
At the entry/exit registers are stored/retrieved using STMFD/LDRFD
Value in PC at the instant of exception is not same for all
exceptions:
Hence instruction to return back is different for different
exceptions

N. Mathivanan
 Response of Processor to Exceptions

What is the delay in execution introduced by 3-stage pipeline when an

RQ interrupt occurs (interrupt latency)?
Ans.: 7 cycles N. Mathivanan
 Exception Return
Except Processor Response to Enter Exception Handler Pri
Vector Instruction

SPSR_svc = unexpected
CPSR[4:0]= 10011B (SVC mode)
CPSR[5] = 0 (ARM state), CPSR[6] = 1 (Disable FIQ)
Reset 0x00000000 No return 1
CPSR[7] = 1 (Disable IRQ)
r14_svc = unexpected
PC = 0x00000000 (Exception vector)

SPSR_und = CPSR
CPSR[4:0]= 11011B (undefined mode) If registers are
not saved in
CPSR[5] = 0 (ARM state), CPSR[6] unchanged
stack
CPSR[7] = 1 (Disable IRQ)
Un r14_und = addr of next to undefined instruction MOVS pc,lr
0x00000004 6
defined PC = 0x00000004 (Exception vector)

If saved:
Registers are saved in stack at entry using:
LDMFD sp!,
STMFD sp!,{<reglist>,lr}
{<reglist>,pc}^
N. Mathivanan
 Exception
Except Processor Response to Enter Exception Handler Return Instruction Pri
Vector

SPSR_svc = CPSR
CPSR[4:0]= 10011B (SVC mode), If registers are not
CPSR[5] = 0 (ARM state) saved in stack
CPSR[6] unchanged, CPSR[7] = 1 (Disable IRQ)
r14_swi = addr of next instruction to SWI MOVS pc,lr
SWI 0x00000008 PC = 0x00000008 ;Exception vector 6

If saved:
Registers are saved in stack at entry using:
LDMFD sp!,
STMFD sp!,{<reglist>,lr}
{<reglist>,pc}^

SPSR_abt = CPSR
CPSR[4:0]= 10111B (Abort mode), If registers are not
CPSR[5] = 0 (ARM state) saved in stack
CPSR[6] unchanged, CPSR[7] = 1 (Disable IRQ)
Prefetch r14_abt = aborted instruction addr.+4 SUBS pc,lr,#4
0x0000000C PC = 0x0000000C ;Exception vector 5
Abort

Registers are saved in stack at entry using: If saved:

SUB lr,lr,#4 LDMFD sp!,
STMFD sp!,{<reglist>,lr} {<reglist>,pc}^
N. Mathivanan
Exception Exception Processor Response to Enter Return Pri
Vector Exception Handler Instruction

SPSR_abt = CPSR
CPSR[4:0]= 10111B (Abort mode), If registers are
not saved in
CPSR[5] = 0 (ARM state) , CPSR[6] unchanged
stack
CPSR[7] = 1 (Disable IRQ)
r14_abt = aborted instruction addr.+8 SUBS pc,lr,#8
Data Abort 0x00000010 2
PC = 0x00000010 (Exception vector)

Registers are saved in stack at entry using: If saved:

SUB lr,lr,#8 LDMFD sp!,
{<reglist>,pc}^
STMFD sp!,{<reglist>,lr}

Reserved 0x00000014 Reserved Reserved Reserved

N. Mathivanan
Except Exception Return
Processor Response to Enter Exception Handler Pri
ion Vector Instruction

SPSR_irq = CPSR
If registers are
CPSR[4:0]= 10010B (IRQ mode), CPSR[5] = 0 (ARM state)
not saved in stack
CPSR[6] = unchanged, CPSR[7] = 1 (Disable IRQ)
r14_irq = last executed instruction addr.+8 SUBS pc,lr,#4
IRQ 0x00000018 PC = 0x00000018 ;Exception vector 4

Registers are saved in stack at entry using: If saved:

SUB lr,lr,#4 LDMFD sp!,
STMFD sp!,{<reglist>,lr} {<reglist>,pc}^

SPSR_fiq = CPSR
If registers are
CPSR[4:0]= 10001B (FIQ mode), CPSR[5] = 0 (ARM state)
not saved in stack
CPSR[6] = 1 (Disable FIQ), CPSR[7] = 1 (Disable IRQ)
r14_fiq=last executed instruction addr.+8 SUBS pc,lr,#4
FIQ 0x0000001C PC = 0x0000001C ;Exception vector 3

Registers are saved in stack at entry using: If saved:

SUB lr,lr,#4 LDMFD sp!,
STMFD sp!,{<reglist>,lr} {<reglist>,pc}^
N. Mathivanan
 Bus Architecture
• Advanced Microcontroller Bus Architecture (AMBA)
o Bus system connects memory, controllers and peripherals in
ARM processor based microcontroller to ARM core
o AMBA bus protocol std., adopted as on-chip bus by many mC
o ARM core is bus master, peripherals are slaves
o 3 buses within AMBA spec: AHP, ASP, APB
 AHP (Advanced High-performance Bus):
Provides high band-width.
Supports multiple masters, slaves (e.g. of masters: DMA,
Test interface, DSP, and e.g. of slaves: external memory).
Includes bus arbiter, decoder
Used in complex and more sophisticated systems
N. Mathivanan
 ASB (Advanced System Bus):
AHB and ASB have many things in common
Both support bursting, pipelining, split transaction
ASB is used in simple cost effective designs

 APB (Advanced Peripheral Bus):

Simple, low speed, low power bus, for UART, ....
peripherals
Implemented with simple tri-stated data bus
AHB-APB bridge: buffers data & operations between the
two

N. Mathivanan
 Debug Architecture
• Uses boundary scan technology and JTAG to access core
• JTAG can be used in programming, debugging, testing
• ARM7-TDMI is JTAG enabled
(to next cell)
Boundary Serial-out
Scan Cells Mode

Din (Parallel-in) Scan Cell Dout (Parallel-out)

(from device pin) (input cell) (to core logic)
CORE
I/O Pads Shift/ Update
LOGIC Load Clock
Serial-in
(from previous cell)
(b)

TDI Instruction Register Boundary

Scan Path (to next cell)
Scan out
BYPASS Register MUX
Din 0
ID Register (Parall-in) MUX Dout
1 (Parallel-out)
0
Other Registers D Q D Q
1
TCK Clk Clk
Test Access Port Mode
TMS Controller = 0 for functional mode
____ Shift/ Capture Update = 1 for test mode
TRST Load Scan Cell Hold Cell
TDO Scan in Clock Update
(from previous cell)

(a) N. Mathivanan (c)

• Boundary scan cells – read/write pins without physically accessing
Capture: parallel load captures signals on input pin to input cell and
core output to output cell.
Update: parallel unload operation passes values in output cell to
output pin and input cells to core
Serial shift: scan out of scan cell passed to scan in of next cell
Normal mode: Din goes to Dout for normal operation, bypass scan cell

• Scan chains - Scan cells linked to form chain around ARM macrocells
TAP provides JTAG signals to control boundary scan operation
Data can be shifted around from TDI to TDO, collected and probed

• ARM7-TDMI debug – 3 Scan chains around core and EmbeddedICE

‘D’ and ‘I’ stand for Debug and In-Circuit Emulator
Debug system: host, protocol converter, debug target

N. Mathivanan
• Host: PC running ARM debugger, allows setting break points/watch
point, examining contents of registers from host.
• EmbeddedICE forces ARM processor to debug state in which
processor is isolated from rest of the system

• Debug Comm Channel tech. allows ARM core to communicate with

host while program is running and even without entering debug state

N. Mathivanan
 Interface Signals
• Clocks & Timing signals Clocks and
timing
MCLK
nWAIT
TCK
TMS
ECLK TDI
nIRQ
• Processor mode signals Interrupts nFIQ
nTRUST

ISYNC Borndary scan

nRESET
• Memory interface signals BUSEN
TDO
TAPSM[3:0]
HIGHZ IR[3:0]

• Bus control signals nHIGHZ

BIGEND
nTDOEN
TCK1
nENIN TCK2

• Interrupts Bus controls

nENOUT
nENOUT1
SCREG[3:0]
Boundary scan control signals
ABE nM[4:0] Processor mode
Processor state
• Memory management ALE
APE
TBIT
A[31:0]
DBE ARM7-TDMI
DOUT[31:0]
signals TBE
BUSDIS
ECAPCLK D[31:0]

• Coprocessor interface Power

VDD DIN[31:0]
VSS Memory Interface
nMREQ
signals DBGRQ
BREAKPT SEQ
DBGACK nRW
nEXEC MAS[1:0]
• Debug interface signals EXTERN1 BL[3:0]
EXTERN0 LOCK
Debug DBGEN nTRANS Memory Management
RANGEOUT0 ABORT Interface
RANGEOUT1 nOPC
DBGRQI nCP1 Coprocessor
COMMRX CPA Interface
COMMTX CPB
N. Mathivanan
 Review Questions
1. What is the size of address and data busses in ARM7 processor?
2. What is the size of memory space ARM7 processor can address?
3. List the features of ARM processors.
4. What does ‘TDMI-S’ in ARM7-TDMI-S refer to?
5. What are the special functions of r13, r14 and r15 registers?
6. What are special features of multiplier block in ARM7 processor?
7. What are CPSR and SPSR?
8. What are the functions of control bits of program status register?
9. What is the purpose and feature of barrel shifter?
10. Describe the internal architecture of ARM7 processor
11. List modes of operation of ARM7 processor.
12. What is the width of half-word size data?
N. Mathivanan
13. Show schematically how the following data are saved in
memory starting from memory address 0x0000 0000 in big
endian and little endian byte order.
Data: 0xEF, 0x1234, 0xAB, 0x6789ABCD.
14. Illustrate ARM7 processor 3-stage pipelining.
15. What is interrupt latency?
16. Illustrate braking and stalling of pipeline by branch and
Load/Store instructions with suitable examples.
17. List ARM modes and the events that cause the processor to
enter into the corresponding mode.
18. Which one of the ARM modes is non-privileged mode?
19. How are the privileged and non-privileged modes distinguished?
20. What are the seven types of exceptions? List the events that
generate the exceptions. N. Mathivanan
21. How does the ARM7 processor handle exceptions? Explain the
response of the processor to exceptions.
22. What is exception vector table? What does it hold?
23. Give examples of return instructions used in exception
routines.
24. Write down the ARM exceptions in the order of its priority.
25. What is the delay in execution introduced by 3-stage pipeline
when an IRQ interrupt occurs?
26. Discuss typical ARM Bus Architecture implemented in a ARM7
processor based microcontroller.
27. What are the AHB and APB buses and their characteristics?
28. What are technologies used in ARM debug architecture?

N. Mathivanan