PRAVIN ROHIDAS PATIL COLLEGE

OF DEGREE ENGG. & TECHNOLOGY

6. PENTIUM 4

CHAPTER 1 – THE INTEL MICROPROCESSORS 8086 ARCHITECTURE

CHAPTER 2 – INSTRUCTION SET AND PROGRAMMING
SUBJECT – MICROPROCESSOR (CSC405)
SEMESTER – FOURTH
BY– MRS PRACHI KALPANDE
EVOLUTION OF MICROPROCESSOR
 80186 BASIC FEATURES
 The 80186 contains 16 – bit data bus

 The internal register structure of 80186 is

virtually identical to the 8086

 About the only difference is that the

80186 contain additional reserved
interrupt vectors and some very powerful
built-in I/O features
 80186 BASIC FEATURES
Clock Generator:
The internal clock generator replaces the external

8284A clock generator used with the 8086

microprocessors. This reduces the component count
in a system

Programmable Interrupt Controller:

The PIC arbitrates all internal and external
interrupts and controls up to two external 8259A
PICs. When an external 8259 is attached, the
80186 microprocessors function as the master and
the 8259 functions as the slave
 80186 BASIC FEATURES
 Timers:
 The timer section contains three fully
programmable 16-bit timers
 The timers 0 and 1 generate wave-forms
for external use and driven by either the
master clock of the 80186 or by an
external clock

 The third timer, timer 2 is internal and

clocked by the master clock
 80186 BASIC FEATURES
Programmable DMA Unit:

Theprogrammable DMA unit contains two

DMA channels, or four DMA channels in
some models

Each channel can transfer data between

memory locations, between memory and
IO, or between IO devices
 80186 BASIC FEATURES
Programmable chip selection unit:

The chip selection is a built-in

programmable memory and I/O decoder

It has 6 output lines to select memory, 7

lines to select I/O
 80186 BASIC FEATURES

Power save/Power Down Feature:

The power save feature allows the system

clock to be divided by 4, 8, or 16 to reduce
power consumption

The power saving feature is started by

software and exited by a hardware event
such as an interrupt
 80186 BASIC FEATURES

Refresh Control Unit:

The refresh control unit generates the

refresh row address at the interval
programmed
 80286 BASIC FEATURES

 The 80286 microprocessor is an advanced

version of the 8086 microprocessor that is
designed for multi user and multitasking
environments

 The 80286 addresses 16 M Byte of physical

memory and 1G Bytes of virtual memory by
using its memory-management system

 The 80286 is basically an 8086 that is optimized

to execute instructions in fewer clocking periods
than the 8086
 80286 BASIC FEATURES
 Like the 80186, the 80286 doesn’t incorporate
internal peripherals; instead it contains a
memory- management unit (MMU)

 The 80286 operates in both the real and

protected modes

 In the real mode, the 80286 addresses a

1MByte memory address space and is virtually
identical to 8086

 In the protected mode, the 80286 addresses a

16MByte memory space
 80286 BASIC FEATURES

 The clock is provided by the 82284

clock generator, and the system
control signals are provided by the
82288 system bus controller

 The 80286 contains the same

instructions except for a handful of
additional instructions that control the
memory-management nit
 80386 BASIC FEATURES
 The 80386 microprocessor is an enhanced
version of the 80286 microprocessor and
includes a memory-management unit is
enhanced to provide memory paging

 The 80386 also includes 32-bit extended registers

and a 32-bit address and data bus

 The 80386 has a physical memory size of

4GBytes that can be addressed as a virtual
memory with up to 64TBytes
 80386 BASIC FEATURES
 The 80386 is operated in the pipelined mode,
it sends the address of the next instruction or
memory data to the memory system prior to
completing the execution of the current
instruction

 This allows the memory system to begin

fetching the next instruction or data before
the current is completed

 This increases access time, thus reducing the

speed of the memory
 80386 BASIC FEATURES
 The I/O structure of the 80386 is almost identical
to the 80286, except that I/O can be inhibited
when the 80386 is operated in the protected
mode through the I/O bit protection map

 The register set of the 80386 contains extended

versions of the registers introduced on the 80286
microprocessor. These extended registers include
EAX, EBX, ECX, EDX, EBP, ESP, EDI, ESI, EIP and
EFLAGS

 The instruction set of the 80386 is enhanced to

include instructions that address the 32-bit
extended register set
 80386 BASIC FEATURES
 Interrupts, in the 80386 microprocessor, have
been expanded to include additional predefined
interrupts in the interrupt vector table

 The 80386 memory manager is similar to the

80286, except the physical addresses generated
by the MMU are 32 bits wide instead of 24-bits

 The 80386 is also capable of paging

 The 80386 is operated in the real mode (i.e. 8086

mode) when it is reset
 80386 BASIC FEATURES
 The real mode allows the microprocessor
to address data in the first 1MByte of
memory

 In the protected mode, 80386 addresses

any location in its 4G bytes of physical
address space
 80486 BASIC FEATURES

 The 80486 microprocessor is an

improved version of the 80386
microprocessor that contains an 8K-byte
cache and an 80387 arithmetic co
processor; it executes many instructions
in one clocking period

 The 80486 microprocessor executes a

few new instructions that control the
internal cache memory
 80486 BASIC FEATURES
 A new feature found in the 80486 in the BIST
(built- in self-test) that tests the microprocessor,
coprocessor, and cache at reset time

 If the 80486 passes the test, EAX contains a zero

 Additional test registers are added to the 80486

to allow the cache memory to be tested

 These new test registers are TR3 (cache data),

TR4 (cache status), and TR5 (cache control)
COMPARISON OF SEGMENTATION IN 80386
WITH 8086
Segmentation in 80386 Segmentation in 8086

1) It has six types of memory segments, i.e. 1) It has four types of memory segments i.e.
CS,ES,FS,GS and SS CS,DS,ES and SS

2) Size of segments are variable from 1 byte 2) Size of segments are variable from 1 byte
to 4GB to 64KB

3) Segment selectors, descriptors, offset 3) Segment registers and offset registers

registers, GDT/LDT, page directory and are used to generate physical address from
page tables are used to generate physical logical address
address from logical address

4) Logical address is converted to linear 4) Logical address is converted to physical

and then to physical address address
COMPARISON OF SEGMENTATION IN 80386
WITH 8086
Segmentation in 80386 Segmentation in 8086

5) In this protection is provided to memory 5) In this protection is not provided to

segments by giving different privilege levels memory segments
from 0 to 3

6) Size of physical address is 32-bit 6) Size of physical address is 20 bit

7) 80386 can access 4GB of memory 7) 8086 can access 1MB of memory
 PENTIUM PROCESSOR BASIC
FEATURES
 The Pentium microprocessor is almost identical to
the earlier 80386 and 80486 microprocessors

 The main difference is that the Pentium has been

modified internally to contain a dual cache
(instruction and data) and a dual integer unit

 The Pentium also operates at a higher clock

speed of 66 MHz
 PENTIUM PROCESSOR BASIC
FEATURES
 The data bus on the Pentium is 64 – bits wide
and contains eight byte-wide memory banks
selected with bank enable signals

 Memory access time, without wait states, is only

about 18 ns in the 66 MHz Pentium

 The superscalar structure of the Pentium

contains three independent processing units: a
floating point processor and two integer
processing units
 PENTIUM PROCESSOR BASIC
FEATURES
 A new mode of operation called the System
Memory Management (SMM) mode has been
added to the Pentium. It is intended for high-
level system functions such as power
management and security

 The Built-in Self-test (BIST) allows the Pentium to

be tested when power is first applied to the
system

 Allows 4MByte memory pages instead of the

4KByte pages
PENTIUM PRO PROCESSOR BASIC
FEATURES
 The Pentium Pro is an enhanced version of the
Pentium microprocessor that contains not only the
level 1 caches found inside the Pentium, but the
level 2 cache of 256 K or 512K found on most main
boards

 The Pentium Pro operates using the same 66 MHz

bus speed as the Pentium and the 80486

 It uses an internal clock generator to multiply the

bus speed by various factors to obtain higher
internal execution speeds
 PENTIUM PROCESSOR BASIC
FEATURES
The onlysignificant software difference
between the Pentium Pro and earlier
microprocessors is the addition of FCMOV
and CMOV instructions

The only hardware difference between

the Pentium Pro and earlier
microprocessors is the addition of 2M
paging and four extra address lines that
allow access to a memory address space
PENTIUM II
 PENTIUM II

Extension to Pro architecture with some
differences
 Internal cache in PII has been moved out of the
chip
 PII is not available as a single chip
Rather is available on a small plug-in circuit


board, known as Cartridge, along with level

2 (L2) cache chip

Various versions are available
 Cerelon is a version without L2 cache
 Xeon is enhanced by having up to 2M L2 cache
PENTIUM II INTERNAL
ARCHITECTURE

Pentium II
Cartridge
Cache
512K/
Pentium II Internal Bus
1M/
2M
A TYPICAL PENTIUM II SYSTEM

Pentium II
Cartridge
AGP SDRAM
Chipset or
Slot
DRAM

PCI Bus

USB Bridge
Bus

ISA Bus
 PENTIUM II (CONT...)

L2 cache is no longer inside the µP IC
 But placed very close to µP IC

This changes make the µP less expensive
 PENTIUM II (CONT...)

Various versions of P II are available
 Standard P II

L2 cache operates at half the processor speed
 Celeron: does not contain L2 cache in the cartridge

Rather it is in the main board

Operates at processor speed
 Xeon: contain up to 2M (512K/1M/2M) L2 cache

Operates at processor speed
 PENTIUM II (CONT...)

Early P II requires
 5.0 V
 3.3 V and
 variable voltage power supply for operation

may vary from 3.5v to as low as 1.8v

Requires 8.4 to 14.2A depending on operating
frequency
 PENTIUM II (CONT...) MEMORY
SYSTEM

36 bit address

64 bit data

RAM used has an access time of 8 ns to 10 ns

Also include ECC

Though not used by P II system, parity checking is available

Transfers between PII and memory system are controlled by the
chipset

In fact, chipset controls PII, which is a departure from the
traditional use of processor
 PENTIUM II (CONT...)
MEMORY MAP OF A PII BASED SYSTEM

Conventional Memory 0 – 1M
 Application Area 0 – 640K
 System Area 640K – 1M

Main Memory 1M – 1G
 Optional ISA Memory 15M – 16M
 Remapped AGP Data

PCI Memory 1G – 4G
 AGP Aperture Texture and Instructions
 PCI Access to AGP Frame Buffer
 PCI Access to AGP Registers

For future expansion 4G – 64G
PENTIUM III
 PENTIUM III

Improved version of PII, but based on Pro
architecture, not on P II

Two version of P III available
 packaged in a slot 1 cartridge instead of IC chip like P
II with a non-blocking 512K cache running at half
speed of processor
 Packaged in 370-pins IC, known as Coppermine, with
256K advanced transfer cache within the IC and
running at processor speed

It has been observed that, increasing cache size
from 256K to 512K improves the performance by
only a few percent
 PENTIUM III (CONT...)

Chipset is different from P II

Coppermine increases the bus speed to either
100MHz or 133MHz

Bus speed cannot be increased arbitrarily due
to radiation problem
 PENTIUM III (CONT...)

Various versions of P III are also available like PII
 Standard P III
 Celeron PIII uses 66MHz bus speed
 Xeon PIII allows larger cache for server
applications
PENTIUM IV
BLOCK DIAGRAM OF PENTIUM 4
 PENTIUM IV

Based on Pro architecture, not on P II or P III

Released initially in Nov’00 with 1.3GHz speed
 Later available with speed more then 3GHz

Available in two IC packages using 0.18 micron
 423-pin PGA
 478-pin FC-PGA2

More recent versions use 0.13 or 0.09 micron
technology

It uses physically smaller transistors
 Making it much smaller and faster than P III

Uses 100MHz bus speed.
 PENTIUM IV (CONT...)
MEMORY INTERFACE

Typically uses Intel 850 chipset

850 provides a dual-pipe memory bus with
processor
 Each pipe interfaced to a 32-bit wide section of
memory
 Two pipes functions together to comprise the 64-bit
data bus
 PENTIUM 4

Still translate from 80x86 to micro-ops

P4 has better branch predictor, more FUs

Instruction Cache holds micro-operations vs. 80x86 instructions
 no decode stages of 80x86 on cache hit
 called “trace cache” (TC)

Faster memory bus: 400 MHz v. 133 MHz

Caches
 Pentium III: L1I 16KB, L1D 16KB, L2 256 KB
 Pentium 4: L1I 12K uops, L1D 8 KB, L2 256 KB
 Block size: PIII 32B v. P4 128B; 128 v. 256 bits/clock

Clock rates:
 Pentium III 1 GHz v. Pentium IV 1.5 GHz
 PENTIUM 4 FEATURES

Multimedia instructions 128 bits wide vs. 64 bits wide => 144
new instructions
 When used by programs?
 Faster Floating Point: execute 2 64-bit FP Per clock
 Memory FU: 1 128-bit load, 1 128-store /clock to MMX regs

Using RAMBUS DRAM
 Bandwidth faster, latency same as SDRAM
 Cost 2X-3X vs. SDRAM

ALUs operate at 2X clock rate for many ops

Pipeline doesn’t stall at this clock rate: uops replay

Rename registers: 40 vs. 128; Window: 40 v. 126

BTB: 512 vs. 4096 entries (Intel: 1/3 improvement)
 BASIC PENTIUM 4 PIPELINE

TC Nxt IP TC Fetch Drive Alloc Rename Queue Schd

Schd Schd Disp Disp Reg Reg Ex FlagsBr ChkDrive
1-2 trace cache next instruction 10-12 write uops into scheduler
pointer 13-14 move up to 6 uops to FU
3-4 fetch uops from Trace 15-16 read registers
Cache
17 FU execution
5 drive upos to alloc
18 computer flags e.g. for branch
6 alloc resources (ROB, reg, instructions
…)
19 check branch output with
7-8 rename logic reg to 128 branch prediction
physical reg 20 drive branch check result to
9 put renamed uops into queue frontend
 BLOCK DIAGRAM OF PENTIUM 4
MICROARCHITECTURE


BTB = Branch Target Buffer (branch predictor)

I-TLB = Instruction TLB, Trace Cache = Instruction cache

RF = Register File; AGU = Address Generation Unit

"Double pumped ALU" means ALU clock rate 2X => 2X ALU F.U.s
From “Pentium 4 (Partially) Previewed,” Microprocessor Report, 8/28/00