Logic and Computer Design Fundamentals

Chapter 7 – Registers and Register

Transfer

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.
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 Propagation Delay: capacitances
introduce delay
 All physical devices have delays due to the charging
and discharging of (parasitic capacitors) and
interconnection resistance.

Crossing lines level

tpd

t
Resistive tube
Propagation delay

flow

2
 Where to these capacitors come
from?
Most are parasitic caps
Cross section of Altera Stratix EP1S25 (TSMC proces
Crossing lines passivation

M9

M8

9 level of interconnections
rossing interconnections M7

M6

M5

M4

M3

M2

(Source: IBM) M1

(Source: TSMC)
2um
3
Review: 6-3 Flip-Flop Timing
Parameters and metastability
 Edge triggered flip-flop
In Out
D Q

C C Q
C

In (D) tS th

set-up time hold time

 If one violates the set-up time and hold
time, the flip-flop can go in a metastable
state.
4
Metastable behavior
 Example of metastable behavior:

metastable

Eventually, the flip-

flop will settle

(Oscilloscope trace)
 After a while the flip-flop will go into a stable state
(randomly).
 If this happens before the next clock edge, the actual
circuits will see a defined input.
 The longer the clock period is the less chance of
synchronization failure.
 Or use two synchronization flip-flops in series

5
Debouncing

PRACTICAL
CONSIDERATIONS

6
Practical considerations

 In many cases the input signals come from

push buttons and sensors:
• Switches exhibit bouncing
• Are not synchronous
• Give multiple input (sampled many times)
 This can give catastrophic failures of
timing problems
 Solutions:
• Debounce the switch
• Synchronizer
• One-pulse circuit (and synchronizer)

7
 Bouncing of switches

 What is bouncing?
 When closing a switch, the switch contact
bounces back and forth, giving multiple
5V
pulses
chip
Push
button
A B
switch

Causes spurious glitches on input B Measured signal

8
Debouncing circuit

 The two resistors will keep S=R=0:

• Inputs are never floating
• Output does not bounce Push switch
R
5V
R
1
Q

S contact to 5V
Bouncing
S 2 Q

Q No bouncing

SR latch
S=R=0
Is set No change

9
Likely violation of set up times

ISSUES WITH
ASYNCHRONOUS INPUTS

10
 Asynchronous inputs

 Asynchronous inputs (e.g. from sensors)

can cause timing problems if set up time is
violated:t setup time
S

CLK

Signal from
sensor

This setup time violation can give problems,metastable

such as metastability and erroneous
operation:
stable stable

 Use a synchronizer

11
 Metastability and Synchronization
 A flip-flop can get into a metastable state:
• When the set-up or hold times are violated
• This can happen for asynchronous inputs (e.g. push
button; sensor input, etc) Input

CLK
D0i
D Q0
Q
Sensor Q0
asynchronou
s input Q1
D1
D Q1 Both flip flops behave differently!
Q

CLK

kick Q0 Q0

kick Q1

12
Metastability (continued)
 Asynchronous inputs:
• Use a synchronizing flip-flop

Synchronizer
Asynchron D0 D
ous input Q Q0
Di D
Q
Ai

D1i D
Q Q1

• Now, only the synchronizer may get into the metastable

state; however, there is a good chance that by the end of
the clock period it went into one of the stable states.

13
 Synchronizer

Sensor,asyncDi Ai
D
Q
Synchronized output
CLK

CLK

Signal from
sensor
Synchronized output

Note: by having the sensor input enter through a

single D flip-flop
the problem of timing circuits is reduced greatly
(there is still a small chance that the D FF will be
unstable). By using two D flip-flops in series one 14
Chapter 7
Registers and Register Transfers

(Source: reference.findtarget.com)

15
7-1 Registers

 Register – a collection of flip-flops,

together with some combinational
logic, that performs data processing
tasks (e.g. storing, moving data, etc).
 In theory, a register is sequential
logic which can be defined by a state
table.
 More often think of a register as
storing a vector of binary values.

16
 Simple Storage Register
• A D flip-flop register loads information on every

Outputs
clock cycle!
• To “store” or “load” information should be
controlled by a signal.
inputs

Active low Clear (asynch)

17
 Register with Parallel Load: Clock
Gating
 Use a signal to block the clock to the register
 Load is a frequent name for the signal that
controls register storage and loading
• Load = 1: Load the values on the data inputs
• Load = 0: Store the values in the register

Clock gating:
1

Gated clock: To C input of Flip-flops

Clock
Timing:
Load

Gated Clock to FF
Extra edge!

18
Registers with Load-Controlled
Feedback
 A more reliable way to selectively load a register:
• Run the clock continuously, and
• Selectively use a load control to change the register
contents.
2-to-1 Multiplexers
 Example: 2-bit register
with Load Control:
 For Load = 0,
loads register contents A1
(hold current values) D Q Y1
Load
 For Load = 1, In1
C
loads input values
(load new values)
A0
 Hardware more complex Y0
D Q
than clock gating, but C
free of timing problems
In0
Clock

19
 Registers with Load Control:
Example

K1=1: R1 stores the

result of
addition/subtraction

20
7-2 Register Transfers
 The data is stored in registers, which compose
the datapath.

(Source: reference.findtarget.com)

 In many cases one wants to perform a variety of

arithmetic and logical operations on a set of data
bits (e.g. a 16-bit word):
• Additions, subtraction, shifting, loading, etc.

21
Register Transfers Operations
 The type of operations on the data will be
determined by a controller, often called a control
unit.

(Source: reference.findtarget.com)

 This division between the datapath and control

unit makes the design of complex systems easier.
 Strategy: divide and conquer!
 Registers play a key role in complex digital
systems!
22
 Datapath and Control Unit

Control signals

Status signals
Control Unit Datapath

 Determines which operation and  Stores data in registers

sequence of operation based on  Performs operations on
data, specified by Cntr unit
status signals  Provide status signals
 Control signals: activate various  Is defined by registers
operations in the datapath and its operations:
 Is a large finite state machine Register Transfer
Operations (RTL)
 An elementary operation:
microoperation
23
 7-3 Register Transfer Operations
 Register Transfer Operations – The movement
and processing of data stored in registers
 Three basic components:
• set of registers
• operations
• control of operations
 Elementary Operations -- load, count, shift, add,
bitwise "OR", etc.
• Elementary operations called microoperations
Register Notation: MSB 7 …1 0 LSB
Ex. 8-bit register R:
R

15 8 7 0 15 0
16-bit registers: PC(H) PC(L) R2
24
 Conditional Transfer
 If (K1 =1) then (R2  R1) is
shortened to
K1
Load
n
K1: (R2  R1) R1 R2
where K1 is a control variable
specifying a conditional
execution
of the microoperation. Clock

Clock

K1
Clock Transfer occurs
here
K1 No Transfers Occur Here
Transfer occurs
here
No Transfers Occur Here
25
7-5 Microoperations
 Logical Groupings:
• Transfer - move data from one set of registers to
another
• Arithmetic - perform arithmetic on data in registers
• Logic - manipulate data or use bitwise logical
operations
• Shift - shift data in registers
Logical operations (bitwise)
Arithmetic operations  Logical OR
+ Addition  Logical AND
– Subtraction  Logical Exclusive OR
* Multiplication  Not
/ Division

26
Example Microoperations
 Add the content of R1 to the content of R2
and place the result in R1.
R1 R1 + R2
 Multiply the content of R1 by the content
of R6 and place the result in PC.
PC  R1 * R6
 Exclusive OR the content of R1 with the
content of R2 and place the result in R1.
R1  R1  R2

27
Example Microoperations (Continued)

 On condition K1 OR K2, the content of R1

is Logic bitwise ORed with the content of
R3 and the result placed in R1:
• (K1 + K2): R1  R1  R3

 NOTE: "+" (as in K1 + K2) and means

“OR.” In R1  R1 + R3, + means “plus.”

28
Arithmetic Microoperations

Symbolic Designation Description

R0 ¬ R1 + R2 Addition
R0 ¬ R1 Ones Complement
R0 ¬ R1 + 1 Two's Complement
R0 ¬ R2 + R1 + 1 R2 minus R1 (2's Comp)
R1 ¬ R1 + 1 Increment (count up)
R1 ¬ R1 – 1 Decrement (count down)
 Note that any register may be specified for
source 1, source 2, or destination.
 These simple microoperations operate on
the whole word

29
 Implementation of an Arithmetic
Micro operation
Conditional microoperation:

X K1 : R1  R1 + R2
X K1 : R1  R1 + R2 + 1
Condition

30
Logical Microoperations

Symbolic Description
Designation
R0 ¬ R1 Bitwise NOT
R0 ¬ R1 Ú R2 Bitwise OR (sets bits)
R0 ¬ R1 Ù R2 Bitwise AND (clears bits)
R0 ¬ R1 Å R2 Bitwise EXOR (complements bits)

31
Logical Microoperations (continued)

 Let R1 = 10101010,
and R2 = 11110000
 Then after the operation, R0 becomes:

R0 Operation
01010101 R0  R1
11111010 R0  R1  R2 (sets bits)
10100000 R0  R1  R2 (clears bits)
01011010 R0  R1  R2 (complements bits)

32
Shift Microoperations

Symbolic Description
 Let R2 = 11001001 Designation
 Then after the R1 ¬ sl R2 Shift Left
operation, R1 R1 ¬ sr R2 Shift Right
becomes: R1 Operation
10010010 R1 ¬ sl R2
01100100 R1 ¬ sr R2
 Note: These shifts "zero fill". Sometimes a
separate flip-flop is used to provide the data
shifted in, or to “catch” the data shifted out.
 Other shifts are possible (rotates, arithmetic).

33
7-6: Microoperation on a Single
Register
 Microoperation on a Single Register
• MUX-based transfers
• Shift registers (needed for Lab)
• Ripple Counter
• Synchronous binary counter
• Other counters

34
7-6 Microoperations on a Single
Register
 The focus is on the implementation of
microperations with a SINGLE register as
the Destination of the results
 In addition to the register there is some
combinational logic needed. This is
considered part of the register and is
called DEDICATED logic (in contrast to
SHARED logic for multiple destination
registers).
 Multiplexer-based transfer: makes use of
multiplexers to allow multiple operations
on a single destination register (See next)

35
Multiplexer-Based Transfers
 Multiplexers connected to register inputs produce
flexible transfer structures
 Consider the following
Load
circuit K 2
R2 K1

n S Load
0 n
n MUX R0
1
Load

R1
Combinational circuit

 What are the corresponding Register Transfer

operations of the following implementation?

36
Register Transfer Operations
implemented by the following circuit
• K1.K2: R0  R1
• K1.K2: R0  R2

Load
K2
R2 K1

n S Load
0 n
n MUX R0
1
Load

R1

37
Exercise
 Consider the following circuit (Note: Clocks are omitted for
clarity)

Load
K2
R2
K1
n S Load
0
n
n MUX R0
Load 1

R1

 What are the corresponding Register Transfer operations?

38
Shift Registers
 Shift Registers move data laterally within the register
toward its MSB or LSB position
 In the simplest case, the shift register is simply a set of
D flip-flops connected in a row like this:
In A B C Out
DQ DQ DQ DQ

CP

 Data input, In, is called a serial input or the shift right input.
 Data output, Out, is often called the serial output.
 The vector (A, B, C, Out) is called the parallel output.

39
 Shift Registers (continued)
 The behavior of the
In A B C Out
serial shift register DQ DQ DQ DQ
is given in the listing
on the lower right
 T0 is the register
Clock CP
state just before
the first clock Clock In A B C Out
pulse occurs T0 0 ? ? ? ?
 T1 is after the T1 1 0 ? ? ?
first pulse and T2 1 1 0 ? ?
before the second. T3 0 1 1 0 ?
 Initially unknown
T4 1
states are denoted by “?” T5 1
 Complete the last three T6 1
rows of the table

40
Shift Registers (continued)

In A B C Out
DQ DQ DQ DQ

Clock CP

CP In A B C Out
T0 0 ? ? ? ?
T1 1 0 ? ? ?
T2 1 1 0 ? ?
T3 0 1 1 0 ?
T4 1 0 1 1 0
T5 1 1 0 1 1
T6 1 1 1 0 1

41
 Parallel Load Shift Registers
 By adding a mux MUX
DA DB
between each shift register
A B
stage, data can be
shifted or loaded IN D
Q
D
Q
 If SHIFT is low,
A and B are SHIFT
replaced by the data on DA
CP
and DB lines, else data
shifts right on each clock.
 By adding more bits, we
can make n-bit parallel load
shift registers. SHIFT: Q  sr Q
 Register Transfer SHIFT’: Q  D
Operation:

42
Parallel Load Shift Registers with Load
Serial input

D0 2
1
D Q0
0 Q
S1 S0
Shift C
Load

2
D1 1 Q1
D
0 Q
Control S1 S0
Shift C
Load
Use a multiplexer with 3 inputs:

2
D2
Serial input
1
D Q2
2 0 Q
S1 S0
D0 1
=
0 Shift C
S1 S0 Load
Shift
Load

43
 Timing

Clock

Load
(Shift = 0)
Di

Qi

Output changes here

Register Transfer Operation:

Shift: Q  sl Q
Shift.Load: Q  D

44
Bidirectional shift register

45
Counters
 Counters are sequential circuits which "count"
through a specific state sequence. They can
count up, count down, or count through other
fixed sequences. Two distinct types are in
common usage:
 Ripple Counters
• Clock is connected to the flip-flop clock input on the
LSB bit flip-flop
• For all other bits, a flip-flop output is connected to the
clock input, thus circuit is not truly synchronous
• Output change is delayed more for each bit toward the
MSB.
• Resurgent because of low power consumption
 Synchronous Counters
• Clock is directly connected to the flip-flop clock inputs
• Logic is used to implement the desired state sequencing
46
 Ripple Counter
 How does it work? A
D
• When there is a positive
Clock CR
edge on the clock input
of A, A complements
• The clock input for flip- D B
flop B is the complemented
output of flip-flop A CR
Reset
• When flip A changes
from 1 to 0, there is a
positive edge on the CP
clock input of B
causing B to A
complement
B
0 1 2 3 0 1
47
Ripple Counter (continued)
 The arrows show the
cause-effect relation-
CP
ship from the prior
slide =>
A
 The corresponding
sequence of states => B
0 1 2 3 0 1
(B,A) = (0,0),(0,1), (1,0), (1,1), (0,0), (0,1), …

Each additional bit, C, D, …behaves like bit B,

changing half as frequently as the bit before it.
 For 3 bits: (C,B,A) = (0,0,0), (0,0,1), (0,1,0), (0,1,1),
(1,0,0), (1,0,1), (1,1,0), (1,1,1), (0,0,0), …

48
Delays in a Ripple Counter
 Starting with C = B = A = 1, the next clock
increments the count to (C,B,A) = 0; thus
from (111) to (000)
 In fine timing detail: The clock to output
delay tPHL causes an increasing
delay from clock edge for tPHL
each stage transition. CP
• Thus, the count “ripples” tPHL
from least to most A 1
0 0 0
significant bit.
tpHL
• For n bits, total worst case
B 1 1 0 0
delay is n tPHL.
C 1 1 1 0

49
Ripple Counter (continued)

 These circuits are called ripple counters

because the changes “ripple” through the
chain of flip-flops, i. e., each transition
occurs after a clock-to-output delay from
the stage before.
 Disadvantages:
• Slow operation due to the delays
• Intermediate results with can give rise to
unreliable operation in digital circuits
 Advantages:
• Simple hardware
• Low power consumption
50
Synchronous Counters
 To eliminate the "ripple" effects, use a common
clock for each flip-flop and a combinational circuit
to generate the next state.
 For an up-counter,
use an incrementer =>
Comb. Logic
Incre-
menteS3 D3 Q3
A3
r
A2 S2 D2 Q2
A1 S1 D1 Q1
A0 S0 D0 Q0

Clock

51
 Synchronous counter

Clock

Q0 1 1 1

Q1 1 1

Q2

Q0: changes at every clock

When EN=1: XOR inverts and Q0=D’
EN D Q0
Q

C
Q0 D Q1
Q
EN
Q1: changes when Q0 = 1:
C

Q1
D Q2
Q
Q2: changes when Q0 and Q1 = 1
C

52
 Synchronous counter – parallel
gating
Incrementer
•Replace AND carry
chain with ANDs =>
in parallel
•Advantages
• Reduces path delays
• Called parallel gating
• Like carry lookahead

Symbol:

Carry Out CO
53
Synchronous Counter with an
Arbitrary Sequence
 Start with the state
diagram or the state 000
table
 Decide which flip- 110 001
flops to use
 Find the
101 010
combinational logic
(inputs to the flip- 100
flops)
 Draw or build the
circuit
54
 Design Exercise: Arbitrary
Sequence

000

110 001

101 010

100

55
 Arbitrary Count sequence: next state
equation
 3 Flip-flops required
 Find the next state equations: DC, DB, DA.

DA B

0 0 x 1
Be careful with A 1 1 x 0
Table sequence
C
DB DC B
B

DA = A’B+AB’ 0 1 x 0 1 0 x 0
= AB A 1 0 x 0
A 0 1 x 0
DB = C DC = B’C’
C
C
56
 Counter schematic

DA = A’B+AB’
= AB
DB = C

DC = B’C’

What about unused states?

Complete the state diagram

57