Logic and Computer Design Fundamentals

Chapter 9 – Computer
Design Basics
Part 1 – Datapaths

Charles Kime & Thomas Kaminski

© 2008 Pearson Education, Inc.
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Overview
 Part 1 – Datapaths
• Introduction
• Datapath Example
• Arithmetic Logic Unit (ALU)
• Shifter
• Datapath Representation and Control Word
 Part 2 – A Simple Computer
 Part 3 – Multiple Cycle Hardwired Control

Chapter 9 Part 1 2
Introduction

 Computer Specification
• Instruction Set Architecture (ISA) - the
specification of a computer's appearance to a
programmer at its lowest level
• Computer Architecture - a high-level
description of the hardware implementing
the computer derived from the ISA
• The architecture usually includes additional
specifications such as speed, cost, and
reliability.

Chapter 9 Part 1 3
Introduction (continued)

 Simple computer architecture

decomposed into:
• Datapath for performing operations
• Control unit for controlling datapath
operations
 A datapath is specified by:
• A set of registers
• The microoperations performed on the data
stored in the registers
• A control interface
Chapter 9 Part 1 4
Datapaths
 Guiding principles for basic datapaths:
• The set of registers
 Collection of individual registers
 A set of registers with common access resources called a
register file
 A combination of the above
• Microoperation implementation
 One or more shared resources for implementing
microoperations
 Buses - shared transfer paths
 Arithmetic-Logic Unit (ALU) - shared resource for
implementing arithmetic and logic microoperations
 Shifter - shared resource for implementing shift
microoperations

Chapter 9 Part 1 5
Datapath Example
L oad enable A select B select

 Four parallel-load Write

D data n
A address B address

registers L oad
R0 2 2

 Two mux-based n n

L oad
register selectors R1
0
n
 Register destination
1
MUX
2
n
0 3

decoder L oad
R2
1
2
MUX

 Mux B for external n n

3

constant input L oad R3

n n
0 1 2 3 n
 Buses A and B with external Decoder
D address A data
Register file
B data
2 Constant in n n
address and data outputs Destination select n 1 0
MB select
 ALU and Shifter with BusA
MUX B

Bus B
n
n
A ddress
out
Data

Mux F for output select

A B n out
G select H select
4 A B 2 B
S
 Mux D for external data input
S2:0 || Cin
V A rithmetic/logic 0 IR Shifter IL 0
C unit (A L U)
G H
 Logic for generating status bits N
Z Zero Detect
n n

0 1
V, C, N, Z MF select MUX F
F
Function unit

Data in
n n

MD select 0 1
MUX D
n Bus D
Chapter 9 Part 1 6
 Datapath Example: Performing a
Microoperation
L oad enable A select B select

 Microoperation: R0 ← R1 + R2 Write
D data n
A address B address

 Apply 01 to A select to place L oad

R0 2 2
contents of R1 onto Bus A n n

 Apply 10 to B select to place L oad

R1

contents of R2 onto B data and n

0
1
MUX
apply 0 to MB select to place n
0
2
3

B data on Bus B L oad

R2
1
2
MUX

 Apply 0010 to G select to perform n n

3

addition G = Bus A + Bus B L oad R3

 Apply 0 to MF select and 0 to MD

n n
0 1 2 3 n
Register file
Decoder
select to place the value of G onto 2
D address
Constant in n
A data
n
B data

BUS D Destination select

MB select
n 1 0

 Apply 00 to Destination select to BusA

MUX B

Bus B
n
n
A ddress
out
Data
enable the Load input to R0 G select
A

A
B

B
H select
n
B
out

4 2
 Apply 1 to Load Enable to force the V
S2:0 || Cin
A rithmetic/logic 0
S
IR Shifter IL 0
unit (A L U)
Load input to R0 to 1 so that R0 is C
N
G
n
H
n
loaded on the clock pulse (not shown) Z Zero Detect
MF select
0 1
Function unit
MUX F
 The overall microoperation requires F
n n Data in

1 clock cycle n
MD select
Bus D
0 1
MUX D
Chapter 9 Part 1 7
 Datapath Example: Key Control Actions
for Microoperation Alternatives
 Perform a shift microoperation –
L oad enable A select B select
Write A address B address
D data n

apply 1 to MF select L oad

R0 2 2
 Use a constant in a micro- n n

operation using Bus B – apply 1 L oad

R1
0

to MB select n 1
2
MUX
n
 Provide an address and data for a L oad
0
1
MUX
3

R2 2
memory or output write n n
3

microoperation – apply 0 to Load L oad R3

n n
enable to prevent register loading 0 1 2 3
Decoder
n
Register file

 Provide an address and obtain D address A data B data

2 Constant in n n

Destination select n 1 0
data for a memory or output read MB select
BusA
MUX B
n A ddress
out
microoperation – apply 1 to MD A B
Bus B n
n
Data
out

select
G select H select
4 A B 2 B
S2:0 || Cin S
V A rithmetic/logic 0 IR Shifter IL 0
 For some of the above, other C unit (A L U)
G H
N n
n
control signals become don't Z Zero Detect
MF select
0 1
Function unit
MUX F
cares F
n n Data in

MD select 0 1
MUX D
n Bus D
Chapter 9 Part 1 8
Arithmetic Logic Unit (ALU)

 In this and the next section, we deal with detailed design

of typical ALUs and shifters
 Decompose the ALU into:
• An arithmetic circuit
• A logic circuit
• A selector to pick between the two circuits
 Arithmetic circuit design
• Decompose the arithmetic circuit into:
 An n-bit parallel adder
 A block of logic that selects four choices for the B input to the
adder
 See next slide for diagram

Chapter 9 Part 1 9
Arithmetic Circuit Design (continued)
 There are only four functions of B to select as Y in G = A + Y:
Cin = 0 Cin = 1
• 0 G=A G=A+1
• B G=A+B G=A+B+1
• B G=A+B G=A+B+1
• 1 G=A–1 G=A
 What functions are implemented with carry-in to the adder = 0?
=1? C in

n
A X

n n-bit n
B parallel G X Y Cin
add
B input n
Y
S0 logic

S1

Cout
Chapter 9 Part 1 10
 Arithmetic Circuit Design (continued)

 Adding selection codes to the functions of B:

TABLE 9-1
FunctionTable for Arithmetic Circuit +
Select Input G = (A +
1Y+
1Cin )

S1 S0 Y Cin =0 Cin =1

0 0 all 0s G A (transfer) G A + 1 (increment)

0 1 B G A B (add) G A + B +1
1 0 B G A B G A B 1 (subtract)
1 1 all 1s G A 1 (decrement) (transfer)
 The useful arithmetic functions are labeled in the table
 Note that all four functions of B produce at least one
useful function

Chapter 9 Part 1 11
 Logic Circuit

 The text gives a circuit implemented using a multiplexer

plus gates implementing: AND, OR, XOR and NOT
 Here we custom design a circuit for bit Gi by beginning
with a truth table organized as a K-map and assigning
(S1, S0) codes to AND, OR, etc.
 Gi = S0 Ai Bi + S1 Ai Bi S1S0 AND OR XOR NOT
+ S0 Ai Bi + S1 S0 Ai A B 00 01 11 10
i i
 Gate input count for
00 0 0 0 1
MUX solution > 29
 Gate input count for 01 0 1 1 1
above circuit < 20 11 1 1 0 0
 Custom design better 10 0 1 1 0
Chapter 9 Part 1 12
 Arithmetic Logic Unit (ALU)
 The custom circuit has interchanged the (S1,S0) codes for XOR and NOT
compared to the MUX circuit. To preserve compatibility with the text,
we use the MUX solution.
 Next, use the arithmetic circuit, the logic circuit, and a 2-way
multiplexer to form the ALU. See the next slide for the bit slice diagram.
 The input connections to the arithmetic circuit and logic circuit have
been been assigned to prepare for seamless addition of the shifter,
keeping the selection codes for the combined ALU and the shifter at 4
bits:
• Carry-in Ci and Carry-out Ci+1 go between bits
• Ai and Bi are connected to both units
• A new signal S2 performs the arithmetic/logic selection
• The select signal entering the LSB of the arithmetic circuit, C in, is
connected to the least significant selection input for the logic circuit,
S0 .
Chapter 9 Part 1 13
 Arithmetic Logic Unit (ALU) (continued)
C0 5

Ci Ci Ci 1 1

Ai Ai
One stage of
Bi Bi arithmetic
circuit 2-to-1
S0 S0
0 MUX
S1 S1
Gi
1
Ai S
B i One stage of
Cin S logic circuit
0

S1
S
 The next most 2
significant select signals, S0 for the arithmetic circuit and
S1 for the logic circuit, are wired together, completing the two select
signals for the logic circuit.
 The remaining S1 completes the three select signals for the arithmetic
circuit.
Chapter 9 Part 1 14
Combinational Shifter Parameters
 Direction: Left, Right
 Number of positions with examples:
• Single bit:
 1 position
 0 and 1 positions
• Multiple bit:
 1 to n – 1 positions
 0 to n – 1 positions
 Filling of vacant positions
• Many options depending on instruction set
• Here, will provide input lines or zero fill

Chapter 9 Part 1 15
4-Bit Basic Left/Right Shifter
B3 B2 B1 B0
Serial
output L

Serial
output R
IR IL
0 1 2 M 0 1 2 M 0 1 2M 0 1 2M
S U S U S U S U
X X X X

2
S
H3
 Serial Inputs: H2 H H
 Shift1
Functions:
0

• IR for right shift (S1, S0) = 00 Pass B unchanged

• IL for left shift 01 Right shift
 Serial Outputs 10 Left shift
• R for right shift (Same as MSB input) 11 Unused
• L for left shift (Same as LSB input)

Chapter 9 Part 1 16
 Barrel Shifter
D3 D2 D1 D0

S0
S1
3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0 3 2 1 0 S1 S0
M M M M
U U U U
X X X X

Y3 Y2 Y1
 A rotate is a shift in which the bits shifted out are insertedY0into the
positions vacated
 The circuit rotates its contents left from 0 to 3 positions depending on S:
S = 00 position unchanged S = 10 rotate left by 2 positions
S = 01 rotate left by 1 positions S = 11 rotate left by 3 positions
 See Table 10-3 in text for details

Chapter 9 Part 1 17
Barrel Shifter (continued)

 Large barrel shifters can be constructed

by using:
• Layers of multiplexers - Example 64-bit:
 Layer 1 shifts by 0, 16, 32, 48
 Layer 2 shifts by 0, 4, 8, 12
 Layer 3 shifts by 0, 1, 2, 3
 See example in section 12-2 of the text
• 2 - dimensional array circuits designed at the
electronic level

Chapter 9 Part 1 18
 Datapath Representation
 Have looked at detailed design n

of Write
D data
m
ALU and shifter in the datapath D address
2mx n
in slide 8 Register file
m
 Here we move up one level in the A address B address
m

A data B data
Constant in
hierarchy from that datapath n
n n

 The registers, and the MB select

1 0
MUX B
multiplexer, decoder, and enable Bus A n
Address out
hardware for accessing them Bus B n
Data out
become a register file 4 A B
FS
 The ALU, shifter, Mux F and V
Function
status hardware become a N
C
unit

function unit Z
F
 The remaining muxes and buses n n
Data in
which handle data transfers are 0 1
MD select MUX D
at the new level of the hierarchy Chapter 9 Part 1 19
 Datapath Representation (continued)
 In the register file: n
• Multiplexer select inputs become D data
Write
A address and B address m
D address
• Decoder input becomes D 2mx n
Register file
address m m
A address B address
• Multiplexer outputs become A
A data B data
data and B data Constant in
n n
• Input data to the registers n
1 0
becomes D data MB select
MUX B
• Load enable becomes write Bus A n
Address out
Bus B n
 The register file now appears like Data out

a memory based on clocked flip- FS

4 A B

flops (the clock is not shown) V

Function
C
 The function unit labeling is quite N
unit

straightforward except for FS Z

F
n
n Data in

MD select 0 1
MUX D
Chapter 9 Part 1 20
Definition of Function
GSelect,HSelect,
andMF Unit Select (FS) Codes
in T ofFSCodes

MF G H
FS(3:0) Select Select(3:0) Select(3:0) Microoperation

0000 0 0000 XX F ¬ A Boolean

0001 0 0001 XX F ¬A +1
0010 0 0010 XX F ¬A + B Equations:
0011 0 0011 XX F ¬A + B +1
MFS = F3 F2
0100 0 0100 XX F ¬A + B
0101 0 0101 XX F ¬ A+ B + 1 GSi = Fi
0110 0 0110 XX F ¬A- 1
0111 0 0111 XX F ¬A HSi = Fi
1000 0 1X00 XX F ¬A Ù B
1001 0 1X01 XX F ¬A Ú B
1010 0 1X10 XX F ¬A ÅB
1011 0 1X11 XX F ¬A
1100 1 XXXX 00 F ¬B
1101 1 XXXX 01 F ¬ sr B
1110 1 XXXX 10 F ¬sl B

Chapter 9 Part 1 21
The Control Word

 The datapath has many control inputs

 The signals driving these inputs can be defined
and organized into a control word
 To execute a microinstruction, we apply control
word values for a clock cycle. For most
microoperations, the positive edge of the clock
cycle is needed to perform the register load
 The datapath control word format and the field
definitions are shown on the next slide

Chapter 9 Part 1 22
The Control Word Fields

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

DA AA BA M FS M R
B D W

Control word
 Fields
• DA – D Address
• AA – A Address
• BA – B Address
• MB – Mux B
• FS – Function Select
• MD – Mux D
• RW – Register Write
 The connections to datapath are shown in the next slide

Chapter 9 Part 1 23
Control Word Block Diagram
n

RW 0 Write D data

15
DA 14 D address
13 8x n
Register file
12 9
AA 11 A address B address 8 BA
10 7
A data B data
n n

n
Constant in

1 0
MB 6 MUX B
Bus A n
Address out
Bus B n
Data out

A B

V 5
C Function 4 FS
N unit 3
Z 2

n
n Data in

0 1
MD 1 MUX D
Bus D
Chapter 9 Part 1 24
 Control Word Encoding
Encoding of Control
W

DA, AA, BA MB FS MD RW

Function Code Function Code Function Code Function Code Function Code

R0 000 Register 0 F ¬A 0000 Function 0 No write 0

R1 001 Constant 1 F ¬A+1 0001 Data In 1 Write 1
R2 010 F ¬A+ B 0010
R3 011 F ¬A+ B+1 0011
R4 100 F ¬A+ B 0100
R5 101 F ¬A + B+1 0101
R6 110 F ¬A - 1 0110
R7 111 F ¬A 0111
F ¬A ÙB 1000
F ¬A ÚB 1001
F ¬ AÅB 1010
F ¬A 1011
F ¬B 1100
F ¬ sr B 1101
F ¬sl B 1110

Chapter 9 Part 1 25
 Microoperations for the Datapath -
Symbolic Representation
Micr o-
operatio n DA AA BA MB FS MD RW

R1 ¬ R2 – R3 R1 R2 R3 Register F = A + B+ 1 Function Write

R4 ¬ sl R6 R4 — R6 Register F = sl B Function Write
R7 ¬ R7 +1 R7 R7 — Register F = A + 1 Function Write
R1 ¬ R0 +2 R1 R0 — Constant F = A + B Functio n Write
Data out¬ R3 —— R3 Reg ister — — No Wr ite
R4 ¬ Data in R4 —— — — Data in Write
R5¬ 0 R5 R0 R0 Register F = A Å B Function Write

Chapter 9 Part 1 26
 Microoperations for the Datapath -
Binary
m Representation
Microoperations from
aT Binary C
o o

Micro-
operation DA AA BA MB FS MD RW

R1 ¬ R2 – R3 001 010 011 0 0101 0 1

R4 ¬ sl R6 100 XXX 110 0 1110 0 1
R7 ¬ R7 + 1 111 111 XXX 0 0001 0 1
R1 ¬ R0 + 2 001 000 XXX 1 0010 0 1
Data out¬ R3 XXX XXX 011 0 XXXX X 0
R4 ¬ Data in 100 XXX XXX X XXXX 1 1
R5 ¬ 0 101 000 000 0 1010 0 1

 Results of simulation of the above on the

next slide

Chapter 9 Part 1 27
Datapath Simulation
Clock 1 2 3 4 5 6 7 8
DA 1 4 7 1 0 4 5
AA 2 0 7 0
BA 3 6 0 3 0
FS 5 14 1 2 0 10
Constant_in X 2 X
MB
A ddress_out 2 0 7 0
Data_out 3 6 0 2 3 0
Data_in 18 18
MD
RW
reg0 0
reg1 1 255 2
reg2 2
reg3 3
reg4 4 12 18
reg5 5 0
reg6 6
reg7 7 8
Status_bits 2 0 0 1 X
Chapter 9 Part 1 28
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Chapter 9 Part 1 29