J.

Ramprabu AP-2/EEE/KCT
 CISC RISC

Compiler Greater
Compiler
complexity

Code generation
Code generation

Greater Processor Processor

complexity

CISC – Hardware complexity

RISC – Software complexity

J.Ramprabu AP-2/EEE/KCT
 RISC MACHINE
(Reduced instruction set computer)
• INSTRUCTIONS – Less number of instructions that does simple
operations that can execute in single cycle.

• PIPELINING – The instructions are broken down into smaller units

and executed in parallel by pipe lines.

• REGISTERS – Large number of registers sets. That can be used to

store data as well as address.

• LOAD STORE ARCH – Separate load and store instructions are

used to transfer data between registers and external memory

Load – loads the data to processor from memory.

J.Ramprabu AP-2/EEE/KCT
Store – stores the data to memory from processor.
 ARM DESIGN PHILOSOPHY
ARM – ADVANCED RISC MACHINE
The Arm design philosophy are the extended features of RISC system –

1. Processor size is small and low power consumption (portable device like mobile phones).

2. Smaller die size which reduces the cost.

3. High code density is another requirement.

4. Incorporated debug technology -where the software engineers can see what is happening
inside the processor while executing a program. So engineers can easily resolve the issues
easily.

5. variable cycle execution for certain instructions.( eg Load store instruction)

6. Inline barrel shifter (leading to more complex instruction)

7. Thumb 16-bit instruction set (32 bit instruction set)

8. Conditional execution (Specific condition)

9. J.Ramprabu
Enhanced instructions like (DSP AP-2/EEE/KCT
applications , 16 X 16 multiplication)
EMBEDDED SYSTEM HARDWARE

J.Ramprabu AP-2/EEE/KCT
 The Main Hardware components of ARM
1. The ARM PROCESSOR – Controls the whole embedded
system
2. CONTROLLERS – Coordinates the important functional block
(Interrupt and memory controller)
3. The PERIPHERALS – are Responsible for the inputs and
outputs connected external to the chip.
4. BUS- ARM uses ON chip bus which connects peripherals inside the
ARM core (older days we use Peripheral component interconnect bus
( PCI) that connect pripherals externally or off chip eg x86 PC’s)

5. There are two classes of device attached to the bus.

BUS MASTER – Logical device initiate the data transfer (ARM Processor)
BUS SLAVE – Logical device respond to the bus master device (peripherals)

6. The bus has two architecture levels

Level 1 – Elecrical characteristics and bus width (16,32 & 64)
Level 2 – Deals with protocol (logical rules between two devices)
 AMBA BUS PROTOCOL

AMBA – Advanced microcontroller Bus Architecture

ON chip BUS - first introduced in ARM processor in the year 1996

ASB – ARM system bus

APB – ARM peripheral bus
AHB – ARM high perfomance bus

AHB bus provides higher data throughput than ASB

AHB runs higher clock speed AHB-Lite – Single bus master
First bus Supports 64 and 128 data bits AHB Multilayer – Multiple bus master
J.Ramprabu AP-2/EEE/KCT
Performance /costs MEMORY

Cache – faster , costlier which is closer to the processor.

cache
Main memory- Larger in size, placed in separate chips
Secondary storage – size is very large.(hard disks & CD)
Main memory

Secondary storage

Memory size

Width of memory – 8,16,32 &64 bits

Types – ROM –holds boot code, we can read
RAM – we can read and write
DRAM- every few second refreshed by electronic charge.
SRAM- faster than DRAM does not require
SDRAM – operates at high clock frequency , synchronize
with processor (Synchronous dynamic RAM)

J.Ramprabu AP-2/EEE/KCT
 PERIPHERALS

• All ARM peripherals are memory mapped.

Two important PERIPHERAL controllers are
• memory and
• interrupt controller
(Standard and vector interrupt controller)

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 EMBEDDED SYSTEM SOFTWARE
Applications Embedded system – needs software to
drive the hardware
Operating system Software – 4 typical component software
are required to control the embedded
Initialization Device drivers system
Hardware Device

Initialization code –It is the first code executed on the board sets up the parts in
the board before handing control to the operating system.
Operating system- provides infrastructure to control application and manages
hardware resources.
Device drivers- third component which gives software interface to peripherals.
Applications- Task required for a device (mobile phone rquires diary application)
J.Ramprabu AP-2/EEE/KCT
 ARM CORE DATA FLOW MODEL
(Architecture)
Data
Instruction
decoder
Sign extend
Write Read

r15 Register file Rd

r0-r15 Result
pc
Rn Rm

A B A B Acc

Barrel shifter MAC

N
ALU

Address register

Incrementer
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Address
 ARM CORE DATA FLOW MODEL
Instruction decoder – Translates the instruction before executed.

Sign extend – it is hardware which converts signed 8 bit and 16 bit numbers to
32 bit value (taken from memory placed in register).

Register file – Two source registers Rn and Rm and

one destination register Rd

ALU & MAC – Takes the value from source regist through bus A and B and
computes the result and data processing instruction write
the result in Rd to the register file.

Barrel shifter- Together ALU and barrel shifter calculate the wide range of
addresses

Address rergister– Address register hold the address calculated by ALU &
BS.

Incrementer - Incrementer updates the addressJ.Ramprabu

register AP-2/EEE/KCT
whenever load and
 REGISTERS

• ARM processor has 18 active registers. (Each 32 bit wide)

• There are 16 General purpose register ro-r15 (Out of 18).

• General purpose registers hold either data and address

• Left out 2 registers are status registers (CPSR and SPSR).

• The ARM processor has 3 registers assigned to a particular task called

Special function register (SFR) r13,r14 and r15.

– r13 – Stack pointer (sp) – holds the address of the head of the stack
– r14 – Link register (lr) – Core puts the return address whenever it
calls subroutine
– r15 – Program counter – Stores the address of the next instruction
to be executed J.Ramprabu AP-2/EEE/KCT
CPSR- CURRENT PROGRAM STATUS REGISTER
• CPSR – used to monitor and control the internal operation.

• CPSR is 32 bit wide register.

• CPSR is divided into four fields each 8 bit wide (Flag,Status

Extension and control)

• Flag field – contains conditional flags N Z C V.

• Status and Extension field – are reserved for future use.

• Control field – contains 5 bits processor mode of operation

1 bit for Thumb state
2 bit for interrupts
J.Ramprabu AP-2/EEE/KCT
CPSR- CURRENT PROGRAM STATUS
REGISTER

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 PROCESSOR MODES

• ARM Core – The processor can operate in 7 modes.

1. Abort – When processor failed access to memory it enters the abort mode.
2. Fast interrupt request- processor respond to the int level & enters the mode.
3. interrupt request - processor respond to the int level & enters the mode.
4. Supervisor – The processor enters into the mode after reset.
5. System – Special version of user mode allows read write the CPSR.
6. Undefined – processor enters the mode when undefined instruction executed.
7. User – used for program and applications

Priviliged mode (6) – (Mode 1- 6) Allows full read wite access to CPSR
NON Priviliged mode (1) – (user Mode–7) allows read access to control fields

and read write access to conditional flags

J.Ramprabu AP-2/EEE/KCT
 BANKED REGISTERS

• The figure shows all 37 registers

• 20 (37) registers are hidden are called as
banked registers

J.Ramprabu AP-2/EEE/KCT
 The ARM Register Set
CurrentVisible
Current VisibleRegisters
Registers
r0
r0
Abort
Undef
SVC
IRQ
FIQ
User Mode
Mode
Mode
Mode
Mode
Mode r1
r1
r2
r2
r3
r3 Bankedout
Banked outRegisters
Registers
r4
r4
r5
r5
r6
r6 User
User FIQ
FIQ IRQ
IRQ SVC
SVC Undef
Undef Abort
r7
r7
r8
r8 r8 r8
r8
r9
r9 r9 r9
r9
r10
r10 r10 r10
r10
r11
r11 r11 r11
r11
r12
r12 r12 r12
r12
r13 (sp)
r13 (sp) r13 (sp)
r13 (sp) r13 (sp)
r13 (sp) r13
r13 (sp)
(sp) r13
r13 (sp)
(sp) r13
r13 (sp)
(sp) r13 (sp)
r14 (lr)
r14 (lr) r14 (lr)
r14 (lr) r14 (lr)
r14 (lr) r14
r14 (lr)
(lr) r14
r14 (lr)
(lr) r14
r14 (lr)
(lr) r14 (lr)
r15 (pc)
r15 (pc)

cpsr
cpsr
spsr
spsr spsr
spsr spsr
spsr spsr
spsr spsr
spsr spsr

J.Ramprabu AP-2/EEE/KCT
Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

J.Ramprabu AP-2/EEE/KCT
Processor mode bits

J.Ramprabu AP-2/EEE/KCT
 PIPELINE
Pipeline ? – parallel operation which speed up the execution of the
processor.
ARM7 – 3 stage pipeline
Fetch Decode Execute

Fetch - loads the instruction to core from memory

Decode - Translates the instruction
Execute - process the instructionand writes the rsult back to register

Fetch Decode Execute

cycle1 ADD

Time cycle2 SUB ADD

cycle3 CMP SUB ADD

J.Ramprabu AP-2/EEE/KCT
 ARM 9 – 5 stage pipeline

Fetch Decode Execute Memory Write

J.Ramprabu AP-2/EEE/KCT
• The five stages of pipeline are:
1. Fetch – The instruction is fetched from the memory and stored
in the instruction register.

2. Decode – The instruction is moved to the decoder which

decodes the instruction. It activates the appropriate control
signals and takes the necessary steps for the the next
execution stage.

3. Execute – An operand is shifted and the ALU result generated.

If the instruction is a load or store, the memory address is
computed in the ALU.

4. Buffer/Data – Data memory is accessed if required. Otherwise

the ALU result is simply buffered for one cycle.

5. Write back – The result generated by the instruction are

written back to the register file, including any data loaded from
memory.
J.Ramprabu AP-2/EEE/KCT
 ARM10 – 6 stage pipeline

Fetch Issue Decode Execute Memory Write

J.Ramprabu AP-2/EEE/KCT
• ARM 10 –
• It is a six stage pipeline. Which in turn takes 6
cycles to complete the process.

• Same as that of ARM 9 but with an issue stage

which checks whether the instruction is
ready to get decoded in the current stage or
not.

• It nearly doubles the throughput than that of ARM

7.

• The core frequency is higher than that of ARM 9.

J.Ramprabu AP-2/EEE/KCT
INTERRUPT

J.Ramprabu AP-2/EEE/KCT
• An interrupt is a condition that makes the
CPU suspend the current program and
execute an ISR.
• An ISR is a specially written program to
service the condition that caused the
interrupt. After an interrupt is serviced, the
CPU returns to the main program, exactly at
the next instruction where it had left.
• Interrupt vectors are addresses that
inform the interrupt handler as to where to
find the ISR

J.Ramprabu AP-2/EEE/KCT
VECTOR TABLE ADDRESS

J.Ramprabu AP-2/EEE/KCT
• Reset vector is the location of the first instruction executed by the processor
when poweris applied. This instruction branches to the initialization code.

■Undefined instruction vector is used when the processor cannot decode an

instruction.

■Software interrupt vector is called when you execute a SWI instruction.

The SWI
instruction is frequently used as the mechanism to invoke an operating
system routine.

■Prefetch abort vector occurs when the processor attempts to fetch an

instruction from an address without the correct access permissions. The actual
abort occurs in the decode stage.

■Data abort vector is similar to a prefetch abort but is raised when an

instruction attempts to access data memory without the correct access
permissions.

■Interrupt request vector is used by external hardware to interrupt the

normal execution flow of the processor. It can only be raised if IRQs are not
masked in the cpsr.

J.Ramprabu AP-2/EEE/KCT
ARM THUMB JAZELLE

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Condition codes

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ARM NOMENCLATURE

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ARM FAMILIES

J.Ramprabu AP-2/EEE/KCT
Example of an instruction with
Three operands

r1 ,r2 -are the source register

r3 - is the destination register stores the result

J.Ramprabu AP-2/EEE/KCT
Data Processing Instructions
• Move Instructions

J.Ramprabu AP-2/EEE/KCT
• Barrel Shifter:-
• A unique and powerful feature of the ARM processor is the ability to shift the
32-bit binary pattern in one of the source registers left or right by a specific
number of positions before it enters the ALU.

J.Ramprabu AP-2/EEE/KCT
J.Ramprabu AP-2/EEE/KCT
J.Ramprabu AP-2/EEE/KCT
Arithmetic Instructions

N is a register or immediate value

J.Ramprabu AP-2/EEE/KCT
J.Ramprabu AP-2/EEE/KCT
 Using the Barrel Shifter with
Arithmetic
Instructions
• Register r1 is first shifted one location to the left to give the value of twice
r1. The ADD instruction then adds the result of the barrel shift operation to
register r1. The final resulttransferred into register r0 is equal to three times
the value stored in register r1.

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Logical Instructions

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Comparison Instructions

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Multiply Instructions

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J.Ramprabu AP-2/EEE/KCT