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DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

SUBJECT CODE : MVJ19EC34
SUBJECT NAME: DIGITAL SYSTEM DESIGN AND VERILOG
LECTURE PRESENTATION MODULE – 5

Synthesis Basics
FACULTY : Prof. Anu Joy, Asst. Prof, Dept. of ECE

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Digital electronics is a field of electronics involving the study of digital
signals and the engineering of devices that use or produce them. This is in
contrast to analog electronics and analog signals.
Digital electronic circuits are usually made from large assemblies of logic gates,
often packaged in integrated circuits. Complex devices may have simple
electronic representations of Boolean logic functions
DIGITAL SYSTEMS DESIGN USING VERILOG integrates coverage of logic design
principles, Verilog as a hardware design language, and FPGA implementation to
help electrical and computer engineering students master the process of
2
designing and testing new hardware configurations. combinational circuit
examples. An Autonomous Institution ,Affiliated to Visvesvaraya Technological University, Belagavi. Approved By AICTE, New Delhi.
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 SYLLABUS
MODULE 1
Prerequisites: Number systems, Boolean Algebra, Logic Gates, Comparison of Combinational &
Sequential Circuits.
Principles of combinational logic: Introduction, Canonical forms, Minterm & Maxterm Simplification
using Karnaugh maps-3, 4 variables and Quine- McClusky techniques- 3 & 4 variables. [Text1: Chapter
3- 3.2,3.3,3.4,3.5]
Introduction to HDL: Structure of HDL Module, Operators, Data types, Types of Descriptions,
simulation and synthesis, Brief comparison of VHDL and Verilog. [Text 5: Chapter 1]
MODULE 2
Design and Analysis of combinational logic: Full Adder & Subtractors, Parallel Adder and
Subtractor, Look ahead carry Adder, Binary comparators. Decoder, Encoders, Multiplexers &
Demultiplexer, Decoders & Multiplexers as minterm/maxterm Generator. [Text 1: Chapter4- 4.3 to
3
4.6.2, 4.7]
HDL Concepts: Verilog Models for Full Adder & Subtractors, Parallel Adder and Subtractor, Look
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ahead carry Adder, Binary comparators.[[Text 5: Chapter 2- 2.2, 2.3] Decoder, Encoders, Multiplexers
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MODULE 3
Flip-Flops and its Applications: Basic Bi-stable Element, Latches and Flip Flops - SR, JK, Master-
slave JK flip-flops, D, T; Timing considerations in sequential circuits, Characteristic equations,
Registers.[ Text 2: Chapter 6:6.1 to 6.3, 6.4.2, 6.6-6.7]
HDL Concepts: Sequential circuit design on Flipflops in Verilog (behavioural description)

MODULE 4
Sequential Circuit Design: Asynchronous Counter, Design of a synchronous mod-n counter using
clocked JK, D, T and SR flip-flops, Melay & Moore Models, Synchronous Sequential circuit Analysis.
[ Text 2: Chapter 6-6.8-6.9]
HDL Concepts: Sequential circuit design on Synchronous and Asynchronous Counters in Verilog.

MODULE 5
Synthesis Basics: Introduction, Synthesis information from Entity and Module, Mapping Process
4 and

Always in the Hardware Domain. [Text 5: Chapter 10]

ProgrammableAnLogic Devices:
Autonomous PLA, PAL,
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to Visvesvaraya Approach)
Technological University, .[ Approved
Belagavi. Text 3:ByChapter
AICTE, New3]
Delhi.
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 MODULE STRUCTURE

• Synthesis Basics:
• Introduction
• Synthesis information from Entity and
Module
• Mapping Process and Always in the
Hardware Domain. [Text 5: Chapter 10]

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 MODULE STRUCTURE
• Programmable Logic Devices
• PLA
• PAL
• FPGA(Qualitative Approach)
• [ Text 3: Chapter 3]

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 REFERENCE BOOKS

• John M Yarbrough, Digital Logic Applications and Design, Thomson Learning, 2001.

• Donald D. Givone, ―Digital Principles and Design‖, McGraw Hill, 2002.

• Charles H. Roth. Jr. - Digital Systems Design using Verilog, Thomson Learning, Inc, I
edition 2015.

• “Fundamentals of Digital Logic with Verilog Design”- Stephen Brown, Zvonko

Vranesic, Tata McGraw Hill, 2002

• “HDL Programming (VHDL and Verilog)”- Nazeih M.Botros- John Weily India Pvt. Ltd.
2008
7
• Samir Palnitkar ―Verilog HDL: A Guide to Digital Design and Synthesis”, Pearson

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 COURSE OUTCOME
• Illustrate simplification of Algebraic equations using K-map & Quine-McCluskey Technique.

• Use the modern engineering tools such as verilog, necessary for engineering practice.

• Analyze & design different applications of Combinational & Sequential Circuits to

meet desired need within realistic constraints.

• Write code & verify the functionality of digital circuit/system using test benches to

solve engineering problems in digital circuits.

• Know the importance of Synthesis & programmable devices used for designing digital

circuits.
8

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 Synthesis Basics
• Synthesis maps between the simulation (software) domain and the hardware
domain.

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 synthesis steps
• General synthesis steps can be summarized as follows:
• Step 1: If the behavioral description of the system is available, go to Step 3.
Otherwise, formulate a flowchart for the behavior of the system.
• Step 2: Use the flowchart to write a behavioral description of the system.
• Step 3: Simulate the behavioral code and verify that the simulation correctly
describes the system.
• Step 4: Map the behavioral statements into components or logic gates (this
chapter shows you how to do that). Be sure that the components used are
downloadable into the selected chip.
• Step 5: Write a structural- or gate-level description of the components and
logic gates of Step 4. Simulate the structural description and verify that this
simulation is similar to that of Step 3.

10

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• Step 6: Use CAD tools to download the gates and components
of Step 4 into the electronic chip, usually a FPGA chip.
• Step 7: Test the chip by inputting signals to the input pins of the
chip and observe the output from the output pins.
This step is similar to the verification done in Step 5,
except the test here is on real, physical signals.

11

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 Synthesis Information From Entity and
Module
• Entity (VHDL) or Module in (Verilog) provide information on the inputs and
outputs and their types for the system to be synthesized.
• For all the following examples, unless otherwise explicitly stated, the digital
hardware domain in which the HDL code is synthesized consists of binary
signals; their values can be 0, 1, or tristate (open).
• The domain does not include analog or multilevel signals.

12

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 Synthesis Information From Entity (VHDL)

• In all of the examples shown here, libraries are not shown in the code since
they provide no information to the hardware domain.
• Consider the VHDL code shown below
• VHDL Code for System1 Entity
• entity system1 is
• port (a, b : in bit; d : out bit);
• end system1;
• The synthesis information extracted is summarized in Figure below system1
has two input signals, each of one bit, and one output signal of one
bit. Each signal can take 0 (low) or 1 (high).

13

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VHDL Code for System2 Entity

entity system2 is
port (a, b : in std_logic; d : out std_logic);
end system2;

System2 also has two one-bit input signals and one one-bit output signal. However, because the
type is std_logic, each signal can take 0 (low), 1 (high), or high impedance (open).

14

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 VHDL Code for System3 Entity

• entity system3 is
• port (a, b : in std_logic_vector (3 downto 0); d : out std_logic_vector (7 downto
0));
• end entity system3;
• System3 has two four-bit input signals and one eight-bit output signal. The
input signals can be binary or left open.

15

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 VHDL Code for System4 Entity

entity system4 is
port (a, b : in signed (3 downto 0); d : out std_logic_vector (7
downto 0));
end entity system4;

System4 has two four-bit signals and one eight-bit signal. The input
signals are binary; the output signal can be binary or high
impedance

16

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 VHDL Code for System5 Entity

entity system5 is
port (a, b : in unsigned (3 downto 0);d : out std_logic_vector (7 downto
0));
end entity system5;

Synthesis information extracted from system 5 is identical to that

extracted from system 4.

17

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 VHDL Code for System7 Entity

entity system7 is
generic (N : integer := 4; M : integer := 3);
Port (a, b : in std_logic_vector (N downto 0); d : out std_logic_vector (M
downt0));
end system7;

Because N = 4 and M = 3, system7 has two five-bit input signals and one
four-bit output signal. All signals are binary. N and M have no explicit
hardware mapping. Figure illustrates the synthesis information extracted
from the code.

18

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 VHDL Code for ALUS2 Entity
package codes is
type op is (add, mul, divide, none);
end;
use work. codes;

entity ALUS2 is
port (a, b : in std_logic_vector (3 downto 0); cin : in std_logic; opc : in op; z : out
std_logic_vector (7 downto 0); cout : out std_logic; err : out Boolean);
end ALUS2;
The package codes defines type op and Signal opc is of type op. In our digital hardware domain,
there are only zeros and ones. Packages and libraries have no explicit mapping into the
hardware domain; they are simulation tools. To map the signal opc into the hardware
domain, the signal is decoded. Because the signal can take one of four values (add, mul,
divide, or none), it is decoded into two bits. A possible decoding is shown in Table above.
19

Better decoding could be used; choose the one that yields the minimum number of components
after minimization.
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Contd..

Figure above illustrates the information extracted

from the ALUS2 entity . As shown, entity ALUS2 has
two input signals, a and b, each of four bits, one
input signal cin of one bit, one input signal opc of
two bits, one output signal z of eight bits, one output
20
signal cout of one bit, and one output signal err of
one bit. The Boolean type is mapped to binary 0 or 1.
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 VHDL Code for Array1
Entity package array_pkg is
constant N : integer := 4;
constant M : integer := 3;
subtype wordN is std_logic_vector (M downto 0);
type strng is array (N downto 0) of wordN;
end array_pkg;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use work.array_pkg.all;

entity array1 is
generic (N : integer := 4; M : integer := 3);
Port (a : in strng; z : out std_logic_vector (M downto 0));
end array1;
21

From the package, type strng is an array of five elements, and each element is four bits wide,
so entity array1 has five input signals, each of four bits. The output of array1 is a four-bit
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 VHDL Code for Weather_frcst
• Entity package weather_fcst is
• Type cast is (rain, sunny, snow, cloudy);
• Type weekdays is (Monday, Tuesday, Wednesday, Thursday, Friday, Saturday, Sunday);
• end package weather_fcst;

• library ieee;
• use ieee.std_logic_1164.all;
• use std.textio.all;
• use work.weather_fcst.all;

• entity WEATHER_FRCST is
• port (Day_in : in weekdays; out_temperature : out integer range -100 to 100; out_day : out
weekdays; out_cond : out cast);
• end WEATHER_FRCST;
22

• Elements of type cast in package weather_fcst can be decoded by two bits, as shown in Table.

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 Contd..

The elements of type weekdays need three bits to be decoded. Table 10.3
shows a possible decoding of these elements.

Accordingly, entity WEATHER_FRCST has one input signal, Day_in,

which is three bits, an output signal, out_temperature, of seven
bits, an output signal, out_day, of three bits, and an output signal,
out_cond, of two bits.
23

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 VHDL Code for Entity Procs_Mchn
• library ieee;
• use ieee.std_logic_1164.all;
• package state_machine is
• Type machine is (state0, state1, state2, state3);
• Type st_machine is
• record
• state : machine;
• weight : natural range 3 to 16;
• Measr : std_logic_vector (5 downto 0);
• end record;
• end package state_machine;

24

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 Contd..
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
use work.state_machine.all ;

entity Procs_Mchn is port (S : in machine; Y : in st_machine; Z : out integer

range -5 to 5);
end Procs_Mchn;

25

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 Contd..
The entity Procs_Mchn has two inputs, S and Y, and one output, Z.
• Input S is of type machine; this type has four elements, so input S is mapped to two
bits.
• Input Y is of type st_machine; this type is record (a collection of different types).
• The record includes type state, which is mapped to a two-bit signal, type
weight, which is mapped to a five-bit signal, and type Measr, which is mapped
to a six-bit signal.
• So, signal Y is mapped to six bits (the largest out of two, five, and six).
• Output Z is mapped to a four-bit signal.

26

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 Verilog Synthesis Information From Module
Inputs/Outputs

Verilog, in contrast to VHDL, does not have a large variety of

types. In the following, we discuss synthesis information that can be
extracted from the inputs and outputs of a module.

Verilog Code for Module System1v

module system1v (a, b, d);
input a, b;
output d;
endmodule

Here system1v has two input signals, a and b, each of one bit, and one
output signal d of one bit. All signals can take 0, 1, or high impedance.
Figure shows the synthesis information extracted from the above code.

27

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 Verilog Code for Module System2v

module system2v (X, Y, Z);

input [3:0] X, Y;
output [7:0] Z;
reg [7:0] Z
........
endmodule

Listing describes system2v with two input signals, X and Y,

each of four bits, and one output signal, Z, of eight bits. The
statement reg [7:0] Z; does not convey any additional
information to the hardware domain; its use is solely for
simulation.

28

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 Verilog Code for Module System3v

module system3v (a, b, c);

parameter N = 4;
parameter M = 3;
input [N:0] a;
output [M:0] c;
input b;
.........
endmodule

Module system3v has two input signals, a and b, and one output signal c. Input a is a
five-bit signal, input b is one bit, and output c is a four-bit signal. Parameter has no
explicit mapping in the hardware domain; it is just a simulation tool to instantiate
N and M. 29

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 Verilog Code for Module Array1v

module array1v (start, grtst);

parameter N = 4;
parameter M = 3;
input start;
output [3:0] grtst;
reg[M:0] a[0:N];
..............
endmodule

Module array1v has one one-bit input signal (start) and one four-bit output signal (grtst). 30
The register a is an array of five elements, each of four bits. This register is mapped to
five signals, each of four bits.
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 Mapping Process and Always in the
Hardware Domain
• Process (VHDL) and Always (Verilog) are the major behavioral statements.
• These statements are frequently used to model systems with data
storage such as counters, registers, and CPUs.
• The first line in both statements declares, among other factors, the sensitivity
list.
• This list determines the signals that activate process or always.
• The following examples illustrate the mapping of process and always.

31

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 Mapping the Signal-Assignment
Statement to Gate
Mapping VHDL Code for Signal-Assignment Statement Y <= X

library ieee;
use ieee.std_logic_1164.all;
entity SIGNA_ASSN is
port (X : in bit; Y : out bit);
end SIGNA_ASSN;
architecture BEHAVIOR of SIGNA_ASSN is
begin
P1 : process (X)
begin
Y <= X;
end process P1;
end BEHAVIOR;

32

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 Mapping Verilog Code for Signal-Assignment
Statement Y = X
module SIGNA_ASSN (X, Y);
input X;
output Y;
reg y;
always @ (X)
begin
Y = X;
end
endmodule

The code in Listing above describes a one-bit input signal X and a one-bit output signal Y (see Figure).

In VHDL Listing, the entity is bound to architecture BEHAVIOR. The process has X as the sensitivity list.
The signal-assignment statement states that Y = X. In the hardware domain, this statement is mapped to a
buffer. Other statements such as begin, end, and architecture have no hardware mapping. The same
applies for Listing in verilog; the hardware is a buffer. Figure (b) shows this mapping: if X changes, Y 33is
updated.

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 VHDL & Verilog Code for Signal-Assignment
Statement Y = 2 * X + 3:
VHDL Signal-Assignment Statement Y = 2 *X + 3

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity sign_assn2 is
port (X : in unsigned (1 downto 0);
Y : out unsigned (3 downto 0));
end ASSN2;
architecture BEHAVIOR of sign_assn2 is
begin
P1 : process (X)
begin
Y <= 2* X + 3; // assign values to signals
end process P1;
end BEHAVIOR; 34

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 Contd..
• Verilog Signal-Assignment Statement Y = 2 *X + 3

module sign_assn2 (X, Y);

input [1:0] X;
output [3:0] Y;
reg [3:0] Y;
always @ (X)
begin
Y = 2 *X + 3;
end
endmodule
35

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• Listing above shows an entity (sign_assn2) with one input, x, of two
bits and one output, Y, of four bits (see Figure).
• The architecture that is bound to the entity and the VHDL includes
one process (P1) and Verilog module includes one always,
respectively.
• The process (always) contains one signal-assignment statement: Y
<= 2 * X + 3;(VHDL) and Y=2*X+3; (Verilog).
• To synthesize the code, construct a truth table to find the logic
diagram of sign_assn2 and use gate-level synthesis.
• Table shows the truth table of sign_assn2.

36

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From Table 10.4:

Figure b shows the gate-level logic diagram of

Listing 10.17.

To verify the synthesis, write the structural code

for the logic diagram shown in Figure b and then
simulate it.
If the simulation waveform is the same as the
simulation waveform in Listing 10.17, then the
synthesis is correct. The simulation waveform for
Listing 10.17 is shown in Figure 10.16. The Verilog
structural code is shown in Listing 10.18.
37

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 Structural Verilog Code for the Logic Diagram in Figure
10.15b.
module sign_struc(X, Y);
input [1:0] X;
output [3:0] Y;
reg [3:0] Y;
always @ (X)
begin
Y[0] = 1'b1;
Y[1] = ~ X[0];
Y[2] = X[0] ^ X[1];
Y[3] = X[1] & X[0];
end
endmodule

After simulating the code, the simulation is identical to 38

Figure 10.16. We conclude that the synthesis is correct.

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 Mapping the VHDL Variable-Assignment
Statement to Gate Level
The variable-assignment statement is a VHDL statement. Verilog does not
distinguish between signal- and variable-assignment statements.

VHDL Variable-Assignment Statement

library ieee;
use ieee.std_logic_1164.all;
entity parity_even is
port (x : in std_logic_vector (3 downto 0); C : out std_logic);
end parity_even;
architecture behav_prti of parity_even is
begin
P1 : process (x)
variable c1 : std_logic;
begin
c1 := (x(0) xor x(1)) xor (x(2) xor x(3)); //assign values to variables
C <= c1; // assign values to signals
end process P1; 39
end behav_prti;

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• Listing shows an entity with one four-bit input and one one-
bit output (see Figure).
• The architecture behav_prti is bound to the entity and
consists of one process (P1).
• The process contains one variable declaration, variable c1 :
std_logic; and two assignment statements.
• One of the assignment statements is a signal, C <= c1;, and
the other is a variable assignment: c1 := (x(0) xor x(1)) xor
(x(2) xor x(3));

• The hardware domain cannot distinguish between

signal and variable; all we have in the hardware domain
are signals.
• To synthesize the code, notice that signal C takes the value of
variable c1, so in the hardware domain, c1 and C are
one signal.
• The variable-assignment statement includes three XOR
functions that are mapped to three XOR gates .Figure shows 40
the gate-level synthesis.

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40
 Mapping Logical Operators
Mapping logical operators is relatively straightforward because finding the gate
counterpart of a logical operator is very easy. For example, the mapping of logical
operator (VHDL) or & (Verilog) of AND gate. Table shows the logical operators in VHDL
and Verilog and their gate level mappings.

41

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41
 Mapping Logical Operators: VHDL and Verilog
VHDL Mapping Logical Operators
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decod_var is
port (a : in std_logic_vector (1 downto 0); D : out std_logic_vector (3 downto 0));
end decod_var;

architecture Behavioral of decod_var is

begin
dec : process (a)
variable a0bar, a1bar : std_logic;
begin
a0bar := not a(0);
a1bar := not a(1);
D(0) <= not (a0bar and a1bar);
D(1) <= not (a0bar and a(1));
D(2) <= not (a(0) and a1bar);
D(3) <= not (a(0) and a(1));
end process dec; 42
end Behavioral;

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42
Verilog: Mapping Logical Operators
module decod_var (a, D);
input [1:0] a;
output [3:0] D;
reg a0bar, a1bar;
reg [3:0] D;
always @ (a)
begin
a0bar = ~ a[0];
a1bar = ~ a[1];
D[0] = ~ (a0bar & a1bar);
D[1] = ~ (a0bar & a[1]);
D[2] = ~ (a[0] & a1bar);
D[3] = ~ (a[0] & a[1]); 43

end
endmodule
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43
The statements :
a0bar := not a(0); -- VHDL
a0bar = ~ a[0]; // Verilog
represent an inverter. The input to the inverter is the least significant bit of the input a.
The statements :
D[3] = ~ (a[0] & a[1]); -- VHDL
D(3) <= not (a(0) and a(1)); // Verilog
represent a two-input NAND gate. The input is a, and the output is the most significant bit of D

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 Mapping the IF Statement
VHDL IF-else Description

process (a, x)
begin
if (a = '1’) then
Y <= X;
else
Y <= '0';
end if;
end process;

Verilog IF-else Description

always @ (a, X)
begin
if (a == 1'b1)
Y = X;
else
Y = 1'b0; 45
end

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45
Example of Multiplexer IF-else Statement: VHDL and Verilog

VHDL Multiplexer IF-else Description

process (a, X, X1)
begin
if (a = '1’) then
Y <= X;
else
Y <= X1;
end if;
end process;

Verilog Multiplexer IF-else Description

always @ (a, X, X1)
begin
if (a == 1'b1)
Y = X;
else
Y = X1;
end 46

The IF statement represents a 2x1 multiplexer. Figure shows the synthesis of this.
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46
Example of Comparison Using IF-else Statement: VHDL and Verilog
VHDL IF-else Statement
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity IF_st is
port (a : in std_logic_vector (2 downto 0);
Y : out Boolean);
end IF_st;

architecture IF_st of IF_st is

begin
IfB : process (a)
variable tem : Boolean;
begin
if (a < "101") then
tem := true;
else
tem := false;
end if;
Y <= tem; 47

end process;
end IF_st;
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47
Verilog IF-else Statement

module IF_st (a, Y);

input [2:0] a;
output Y;
reg Y;
always @ (a)
begin
if (a < 3’b101)
Y = 1'b1;
else
Y = 1’b0;
end
endmodule

To find the gate-level mapping, construct a truth table.

48

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48
 Y= a(2) + a(1) a(0)

From the Boolean function, draw the gate-level synthesis for Listing 10.22 as
shown in Figure

49

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49
Example of elseif and Else-If: VHDL and Verilog
VHDL elseif Description
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
entity elseif is
port (BP : in natural range 0 to 7; ADH : out natural range 0 to 15);
end;
architecture elseif of elseif is
begin
ADHP : process(BP)
variable resADH : natural := 0;
begin
if BP <= 2 then resADH := 15;
elsif BP >= 5 then resADH := 0;
else
resADH := BP * (-5) + 25;
end if;
ADH <= resADH;
end process ADHP;
end elseif;

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Verilog Else-If Description

module elseif (BP, ADH);

input [2:0] BP;
output [3:0] ADH;
reg [3:0] ADH;
always @ (BP)
begin
if (BP <= 2) ADH = 15;
else if (BP >= 5) ADH = 0;
else
ADH = BP * (-5) + 25;
end
endmodule

The variable resADH (VHDL) is identical in value to the output ADH. Accordingly, resADH is
not mapped into the hardware domain. To synthesize the code, construct the truth table.

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 Truth Table
BP ADH
Bit21 Bit32
0 10
000 1111
001 1111
010 1111
011 1010
100 0101
101 0000
110 0000
111 0000

From Table 10.7, construct K-maps to find ADH

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 Gate-level synthesis.

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Example of IF Statement with Storage:
VHDL and Verilog
VHDL IF Statement with Storage

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity If_store is
port (a, X : in std_logic; Y : out std_logic);
end If_store;
architecture If_store of If_store is
begin
process (a, X)
begin
if (a = ‘1’) then
Y <= X;
end if;
end process;
end If_store;

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Verilog IF Statement with Storage
module If_store (a, X, Y);
input a, X;
output Y;
reg Y;
always @ (a, X)
begin
if (a == 1’b1)
Y = X;
end
endmodule

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The IF statement in Listing 10.25 is similar to that of Listing 10.22(Example of Multiplexer If-
else statement), except when a = 0. In Listing 10.22, the value of the output Y is
explicitly stated when a = 0. In Listing 10.25, the code states that when a = 0, there
should be no change in the values of any signal. This means that the value of all signals
should be stored during the execution of the IF statement. To store signals in the hardware
domain, latches or flip-flops are used.

In Listing 10.25, signal a is implemented as a clock to a D-latch; the input to the latch is the
signal X. If a = 0, then the output of the latch stays the same. If a = 1, then the output follows
the input X. Below Figure shows the mapping of Listing 10.25 to the hardware domain.

Synthesis of Listing 10.25

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Else-If Statement with Gate-Level Logic
package weather_fcst is
Type unit is (cent, half, offset);
end package weather_fcst;

library ieee;
use ieee.std_logic_1164.all;
use work.weather_fcst.all;

entity weather is
port (a : in unit; tempr : in integer range 0 to 15;
z : out integer range 0 to 15);
end weather;

architecture weather of weather is

begin
T : process (a, tempr)
variable z_tem : integer range 0 to 15;
begin
if ((tempr <= 7) and (a = cent)) then
z_tem := tempr;
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elsif ((tempr <= 7) and (a = offset)) then
z_tem := tempr + 4;
elsif ((tempr <= 7) and (a = half)) then
z_tem := tempr /2;
else
z_tem := 15;
end if;
z <= z_tem;
end process T;
end weather;

From the entity (module), the extracted information can be summarized as

follows:
 Input a is a two-bit signal.
 Input tempr is a four-bit signal.
 Output z is a four-bit signal.
The code can be summarized as shown in Table

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If we want to construct a truth table, it will be a (2 + 4 = 6) six-bit input and four-bit
output; this table will be huge and cannot be analyzed easily.

Accordingly, the code in Listing 10.26 is analyzed logically. Input a can be the select
lines of a multiplexer. The multiplexer has four inputs; each input is a four-bit signal
representing one of the four values tempr, tempr+4, tempr/2, or the constant 15.

RTL synthesis

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 Truth Table for Logic 1

Inspecting , tempr +4 can be written as:

For logic 2, do the same as for Logic 1. Below Table shows the truth table
of Logic 2.

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 Truth Table for Logic 2

After inspecting Table

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For the select in Figure to satisfy the condition temp ≤ 7, tempr (3) must be
equal to 0.

Accommodating the values of a, construct a truth table as shown in Table.

Truth Table for Select

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From the K-maps:
Select(0) = temp(3) + a(0)
Select(1) = temp(3) + a(1)

Incorporating the gate-level logic of Logic 1, Logic 2, and Select, the synthesis
diagram of Listing 10.26 is shown in Figure.

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 Mapping the case Statement

Mapping the case statement is very similar to mapping the IF

statement. The case statement is treated as a group of IF
statements. Consider the case statement in Listing 10.27.
Example of case Mapping
module case_nostr (a, b, ct, d);
input [3:0] a, b;
input ct;
output [4:0] d;
reg [4:0] d;
always @ (a, b, ct)
begin
case (ct)
1’b0 : d = a + b;
1’b1 : d = a - b;
endcase
end
endmodule
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To synthesize the above code, construct a truth table. This table would have (4 + 4 +1
= 9) nine bits input for a, b, and ct, and five bits for the output d. This table would
yield a minimum number of gates for the code in Listing 10.27; however, the table
would be very large and hard to analyze. Another approach is to logically analyze the
code using RTL blocks.
Listing 10.27 includes two operations: four-bit addition and four-bit subtraction. The
result is expressed in a five-bit output, d. Signal ct selects whether to add or subtract.
To add, use four one-bit ripple-carry adders.
To subtract, use four one-bit subtractors, but the number of components can be
reduced by noticing that the full adder can be used as a subtractor, as shown below:
d = a – b = a + (–b) = a + b + 1
Figure shows the RTL synthesis of Listing 10.27. The XOR gate is implemented to
generate the complement of signal b.

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Now, slightly change the code of Listing 10.27 to that shown in Listing
10.28.

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 case Statement with Storage
module case_str (a, b, ct, d);
input [3:0] a, b;
input ct;
output [4:0] d;
reg [4:0] d;
always @ (a, b, ct)
begin
case (ct)
1’b0: d = a + b;
1’b1: ; /*This is a blank statement with no operation (null in VHDL)*/
endcase
end
endmodule

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The case statement does not specify an action when ct = 1, so a latch is used to store
the value of d when ct = 1. Below figure shows the RTL synthesis.

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Verilog casex
module Encoder_4 (IR, RA);
input [3:0] IR;
output [3:0] RA;
reg [3:0] RA;
always @ (IR)
begin
casex (IR)
4’bxxx1 : RA = 4’d1;
4’bxx10 : RA = 4’d2;
4’bx100 : RA = 4’d4;
4’b1000 : RA = 4’d8;
default : RA = 4’d0;
endcase
end
endmodule

To synthesize the code, build a truth table as shown in Table below.

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 Truth Table for the Code

Notice the input IR has explicit value for all of its entries, so synthesis does not need
storage. By inspecting the Table, the Boolean function of the output can be written as:

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 Below Figure shows the logic diagram

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Example of case with Storage
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package types is
type states is (state0, state1, state2, state3);
end;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all; 73

entity state_machine is
port (A, clk : in std_logic; pres st : buffer states;
Z : out std_logic);
end state_machine;

architecture st_behavioral of state_machine is

begin
FM : process (clk, pres_st, A)
variable present : states := state0;
begin

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if (clk = ‘1’ and clk’event) then
--clock’event is an attribute to the signal clk;
--the above if Boolean expression means the positive
-- edge of clk
--
case pres_st is
when state0 =>
if A ='1' then
present := state1;
Z <= '0';
else
present := state0;
Z <= '1';
end if;
when state1 => if A ='1’ then
present := state2;
Z <= '0';
else
present := state3;

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Z <= '0';
end if;
when state2 => if A ='1' then
present := state3;
Z <= '1';
else
present := state0;
Z <= '0';
end if;
when state3 => if A ='1' then
present := state0;
Z <= '1';
else
present := state2;
Z <= '1';
end if;
end case;
pres_st <= present;
end if;
end process FM;
end st_behavioral;
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In Listing 10.30, the package types declares user-select types state0, state1, state2,
and state3. To decode these user-selected types into the hardware domain, two bits
are needed. So, state0 is decoded as 00,
state1 as 01, state2 as 10, and state3 as 11. The libraries are software constructs
that have no mapping into the hardware domain.
Now let us summarize the information collected from the entity. The name of the
system or entity is state-machine. The system has a one-bit input A, a one-bit input
clk, two-bit input/output states, and a one-bit output Z. The architecture consists of
case and IF statements. Let us see if we need to use a storage element. Consider the
case pres_st is
case statement:
when state0 => if A ='1' then
present := state1;
Z <= '0';
else
present := state0;
Z <= '1';
end if;

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In order to know to which state to go, we need to know the present state. For
example, if the present state is state0, then the next state can be state1 or state0.
The code implies that the current state must be remembered, so, accordingly,
storage elements are needed to synthesize the code.

The best approach here is to follow the same steps covered in Chapter 4 for
analyzing state machines. Write the excitation table of the machine and use D flip-
flops. Table here shows the excitation table for Listing 10.30.
Excitation Table for Listing 10.30

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 From Table 10.13, construct K-maps to minimize
the outputs.
Figure 10.32 shows the K-maps.

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 RTL logic diagram of Listing 10.30.

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 From the K-maps, find the Boolean function of the system
as:

D0 = A Q1 Q0 + A Q0

D1 = Q0 Q1 + A Q0 + A Q1 Q0

Z = Q1 + A Q0

From the Boolean function, the logic diagram of the

system is drawn.

Figure shows the logic diagram of Listing 10.30.

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Mapping the Loop Statement
Loop in HDL description is an essential tool for behavioral modeling. It is, however,
easier to code than it is to synthesize in the hardware domain. The problem is the
repetition involved in the loop. For example, consider the VHDL Loop statement
shown in Listing 10.31.

LISTING 10.31 A For-Loop Statement: VHDL and Verilog

VHDL For-Loop Statement

for i in 0 to 63 loop
temp(i) := temp(i) + b(i);
end loop;

Verilog For-Loop Statement

for i = 0; i <= 63; i = i + 1

begin
temp[i] = temp[i] + b[i];
end

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As shown in Listing 10.31, the loop repeats the statement temp(i) = temp(i) + b(i) 64
times. This statement can be synthesized using adders. Each time the statement
repeats, the index of the operands to be added is incremented. So the three lines of
code in Listing 10.31 result in 64 adders. The straightforward approach to
synthesizing a loop is to expand the loop into statements and synthesize each
statement individually. For example, the loop in Listing 10.31 can be logically written
as:

temp(0) = temp(0) + b(0)

temp(1) = temp (1) + b(1)
temp(2) = temp(2) + b(2)
……………………………
temp(63) = temp(63) + b(63)

Each statement is synthesized as a one-bit adder.

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 SYNTHESIS OF THE LOOP
STATEMENT
LISTING 10.32 VHDL Code Includes For-Loop

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Listing10_32 is
port (a : in std_logic_vector (3 downto 0);
c : in integer range 0 to 15;
b : out std_logic_vector (3 downto 0));
end Listing10_32;

architecture Listing10_32 of Listing10_32 is

begin
shfl : process (a, c)
variable result, j : integer;
variable temp : std_logic_vector (3 downto 0);
begin
result := 0;

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 lop1 : for i in 0 to 3 loop
if a(i) = ‘1’ then
result := result + 2**i;
end if;
end loop;
if result > c then
lop2 : for i in 0 to 3 loop
j := (i + 2) mod 4;
temp (j) := a(i);
end loop;
else
lop3 : for i in 0 to 3 loop
j := (i + 1) mod 4;
temp (j) := a(i);
end loop;
end if;
b <= temp;
end process shfl;
end Listing10_32;

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The code in Listing 10.32 describes a system with one four-bit input a, one integer input c,
and a four-bit output b. In the hardware domain, there are only bits, so the integer c
(because its range is from 0 to 15), is represented by four bits. If you are using a vendor’s
synthesizer, be sure to specify the integer range; otherwise, the synthesizer, because it
does not know the range, will allocate more than 32 bits for the integer. Figure summarizes
the information retrieved from the entity.

Information retrieved from entity Listing 10.32

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The simulation output of the system described by Listing 10.32 is shown in Figure.
From the figure, the system shuffles input a with two shuffling patterns, depending on
whether or not a is greater than c.

Simulation output of Listing 10.32.

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The code in Listing 10.32 included a process labeled shfl. The process has an IF
statement and three For-Loops: lop1, lop2, and lop3. The first For-Loop, lop1,
converts the std_logic_vector a to an integer. This conversion is ignored by the
hardware domain; the main goal of this conversion is to be able to compare a with the
integer c. The hardware views the variable result and a as the same signal. The IF
statement that starts with if result > c then is complete; if result > c, then loop lop2
is executed. Otherwise, loop lop3 is executed.
Expanding Accordingly, latches are not needed to
the Loop lop2
synthesize this IF statement. For loop lop2, expand the loop as shown in below Table.

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Notice from Listing 10.32 that the variable temp is identical to signal b; the
hardware domain views b and temp as the same signal. For loop lop3, expand the
loop as shown in the following Table.Loop lop3
Expanding

From previous Tables, the logic diagram of the system consists of a four-bit
magnitude comparator and four 2x1 multiplexers. The four-bit comparator can be
built from four-bit adders.

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 RTL synthesis of Listing 10.32.
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Mapping Procedures or Tasks
Procedures, tasks, and functions are code constructs that optimize HDL module
writing. In the hardware domain, there is no logic for procedures or tasks; they are
incorporated in the entity or the module that calls them. Consider the Verilog code for
a task shown in Listing 10.33.

Listing 10.33 A Verilog Example of a Task

module example_task (a1, b1, d1);

input a1, b1;
output d1;
reg d1;
always @ (a1, b1)
begin
xor_synth (d1, a1, b1);
end
task xor_synth;
output d;
input a, b;
begin
d = a ^ b;
end
endtask
endmodule
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90
The task is performing a logical XOR operation on two operands, aand b. By
incorporating this information in the module example_task, the module can be
summarized as a system with two one-bit inputs, a1and b1, and one one-bit output,
d1. The relationship between d1and a1and b1is:
d1 = a1 b1

The synthesis of this module is shown in below Figure.

Synthesis of Listing 10.33

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LISTING 10.34 An Example of a Procedure

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Int_Bin is
generic (N : integer := 3);
port (X_bin : out std_logic_vector (N downto 0);
Y_int : in integer;
flag_even : out std_logic);
end Int_Bin;
architecture convert of Int_Bin is
procedure itb (bin : out std_logic_vector;
signal flag : out std_logic;
N : in integer; int : inout integer) is
begin
if (int MOD 2 = 0) then
flag <= ‘1’;
else
flag <= ‘0’;
end if;
for i in 0 to N loop
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 if (int MOD 2 = 1) then
bin (i) := ‘1’;
else
bin (i) := ‘0’;
end if;
int := int / 2;
end loop;
end itb;
begin
process (Y_int)
variable tem : std_logic_vector (N downto 0);
variable tem_int : integer;
begin
tem_int := Y_int;
itb (tem, flag_even, N, tem_int);
X_bin <= tem;
end process;
end convert;

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Let’s analyze the procedure itb. This procedure has two outputs (flag and bin), one
input (N) and one inout (int). In the hardware domain, there is no distinction between
variables and signals: all are signals. Also, type integer has to be converted to binary.
The signal flag checks to see if signal int is divisible by two (even) or not (odd). This
is done by the statements:
if (int MOD 2 = 0) then
flag <= ‘1’;
else
flag <= ‘0’;
end if;
The procedure also includes a For-Loop:
for i in 0 to N loop
if (int MOD 2 = 1) then
bin (i) := ‘1’;
else
bin (i) := ‘0’;
end if;
int := int / 2;
end loop;

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The loop is converting type integer int to binary bin. This conversion is not mapped to the
hardware domain. As mentioned above, all signals in the hardware domain are binary; we
cannot have an integer signal in the hardware domain. So, for our synthesis, the procedure
is performing a test to see whether the signal is even or odd.

Now let’s analyze the entity Int_Bin. The entity has two outputs: a four-bit signal X_bin
(because N = 3) and a one-bit signal flag_even. The entity has one input of type integer,
Y_int. The entity has one process:

process (Y_int)
variable tem : std_logic_vector (N downto 0);
variable tem_int : integer;
begin
tem_int := Y_int;
itb (tem, flag_even, N, tem_int);
X_bin <= tem;
end process;

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The process is calling the procedure itb, the integer Y_int is converted to binary X_bin,
and flag_even is assigned a value of 1 if Y_int is even or 0 if it is odd. To find the
hardware logic of flag_even, notice that if a binary number is even, its least significant
bit is 0. Otherwise, the number is odd. So, flag_even = X_bin(0)bar. That is all there is to
the synthesis of Listing 10.34. Figure 10.38 shows the synthesis of Listing 10.34; it is just
a single inverter.

Synthesis of Listing 10.34.

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 Mapping the Function Statement

Functions, like procedures, are simulation

constructs; they optimize the HDL module
writing style. Consider the Verilog code
shown in Listing 10.35.
module Func_synth (a1, b1, d1);
input a1, b1;
output d1;
reg d1;
always @ (a1, b1)
begin d1 = andopr (a1, b1);
end function andopr;
input a, b;
begin andopr = a ^ b;
end
Endfunction
endmodule
In the hardware domain, there is no distinction between the main module
and a function; we look to see what the function is performing and then
incorporate this information in the entity or module where the function

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is being called. For example, in Listing 10.35, the function andopr is
performing an AND logical operation on two operands. The result is a single
operand. In the module Func_synth, this function is called to perform an AND
operation on the two inputs of the module, a1 and b1; the result is stored in
the output of the module d1. Listing 10.35 is synthesized as shown in Figure
10.39; it has an AND gate with two one-bit inputs, a1 and b1, and a one-bit
output, d1.

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 Example of Function Synthesis

module Function_Synth2 (x, y);

input [2:0] x; output [3:0] y; reg [3:0] y;
always @ (x)
begin y = fn (x);
end
function [3:0] fn;
input [2:0] a;
begin if (a <= 4)
fn = 2 * a + 5;
end
endfunction
endmodule

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• The function in Listing 10.36 has one three-bit input a and one four-bit output fn.
If the value of the input is less than or equal to four, the output is calculated as
fn = 2 * a + 5.

• If the input is greater than four, the function does not change the previous
value of the output. Incorporating the function into the module Function_Synth2,
we summarize the module as representing a system with one three-bit input x
and one four-bit output y. If x is less than or equal to four, y = 2 *a + 5.

• If x is greater than four, y retains its previous value. This means that latches
must be used to retain the previous value. Figure 10.40 shows the simulation
output of the module Function_ Synth2. As is shown, if x is greater than four, y
retains its previous value.

• To synthesize this module, we use four high-level triggered D-latches because

output y is four bits. If x is from zero to four, these latches should be
transparent; if x is from five to seven, these latches should be inactive. We
design a signal clk connected to the clock of the latches; if x is from zero to four,
the clk is high; otherwise, it is low. Table 10.16 shows the truth table of signal
clk.

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 Mapping the Verilog User-Defined Primitive
In Chapter 8, Verilog user-defined primitive (UDP) was covered. Listing
10.37 shows a copy of Listing 8.15 where UDP was implemented

LISTING 10.37 (same as Listing 8.15) Verilog Code 2x1 Multiplexer

with Active-Low Enable Using Combinational User-Defined
Primitive
module Mux2x1Prmtv(A, B, SEL, Gbar,Y);
input A,B,SEL,Gbar;
output Y;
multiplexer MUX1 (Y, Gbar, SEL,A,B) ;
endmodule
primitive multiplexer (mux, enable, control, dataA, dataB) ; output mux;
input enable, control, dataA, dataB;
table

endtable
endprimitive

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To synthesize the code of Listing 10.37, we follow the same steps shown in
Figure 10.1. The module can be summarized as a system with four one-bit
inputs A, B, SEL, Gbar, and one one-bit output Y. The relationship between
the output and the inputs of the system is shown in the statement table in
Listing 10.37. To synthesize the code, a truth table is built; it is very similar
to the contents of the statement table except, due to limitations of the
hardware domain, the operator ? is replaced with the “don’t care” operator
x. Table 10.18 shows the truth table of representing the module in the
hardware domain.

Table 10.18 is the same as Table 2.4, and the logic

diagram of Listing 10.37 is the same as Figure 2.9.

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 2x1 Multiplexer. a) Logic symbol. b) Logic diagram.

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Programmable Logic Devices (PLD)
A programmable logic device (or PLD) is a general name for a digital integrated circuit

capable of being programmed to provide a variety of different logic functions. Simple

combinational PLDs are capable of realizing from 2 to 10 functions of 4 to 16 variables
with a single integrated circuit. More complex PLDs may contain thousands of gates and
flip-flops. Thus, a single PLD can replace many integrated circuits, and this leads to lower
cost designs. When a digital system is designed using a PLD, changes in the design can
easily be made by changing the programming of the PLD without having to change the
wiring in the system.

PLA – Programmable Logic Array

PAL – Programmable Array Logic
FPGA – Field Programmable Gate Array

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Programmable Logic Arrays
 A PLA with n inputs and m outputs can realize m functions of n variables.
 An AND array realizes selected product terms of the input variables and the OR
array ORs together the product terms needed to form the output functions. So, a
PLA implements a sum-of-products expression.
 Product terms are formed in the AND array by connecting switching elements at
appropriate points in the array.

Programmable Logic
Array
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To form A B, switching elements are used to connect the first word line with the A and
B lines. Switching elements are connected in the OR array to select the product terms
needed for the output functions.

For example, F0 = A B + A C, switching elements are used to connect the

A B and AC lines to the F0 line. The connections in the AND and OR arrays of
this PLA make it equivalent to the AND-OR array of below figure

AND-OR Array Equivalent

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The contents of a PLA can be specified by a PLA table. The input side of the table
specifies the product terms. The symbols 0, l, and – indicate whether a variable is
complemented, not complemented, or not present in the corresponding product term.
The output side of the table specifies which product terms appear in each output
function. A 1 or 0 indicates whether a given product term is present or not present in
the corresponding output function.
PLA Table

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Ex: Realize these equations using PLA

f1 = m(2, 3, 5, 7, 8, 9, 10, 11, 13, 15)

f2 = m(2, 3, 5, 6, 7, 10, 11, 14, 15)
f3 = m(6, 7, 8, 9, 13, 14, 15)

Sol:

1. Minimize the equations using k maps.

f1 = bd + bc + ab

f2 = c + abd

f3 = bc + abc + abd

2. Construct a PLA table

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 By inspecting the maps, we can see that terms
a’bd (from f2),abd (from f3),and abc’ (from f3) can
be used in f1. If bd is replaced with a’bd+ abd,
then the gate needed to realize bd can be
eliminated.
ab'c' (from f3) can be used to cover m8 and m9,
and the gate needed to realize ab' can be
eliminated. The minimal solution Is therefore

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 2. Draw the logic diagram showing the corresponding PLA structure, which has four
inputs, six product terms, and three outputs. A dot at the intersection of a word line
and an input or output line indicates the presence of a switching element in the array.

PLA structure
 PLA table represents a general product term. Therefore, zero, one, or more rows
may be selected by each combination of input values.

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 Both mask-programmable and field-programmable PLAs are available.
 The mask-programmable type is programmed at the time of manufacture in a manner
similar to mask-programmable ROMs.
 The field-programmable logic array (FPLA) has programmable interconnection points
that use electronic charges to store a pattern in the AND and OR arrays.
 An FPLA with 16 inputs, 48 product terms, and eight outputs can be programmed to
implement eight functions of 16 variables, provided that the total number of product
terms does not exceed 48.
 When the number of input variables is small, a PROM may be more economical to use
than a PLA.

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 However, when the number of input variables is large, PLAs often provide a more
economical solution than PROMs.
 For example, to realize eight functions of 24 variables would require a PROM
with over 16 million 8-bit words. Because PROMs of this size are not readily
available, the functions would have to be decomposed so that they could be
realized using a number of smaller PROMs. The same eight functions of 24
variables could easily be realized using a single PLA, provided that the total
number of product terms is small. If more terms are required, the outputs of
several PLAs can be ORed together.
Question:

Realize F1 and F2 using a PLA. Give the PLA table and internal connection
diagram for the PLA.

F1(a, b, c, d) = m(1, 2, 4, 5, 6, 8, 10, 12, 14)

F2(a, b, c, d) = m(2, 4, 6, 8, 10, 11, 12, 14, 15)

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 Programmable Array Logic
The PAL (programmable array logic) is a special case of the programmable logic
array in which the AND array is programmable and the OR array is fixed. The basic
structure of the PAL is the same as the PLA shown in Figure 9-24. Because only the
AND array is programmable, the PAL is less expensive than the more general PLA,
and the PAL is easier to program. For this reason, logic designers frequently use
PALs to replace individual logic gates when several logic functions must be
realized.
Let us consider of realizing the function I1 I2 + I1 I2.

The X’s in Figure indicate that I1 and I2 lines are connected to the first AND gate, and
the I1 and I2 lines are connected to the other gate.

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 PAL segment
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 When designing with PALs, we must simplify the logic equations and try to fit them into
one (or more) of the available PALs.

 Unlike the more general PLA, the AND terms cannot be shared among two or more OR
gates; therefore, each function to be realized can be simplified by itself without regard
to common terms.

 For a given type of PAL, the number of AND terms that feed each output OR gate is
fixed and limited.

 If the number of AND terms in a simplified function is too large, we may be forced to
choose a PAL with more gate inputs and fewer outputs.
As an example of programming a PAL, let us implement a full adder. The logic equations for
the full adder are

Sum = X Y Cin + X Y Cin + X Y Cin + X Y Cin

Cout = X Cin + Y Cin + X Y

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 Implementation of a Full Adder Using a
PAL
Question:

Show how to implement a full subtracter using a

PAL
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 Field-Programmable Gate Arrays

 An FPGA is an IC that contains an array of identical logic cells with programmable

interconnections. The user can program the functions realized by each logic cell
and the connections between the cells.

 The interior of the FPGA consists of an array of logic cells, also called configurable
logic blocks (CLBs).

 The array of CLBs is surrounded by a ring of input-output interface blocks.

 These I/O blocks connect the CLB signals to IC pins.

 The space between the CLBs is used to route connections between the CLB
outputs and inputs.

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 Fig1 Layout of a Typical FPGA

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 Figure 2 shows a simplified version of a CLB.

Simplified Configurable Logic Block (CLB)

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 This CLB contains two function generators, two flip-flops, and various
multiplexers for routing signals within the CLB.
 Each function generator has four inputs and can implement any function of up
to four variables. The function generators are implemented as lookup tables
(LUTs).
 A four input LUT is essentially a reprogrammable ROM with 16 1-bit words. This
ROM stores the truth table for the function being generated.
 The H multiplexer selects either F or G depending on the value of H.
 The CLB has two combinational outputs (X and Y) and two flip-flop outputs (XQ
and YQ).The X and Y outputs and the flipflop inputs are selected by
programmable multiplexers.
 The select inputs to these MUXes are programmed when the FPGA is
configured.
 For example, the X output can come from the F function generator, and the Y
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Figure 3 shows one way to implement a function generator with inputs a, b, c, d. The
numbers in the squares represent the bits stored in the LUT. These bits enable
particular minterms. Because the function being implemented is stored as a truth table,
a function with only one minterm or with as many as 15 minterms requires a single
function generator. The functions

F = abc
and

F = a’b’c’d + a’b’cd + a’bc’d + ab’c’d + ab’cd’ + ab’cd ‘+ abc’d’ + abcd

each require a single function generator.

Implementation of
a Lookup Table
(LUT)

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Decomposition of Switching Functions
In order to implement a switching function of more than four variables using 4- variable
function generators, the function must be decomposed into subfunctions where each
subfunction requires only four variables. One method of decomposition is based on
Shannon’s expansion theorem. We will first illustrate this theorem by expanding a function of
the variables a, b, c, and d about the variable a:

f (a, b, c, d) = a’f (0, b, c, d) + a f (1, b, c, d) = a’ f0 + a f1

The 3-variable function f0 = f(0, b, c, d) is formed by replacing a with 0 in f(a, b, c, d), and f1=
f (1, b, c, d) is formed by replacing a with 1 in f (a, b, c, d). To verify that the above Equation
is correct, first set a to 0 on both sides, and then set a to 1 on both sides. An example of
applying this Equation is as follows:

Note that before simplification, the terms c’d’ and bcd appear in both f0 and f1 because
neither term contains a’ or a.
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Expansion can also be accomplished using a truth table or a Karnaugh map. The left
half of the map where a = 0 is in effect a 3-variable map for f0(b, c, d). Looping terms

on the left half gives f0 = c’d’ + b’c + cd, which is the same as the previous result.

Similarly the right half where a =1 is a 3-variable map for f1(b, c, d), and looping terms

on the right half gives f1 = c’ + bd.

Function Expansion Using a Karnaugh Map

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The general form of Shannon’s expansion theorem for expanding an n-variable function
about the variable xi is

f (x1, x2, . . . , xi-1, xi, xi+1, . . . , xn)

= xi‘f (x1, x2, . . . , xi-1, 0, xi+1, . . . , xn) + xi f (x1, x2, . . . , xi-1, 1, xi+1, . . . , xn)

= x i’ f 0 + x i f 1

where f0 is the (n-1)-variable function obtained by setting xi to 0 in the original function and f1 is

the (n-1)-variable function obtained by setting xi to 1 in the original function. The theorem is

easily proved for switching algebra by first setting xi.

Applying the expansion theorem to a 5-variable function gives

f (a, b, c, d, e) = a’ f (0, b, c, d, e) + a f (1, b, c, d, e) = a’ f0 + a f1

This shows that any 5-variable function can be realized using two 4-variable function generators
and a 2-to-1 MUX (fig a). This implies that any 5-variable function can be implemented using a
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To realize a 6-variable function using 4-variable function generators, we apply the expansion
theorem twice:

G(a, b, c, d, e, f ) = a’ G(0, b, c, d, e, f ) + a G(1, b, c, d, e, f ) = a’ G0 + a G1

G0 = b’G(0, 0, c, d, e, f ) + b G(0, 1, c, d, e, f ) = b’G00 + b G01

G1 = b’G(1, 0, c, d, e, f ) + b G(1, 1, c, d, e, f ) = b’G10 + bG11

BecauseG00,G01,G10, and G11 are all 4-variable functions, we can realize any 6-variable function
using four 4-variable function generators and three 2-to-1 MUXes, as shown in fig b. Thus, we
can realize any 6-variable function using two CLBs. Alternatively, we can write and realize G
using four function generators and a 4-to-1 MUX. In general, we can realize any n-variable
function (n > 4) using 2n-4 4-variable function generators and one 2n-4-to-1 MUX.

G(a, b, c, d, e, f ) = a’ b’ G00 + a’ bG01 + ab’G10 + ab G11

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 Realization of 5- and 6-Variable Functions with Function
Generators
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 Thank You

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