CS220 Computer Architecture

Digital Logic Design

Revision Exercises
Be familiar with Boolean algebra theorems for manipulating expressions
into desired forms

Understand how to draw and plot K-Maps for functions with different
numbers of input variables, how to label the axes using Gray code

Understand the terms implicant, prime implicant and essential prime

implicant and how to apply the minimisation process to obtain a minimal
sum of products expression for a function
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Digital Logic Design

In Today’s Class
Converting sum of products to NAND only form

The binary number system

Focus on representing numbers, positive, negative and

fractions in binary, later floating point

The definition of arithmetic functions

Circuits for doing arithmetic – The Adder and Subtractor

 CS220 Computer Architecture
Digital Logic Design

How to convert Sums-of-Products to NAND

When an expression is in two-level sum of
products form it is possible to implement a NAND
form directly (without redesign) provided there is
no limitation to the number of inputs to the gates
being used.

A two-level sum of products implementation

results in the shortest critical path and therefore
the fastest possible circuit.
CS220 Computer Architecture
Digital Logic Design
CS220 Computer Architecture
Digital Logic Design
CS220 Computer Architecture
Digital Logic Design
CS220 Computer Architecture
Digital Logic Design
 CS220 Computer Architecture
Digital Logic Design

Representation of Data - Number Systems

The Decimal numeral system uses 10 symbols, 0,1,2,…,9 with
positional notation. The position of a symbol in the number
determines its magnitude.

The Base or Radix of a number system is the number of different

symbols that can occur at each position in a number. The
decimal number system has a base 10.

Positional notation allows simpler arithmetic. Arithmetic is quite

difficult using other notations such as Roman Numerals.
e.g. MMXIV + MCMLXXXIII
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Digital Logic Design

Binary System
Computer Circuits are composed of transistor devices and to
allow them to deal efficiently with numbers and other data, the
binary system is used to represent data values.

The Binary numeral system uses 2 symbols, 0 and 1 with

positional notation. Each position represents a power of 2 rather
than a power of 10.
 CS220 Computer Architecture
Digital Logic Design

Binary System

In Decimal 24610 = 2x100 + 4x10 + 6x1

In Binary 11012 = 1x8 + 1x4 + 0x2 + 1x1 = 1310

 CS220 Computer Architecture
Digital Logic Design

Binary System

Note that fractions can be formed in the same general way:-

11.0112 = 1x21 + 1x20 + 0x2-1 + 1x2-2 + 1x2-3

=2 +1 +0 +0.25 + 0.125
= 3.37510
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Digital Logic Design

Binary Addition and Subtraction

Addition Definition

0 + 0 = 0 sum
0 + 1 = 1 sum
1 + 0 = 1 sum
1 + 1 = 0 sum with a carry over of 1, i.e. 10
 CS220 Computer Architecture
Digital Logic Design

Binary Addition and Subtraction

Addition Examples

Note that the sum can be one digit longer than either operand.
 CS220 Computer Architecture
Digital Logic Design

Binary Addition and Subtraction

Subtraction Definition

0 - 0 = 0 Difference
1 - 0 = 1 Difference
1 - 1 = 0 Difference
0 - 1 = 1 Difference with a Borrow of 1
 CS220 Computer Architecture
Digital Logic Design

Binary Addition and Subtraction

Subtraction Examples
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Digital Logic Design

Binary Multiplication and Division

Multiplication Definition
0 x 0 = 0 Product
0 x 1 = 0 Product
1 x 0 = 0 Product
1 x 1 = 1 Product
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Digital Logic Design

Binary Multiplication and Division

Multiplication Examples

Note that in binary multiplication, the product may require

double the number of bits of the operands.
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Digital Logic Design

Binary Multiplication and Division

Division Definition
0  0 is not a number
0  1 is 0 Quotient
1  0 is not a number
1  1 is 1 Quotient
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Digital Logic Design

Binary Multiplication and Division

Division Examples
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Digital Logic Design

Converting Decimal Numbers to Binary

Repeated Division by 2
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Digital Logic Design

Converting Decimal Numbers to Binary

Subtraction of powers of 2
What is 148 in binary?

148 -128 = 20
20 - 16 = 4
4-4=0

148 = 128 + 16 + 4
= 27 + 24 + 22
= 100101002
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Digital Logic Design

Converting Decimal Fractions to Binary

Separate the number into its whole part and fractional part.
 CS220 Computer Architecture
Digital Logic Design

Representing Negative Numbers

An integer is a whole number (with no fractional part).
It can be positive, negative or zero.

An unsigned integer is just a magnitude, either positive or zero.

The n bits used to store the number represent its magnitude in the range
0..2n-1. For example, using an 8-bit binary representation we would be able to
express a magnitude range from 0 to 255.

A signed integer encodes the sign of a number along with its magnitude
giving a range of negative and positive numbers which can be encoded
-2n-1 .. +2n-1 -1.
For example, using an 8-bit binary representation we would be able to
express a range from -128 .. +127, so for the same number of bits, the
maximum magnitude is halved.
 CS220 Computer Architecture
Digital Logic Design

Representing Negative Numbers

One way of encoding the sign and magnitude is to use one bit
position (say the highest bit) to represent the sign of a number
and the rest of the bits to represent the magnitude.

For example, use leading value of 0 to represent a positive

number and 1 to represent a negative number.

The sign bit is treated separately from the magnitude bits by the
arithmetic hardware.
 CS220 Computer Architecture
Digital Logic Design

Representing Negative Numbers

Example of Signed Magnitude Form

1 0 0 0 1 1 0 02 = -1210

0 0 0 1 0 1 1 02 = +2210
 CS220 Computer Architecture
Digital Logic Design

Representing Negative Numbers

Example of Signed Magnitude Form

1 0 0 0 1 1 0 02 = -1210

0 0 0 1 0 1 1 02 = +2210

To perform arithmetic using this representation for numeric data

would require separate adder and subtractor circuits.
By using a different technique to represent negative numbers it
is possible to construct a circuit which can add and subtract
using only addition.
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Digital Logic Design

Representing Negative Numbers

Consider the following example in the Decimal system:-
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Digital Logic Design

Representing Negative Numbers

In Binary, using 4 digit numbers:-
 CS220 Computer Architecture
Digital Logic Design

Representing Negative Numbers

The two's complement of a number is more easily calculated by
complementing all the bits and adding 1 to the result.
 CS220 Computer Architecture
Digital Logic Design

Integers in 2’s Complement Form

Using 4-bit binary numbers

in 2’s complement form, we can
represent integers in the range
-7 to +7 as follows:-

To get 2’s complement, we invert

the binary digits and add 1
 CS220 Computer Architecture
Digital Logic Design

Hexadecimal Notation
Sometimes hexadecimal notation provides a convenient way of
representing large data values as it is easy to translate values to
binary and is less unwieldy.

The hexadecimal number system has base 16 with symbols 0,1,2,

…,9,A,B,C,D,E,F and uses positional notation.

Large binary numbers can be represented easily in hexadecimal,

for example:-
1011110101110110 = BC76 in hexadecimal.
Each hexadecimal symbol represents 4 binary digits.
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Digital Logic Design

Hexadecimal Notation
The following table gives the binary, decimal and hexadecimal
representation for different numbers.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Unit

The component of the processor that performs all the integer

processing operations such as addition, subtraction,
multiplication, division, bit shifting, and various boolean logic
operations is known as the Arithmetic and Logic Unit (ALU).

In this section we look at how addition and subtraction

operations can be carried out using an adder circuit that might
form part of the ALU resources.
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Digital Logic Design

Arithmetic and Logic Operations

The table below defines the basic operation of the 1-bit half
adder circuit for adding two binary digits.
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Digital Logic Design

Arithmetic and Logic Operations

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Digital Logic Design

Arithmetic and Logic Operations

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Digital Logic Design

Arithmetic and Logic Operations

Note that if there are several digits in the operands, the half
adder cannot account for carry-ins from lower bit positions.

For example, in the case of the following sum

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

A full adder circuit is capable of adding two 1-bit operands and a
carry in from a previous bit position.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

A full adder can be constructed from two half-adders as follows:-

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Question: What is the propagation delay of the full adder circuit,

if each gate has a propagation delay of 10nsec?

How many gates are needed in total?

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

The longest path from inputs to outputs is in the calculation of
the Full Sum. This requires 3 gate delays in each half adder, so
the Full Sum becomes available after 60nsec. The Full Carry
becomes available after 50nsec. The maximum propagation
delay of the circuit is 60nsec. The design involves 13 gates.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Exercise: Design a 1-bit full adder circuit using only five 2-input
gates. The gates used may be of any type including XOR, AND,
OR, NOT.

Hint Note: AB+C(A+B) = AB+C(AB)

What is the propagation delay of the circuit and how does it

compare to the 1-bit adder circuit created earlier by the
composition of two half-adder circuits?
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Ripple Carry Adder
An adder circuit for adding two words of arbitrary length can be
constructed from a number of full adder circuits.
Example: 4-bit Addition of A and B
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Adder/Subtractor Circuit

Two's complement arithmetic can be used to construct an

adder/subtractor unit based on the ripple carry adder circuit.

Recall that the two's complement is obtained by complementing

each bit and adding 1 to the result.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

Using 4-bit binary numbers

in 2’s complement form, we can
represent integers in the range
-7 to +7 as follows:-

To get 2’s complement, we invert

the binary digits and add 1
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Digital Logic Design

Arithmetic and Logic Operations

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations A+B

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Digital Logic Design

Arithmetic and Logic Operations A-B

 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

This adder/subtractor design still suffers from the ripple carry
effect, incurring long carry propagation delays for longer
numbers.

The delay generated by an n-bit adder is proportional to the

length n of the two numbers A and B that are added because
each 1-bit full adder component cannot calculate its output until
the carry from the previous bit position has propagated through.
 CS220 Computer Architecture
Digital Logic Design

Arithmetic and Logic Operations

For large values of n, the delay becomes unacceptably large. In
our adder design, each bit position takes about three gate delays
to produce each carry so in the case of adding, for example, two
32-bit numbers we are looking at a long propagation delay of
about 96 gate delays before the adder computes the total sum of
the numbers.

While the sum value for each bit position can be calculated in
parallel, we need an accelerated way of generating the carry to
overcome the serial performance limitations of the ripple carry
design.