|| Jai Sri Gurudev ||

Sri Adichunchanagiri Shikshana Trust (R)

SJB Institute of Technology

Department of Electronics & Communication Engineering

Advanced VLSI – 21EC71

Module-2
Floor planning, Placement and routing
By
Mrs. S Nithya
Assistant Professor
Dept of ECE, SJBIT
Module-2
Floor planning and placement: Goals and objectives, Measurement of delay in
Floor planning, Floor planning tools, Channel definition, I/O and Power planning
and Clock planning. Placement: Goals and Objectives, Min-cut Placement
algorithm, Iterative Placement Improvement, Time driven placement methods,
Physical Design Flow. Routing: Global Routing: Goals and objectives, Global
Routing Methods, Global routing between blocks, Back annotation. Text Book 1

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 Introduction

• The input to the floor planning step is the output of system

partitioning and design entry a netlist.
• Floor planning precedes placement. The output of the
placement step is a set of directions for the routing tools.
• Floor planning allows to predict the interconnection delay by
estimating interconnect length. this interconnect delay and gate
delay decreased by scale down feature size.

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 Goals & Objectives

• The goals of floorplanning are to:

1.arrange the blocks on a chip,
2. decide the location of the I/O pads,
3. decide the location and number of the power pads,
4. decide the type of power distribution, and
5.decide the location and type of clock distribution.
• Objectives
1.To minimize the chip area and minimize delay

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 Measurement of Delay in
Floor planning
• Throughout the ASIC design process we need to predict the performance of the final
layout. In floor planning we wish to predict the interconnect delay before routing.
• To predict delay we need to know the parasitics associated with interconnect: the
interconnect capacitance ( wiring capacitance or routing capacitance ) as well as the
interconnect resistance.
• At the floorplanning stage we know only the fanout ( FO ) of a net (the number of
gates driven by a net) and the size of the block that the net belongs to.
• We cannot predict the resistance of the various pieces of the interconnect path
since we do not yet know the shape of the interconnect for a net.
• we can estimate the total length of the interconnect and thus estimate the total
capacitance. we create tables that predict the interconnect capacitance as a function
of net fanout and block size. A
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Floorplanning Tools

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• Figure (a) shows an initial random floorplan generated by a floorplanning tool.
Two of the blocks, A and C in this example, are standard-cell areas.
• These are flexible blocks (or variable blocks ) because, although their total
area is fixed, their shape (aspect ratio) and connector locations may be
adjusted during the placement step.
• The dimensions and connector locations of the other fixed blocks (perhaps
RAM, ROM, compiled cells, or megacells) can only be modified when they are
created.
• We may force logic cells to be in selected flexible blocks by seeding . We
choose seed cells by name.

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• Seeding may be hard or soft.
• A hard seed is fixed and not allowed to move during the remaining
floorplanning and placement steps.
• A soft seed is an initial suggestion only and can be altered if
necessary by the floorplanner. We may also use seed connectors
within flexible blocks.
• use seed connectors within flexible blocksforcing certain nets to
appear in a specified order, or location at the boundary of a flexible
block.
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• The floorplanner can complete an estimated placement to determine
the positions of connectors at the boundaries of the flexible blocks.
• Figure (b) illustrates a rat's nest display of the connections between
blocks. Connections are shown as bundles between the centers of
blocks or as flight lines between connectors.
• Figure (c) and (d) show how we can move the blocks in a
floorplanning tool to minimize routing congestion .
• We need to control the aspect ratio of our floorplan because we
have to fit our chip into the die cavity (a fixed-size hole, usually
square) inside a package.
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Dept. of ECE, SJBIT 10
• Figure (a)(c) show how we can rearrange our chip to achieve a square
aspect ratio. Figure (c) also shows a congestion map , another form of
routability display.
• There is no standard measure of routability. Generally the interconnect
channels , have a certain channel capacity ;that is, they can handle only
a fixed number of interconnects.
• One measure of congestion is the difference between the number of
interconnects that we actually need, called the channel density , and the
channel capacity.
• Another measure uses the ratio of channel density to the channel
capacity. Dept. of ECE, SJBIT 11
Channel Definition
• During the floorplanning step we assign the areas between blocks
that are to be used for interconnect. This process is known as
channel definition or channel allocation .
• Figure shows a T-shaped junction between two rectangular
channels The general problem of choosing the order of rectangular
channels to route is channel ordering .
• Slicing Floorplan

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Dept. of ECE, SJBIT 13
FIGURE : Defining the channel routing order for a slicing floorplan using a
slicing tree
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Dept. of ECE, SJBIT 15
• We say there is a cyclic constraint in this floorplan. There are two
solutions to this problem.
• One solution is to move the blocks until we obtain a slicing
floorplan.
• The other solution is to allow the use of L -shaped, rather than
rectangular, channels We need an area-based router rather than a
channel router to route L -shaped regions or switch boxes

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Dept. of ECE, SJBIT 17
• Figure(a) displays the floorplan of the ASIC shown in Figure . We can
remove the cyclic constraint by moving the blocks again, but this
increases the chip size. Figure (b) shows an alternative solution.
• We merge the flexible standard cell areas A and C. We can do this by
selective flattening of the netlist.
• Sometimes flattening can reduce the routing area because routing
between blocks is usually less efficient than routing inside the row-
based blocks. Figure (b) shows the channel definition and routing
order for our chip.
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 I/O and Power Planning
• Every chip communicates with the outside world. Signals flow onto and
off the chip and we need to supply power. We need to consider the I/O
and power constraints early in the floorplanning process.
• A silicon chip or die is mounted on a chip carrier inside a chip package .
A die consists of a logic core inside a pad ring.
• Figure (a) shows a pad-limited die and Figure (b) shows a core-limited
die. On a pad-limited die we use tall, thin pad-limited pads , which
maximize the number of pads we can fit around the outside of the
chip. On a core-limited die we use short, wide core-limited pads .
Figure (c) shows how we can use both types of pad to change the
aspect ratio of a die to be different from that of the core.
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FIGURE 16.12 Pad-limited and core-limited die. (a) A pad-limited die. The number of pads determines
the die size. (b) A core-limited die: The core logic determines the die size. (c) Using both pad-limited
pads and core-limited pads for a square die.

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• Special power pads are used for the positive supply, or VDD, power
buses (or power rails ) and the ground or negative supply, VSS or
GND.
• one set of VDD/VSS pads supplies one power ring that runs around
the pad ring and supplies power to the I/O pads only. Another set of
VDD/VSS pads connects to a second power ring that supplies the
logic core.
• I/O pads also contain special circuits to protect against electrostatic
discharge (ESD). These circuits can withstand very short high-voltage
(several kilovolt) pulses that can be generated during human or
machine handling. Dept. of ECE, SJBIT 21
• Depending on the type of package the silicon die to the chip cavity
in the chip carrier, there may be an electrical connection between
the chip carrier and the die substrate.
• A double bond connects two pads to one chip-carrier finger and
one package pin. We can do this to save package pins or reduce the
series inductance of bond wires by parallel connection of the pads.
• common example is a clock pad . Some foundries allow a special
form of corner pad that squeezes two pads into the area at the
corners of a chip using a special two-pad corner cell , to help meet
bond-wire angle design rules
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• To reduce the series resistive and inductive impedance of power
supply networks, it is normal to use multiple VDD and VSS pads.
• This is particularly important with the simultaneously switching
outputs(SSOs) that occur when driving buses off-chip.
• The output pads can easily consume most of the power on a
CMOS ASIC, because the load on a pad is much larger than
typical on-chip capacitive loads. Depending on the technology it
may be necessary to provide dedicated VDD and VSS pads for every
few SSOs.

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 FIGURE 16.13 Bonding pads. (a)
This chip uses both pad-limited
and core-limited pads. (b) A
hybrid corner pad. (c) A chip
with stagger-bonded pads.
(d) An area-bump bonded chip
(or flip-chip). The chip is turned
upside down and solder bumps
connect the pads to the lead
frame.

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 Clock Planning
• Integrated circuit has many blocks, we should have a clock signal as
a input. To feed clock signal, we need a clock distribution network.
• Clock distribution network must have minimum skew and buffers
are used to amplifies the degraded clock signal.
• Figure (a) shows a clock spine (not to be confused with a channel
spine) routing scheme with all clock pins driven directly from the
clock driver. MGAs and FPGAs often use this fish bone type of clock
distribution scheme. Figure (b) shows a clock spine for a cell-based
ASIC. Figure (c) shows the clock-driver cell, often part of a special
clock-pad cell. Figure (d) illustrates clock skew and clock latency .
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Dept. of ECE, SJBIT 26
• Figure (c) illustrates the construction of a clock-driver cell. The delay through
a chain of CMOS gates is minimized when the ratio between the input
capacitance C 1 and the output (load) capacitance C 2.
• Suppose we have an ASIC with the following specifications:
– 40,000 flip-flops
– Input capacitance of the clock input to each flip-flop is 0.025 pF
– Clock frequency is 200 MHz
– V DD = 3.3 V
– Chip size is 20 mm on a side
– Clock spine consists of 200 lines across the chip
– Interconnect capacitance is 2 pFcm 1
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Dept. of ECE, SJBIT 28
FIGURE 16.17 A clock tree. (a) Minimum delay is achieved when the taper of successive stages is about 3. (b) Using a
fanout of three at successive nodes. (c) A clock tree for the cell-based ASIC of Figure 16.16 b. We have to balance
the clock arrival times at all of the leaf nodes to minimize clock skew. Designing a

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