NATIONAL ECONOMICS UNIVERSITY

SCHOOL OF INFORMATION TECHNOLOGY AND DIGITAL ECONOMICS

CHAPTER 3
MAIN MEMORY

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OUTLINE

 Background
 Swapping
 Contiguous Memory Allocation
 Segmentation
 Paging
 Structure of the Page Table
 Example: The Intel 32 and 64-bit Architectures
 Example: ARM Architecture
OBJECTIVES

 To provide a detailed description of various ways of organizing

memory hardware
 To discuss various memory-management techniques, including
paging and segmentation
 To provide a detailed description of the Intel Pentium, which supports
both pure segmentation and segmentation with paging

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BACKGROUND

 Program must be brought (from disk) into memory and placed within
a process for it to be run
 Main memory and registers are only storage CPU can access directly
 If the data are not in memory, they must be moved there before the
CPU can operate on them.
 Register access in one CPU clock (or less)
 Main memory can take many cycles, causing a stall
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation
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MEMORY HIERARCHY

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APPLICATION MEMORY

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MEMORY ALLOCATION TO A PROCESS

 Stacks:
 Allocations and deallocations are performed in a LIFO manner.
 Only the last entry of the stack is accessible at any time
 A contiguous area of memory is reserved for the stack
 Stack is used to support function calls.

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MEMORY ALLOCATION TO A PROCESS

 Heap permits allocation and deallocation of memory in a random

order

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BASE AND LIMIT REGISTERS

 A pair of base and limit registers define the logical address space
 CPU must check every memory access generated in user mode to be
sure it is between base and limit for that user

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HARDWARE ADDRESS PROTECTION

 The base and limit registers can be loaded only by the operating
system, which uses a special privileged instruction.

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LOGICAL VS. PHYSICAL ADDRESS SPACE

 The concept of a logical address space that is bound to a

separate physical address space is central to proper
memory management
 Logical address – generated by the CPU; also referred to as
virtual address
 Physical address – address seen by the memory unit
 Logical address space is the set of all logical addresses
generated by a program
 Physical address space is the set of all physical
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addresses generated by a program
MEMORY-MANAGEMENT UNIT (MMU)

 Hardware device that at run time maps virtual to physical address

 Many methods possible, covered in the rest of this chapter
 To start, consider simple scheme where the value in the relocation
register is added to every address generated by a user process at
the time it is sent to memory
 Base register now called relocation register

 The user program deals; with logical addresses it never sees the real
physical addresses
 Execution-time binding occurs when reference is made to location in memory
 Logical addresses must be mapped to physical addresses before they are used
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DYNAMIC RELOCATION USING A RELOCATION REGISTER

 The value in the relocation register is added to every address

generated by a user process at the time the address is sent to
memory

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DYNAMIC RELOCATION USING A RELOCATION REGISTER

 Routine is not loaded until it is called

 Better memory-space utilization; unused routine is never loaded
 All routines kept on disk in relocatable load format
 Useful when large amounts of code are needed to handle
infrequently occurring cases
 No special support from the operating system is required
 Implemented through program design
 OS can help by providing libraries to implement dynamic loading

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DYNAMIC LINKING

 Static linking – system libraries and program code combined by the loader into the binary
program image
 Dynamic linking – linking postponed until execution time

 Small piece of code, stub, used to locate the appropriate memory-resident library routine

 Stub replaces itself with the address of the routine, and executes the routine

 Operating system checks if routine is in processes’ memory address

 If not in address space, add to address space

 Dynamic linking is particularly useful for libraries

 System also known as shared libraries

 Consider applicability to patching system libraries

 Versioning may be needed
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DYNAMIC LINKING VS STATIC LINKING

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SWAPPING

 A process can be swapped temporarily out of memory to a backing store, and

then brought back into memory for continued execution
 Total physical memory space of processes can exceed physical memory
 Backing store – fast disk large enough to accommodate copies of all memory
images for all users; must provide direct access to these memory images
 Swap out, Swap in – swapping variant used for priority-based scheduling
algorithms; lower-priority process is swapped out so higher-priority process can be
loaded and executed
 The system maintains a ready queue consisting of all processes whose memory
images are on the backing store or in memory
 Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
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SWAPPING

 Swapping of two processes using a disk as a backing store.

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CONTEXT SWITCH TIME INCLUDING SWAPPING

 If next processes to be put on CPU is not in memory, need to swap out a process
and swap in target process
 Context switch time can then be very high
 100MB process swapping to hard disk with transfer rate of 50MB/sec
 Swap out time of 2 seconds

 Plus swap in of same sized process => 4 seconds

 Total context switch swapping component time of 4000ms (4 seconds)

 Can reduce if reduce size of memory swapped – by knowing how much memory
really being used
 System calls to inform OS of memory use via request_memory() and release_memory()
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SWAPPING ON MOBILE SYSTEMS

 Not typically supported

 Flash memory based
 Small amount of space
 Limited number of write cycles
 Poor throughput between flash memory and CPU on mobile platform

 Instead use other methods to free memory if low

 iOS asks apps to voluntarily relinquish allocated memory
 Read-only data thrown out and reloaded from flash if needed. Data that have been modified (such
as the stack) are never removed
 Failure to free can result in termination
 Android terminates apps if low free memory, but first writes application state to flash for fast
restart
 Both OSes support paging as discussed below 20
CONTIGUOUS ALLOCATION

 Main memory must support both OS and user processes

 Limited resource, must allocate efficiently
 Contiguous allocation is one early method
 Main memory usually into two partitions:
 Resident operating system, usually held in low memory with interrupt vector
 User processes then held in high memory

 Each process contained in single contiguous section of memory

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HARDWARE SUPPORT FOR RELOCATION AND LIMIT
REGISTERS

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CONTIGUOUS ALLOCATION (CONT.)

 Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
 Base register contains value of smallest physical address
 Limit register contains range of logical addresses – each logical address must be less than
the limit register
 MMU maps logical address dynamically
 If a device driver (or other operating-system service) is not commonly used, we do not
want to keep the code and data in memory, as we might be able to use that space for
other purposes. Such code is sometimes called transient operating-system code;

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MEMORY ALLOCATION

 One of the simplest methods for allocating

memory is to divide memory into several
fixed-sized partitions
 Degree of multiprogramming limited by number of
partitions
 When a partition is free, a process is selected
from the input queue and is loaded into the free
partition.
 When the process terminates, the partition
becomes available for another process.
 This method was originally used by the IBM
OS/360 operating system (called MFT) but is no
longer in use. 24
MEMORY ALLOCATION (CONT)

 In the variable-partition scheme, the operating system keeps a table

indicating which parts of memory are available and which are
occupied.
 Initially, all memory is available for user processes and is considered
one large block of available memory, a hole. Eventually, memory
contains a set of holes of various sizes.
 When a process arrives, it is allocated memory (hole) enough to
accommodate it
 When a process terminates, it releases its memory, which the
operating system may then fill with another process from the input
queue. 25
MULTIPLE-PARTITION ALLOCATION

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TWO WAYS TO TRACK MEMORY USAGE

 Bit map vs Linked list

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DYNAMIC STORAGE-ALLOCATION

 How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough
 Best-fit: Allocate the smallest hole that is big enough; must search entire list,
unless ordered by size
 Produces the smallest leftover hole
 Worst-fit: Allocate the largest hole; must also search entire list
 Produces the largest leftover hole

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DYNAMIC STORAGE-ALLOCATION

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FRAGMENTATION

 External Fragmentation – total memory space exists to satisfy a

request, but it is not contiguous
 Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used
 First fit analysis reveals that given N blocks allocated, 0.5 N blocks
lost to fragmentation
 1/3 may be unusable -> 50-percent rule

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FRAGMENTATION

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COMPACTION

 Reduce external fragmentation by compaction

 Shuffle memory contents to place all free memory together in one large block
 Compaction is possible only if relocation is dynamic
 I/O problem:
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers

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SEGMENTATION

 A program is a collection of segments. A segment is a logical unit such as:

 main program
 procedure
 function
 method
 object
 variables
 common block
 stack
 arrays
 ...
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USER’S VIEW OF A PROGRAM

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LOGICAL VIEW OF SEGMENTATION

4
1

3 2
4

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user space physical memory space
SEGMENTATION ARCHITECTURE

 Logical address consists of a two tuple:

<segment-number, offset>,
 Segment table – maps two-dimensional physical addresses; each table entry has:
 base – contains the starting physical address where the segments reside in memory
 limit – specifies the length of the segment
 Segment-table base register (STBR) points to the segment table’s location in
memory
 Segment-table length register (STLR) indicates number of segments used by a
program;
segment number s is legal if s < STLR

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SEGMENTATION HARDWARE

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EXAMPLE OF SEGMENTATION.

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OUTLINE

 Background
 Swapping
 Contiguous Memory Allocation
 Segmentation
 Paging
 Structure of the Page Table
 Example: The Intel 32 and 64-bit Architectures
 Example: ARM Architecture

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PAGING

 Physical address space of a process can be noncontiguous; process is allocated physical memory
whenever the latter is available
 Avoids external fragmentation
 Avoids problem of varying sized memory chunks
 Divide physical memory into fixed-sized blocks called frames
 Size is power of 2, between 512 bytes and 1Gb
 Divide logical memory into blocks of same size called pages
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and load program
 Set up a page table to translate logical to physical addresses
 Backing store likewise split into pages
 Still have Internal fragmentation

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ADDRESS TRANSLATION SCHEME

 Address generated by CPU is divided into:

 Page number(p) – used as an index into a page table which contains base
address of each page in physical memory
 Page offset(d) – combined with base address to define the physical memory
address that is sent to the memory unit
page number page offset
p d
m -n n

 For given logical address space 2m and page size 2n

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PAGING HARDWARE

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PAGING MODEL OF LOGICAL AND PHYSICAL MEMORY

 In the logical address, n=2 and

m=4,
=> page size: 22 = 4 bytes, logical
address space = 24 = 16 bytes

 Physical memory of 32 bytes (8

page)

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PAGING EXAMPLE

 Logical address 0 is page 0, offset 0.

Indexing into the page table, we find that
page 0 is in frame 5. Thus, logical
address 0 maps to physical address 20
[= (5 x 4) + 0].
 Logical address 3 is page 0 offset 3.
Maps to physical address 23 [= (5 x 4) +
3].
 Logical address 4 is page 1, offset 0;
according to the page table, page 1 is
mapped to frame 6. 44
PAGING

 Calculating internal fragmentation

 Page size = 2,048 bytes
 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
 Process view and physical memory now very different
 By implementation process can only access its own memory

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OBTAINING THE PAGE SIZE ON UNIX SYSTEMS

 The page size varies according to architecture, and there are several
ways of obtaining the page size. One approach is to use the
getpagesize() system call.
 Another strategy is to enter the following command on the command
line:
getconf PAGESIZE
 Each of these techniques returns the page size as a number of bytes.

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FREE FRAMES

Before allocation After allocation

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IMPLEMENTATION OF PAGE TABLE

 Page tables are too large to be kept on the chip (Registers). Page
table is kept in main memory.
 Page-table base register (PTBR) points to the beginning of the
page table for this process
 In this scheme every data/instruction access requires two memory
accesses
 One for the page table and one for the data / instruction

 The two memory access problem can be solved by the use of a

special fast-lookup hardware cache called associative memory or
translation look-aside buffers (TLBs)
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IMPLEMENTATION OF PAGE TABLE (CONT.)

 TLBs typically small (64 to 1,024 entries)

 On a TLB miss, value is loaded into the TLB for faster access next
time
 Replacement policies must be considered. Ex: Least recently used (LRU),
 Some entries can be wired down for permanent fast access

P a ge # F ra m e #

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PAGING HARDWARE WITH TLB

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EFFECTIVE ACCESS TIME

 Associative Lookup < 10% of memory access time

 Hit ratio = 
 Hit ratio – percentage of times that a page number is found in the associative
registers; ratio related to number of associative registers
 Consider  = 80% 100ns for memory access
 Effective Access Time (EAT)
Consider  = 80%,  = 20ns for TLB search, 100ns for memory access
 EAT = 0.80 x 120 + 0.20 x 200 = ..ns
 Consider more realistic hit ratio ->  = 99%, 100ns for memory access
 EAT = 0.99 x 120 + 0.01 x 200 = 121ns
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MULTIPLE LEVELS OF TLBS

 CPUs today may provide multiple levels of TLBs. Calculating memory

access times in modern CPUs is therefore much more complicated
than shown in the example above.
 For instance, the Intel Core i7 CPU:
 Has a (128-entry L1 instruction TLB) and a 64-entry L1 data TLB. In the case of a
miss at L1, it takes the CPU six cycles to check for the entry in the L2 (512-
entry TLB).
 A miss in L2 means that the CPU must either walk through the page-table
entries in memory to find the associated frame address, which can take
hundreds of cycles

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MEMORY PROTECTION

 Memory protection implemented by associating protection bit with

each frame to indicate if read-only or read-write access is allowed
 Can also add more bits to indicate page execute-only, and so on

 Valid-invalid bit attached to each entry in the page table:

 “valid” indicates that the associated page is in the process’ logical address
space, and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical address space
 Or use page-table length register (PTLR)

 Any violations result in a trap to the kernel

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VALID (V) OR INVALID (I) BIT IN A PAGE TABLE

16,383 => (16Kb)

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SHARED PAGES

 Shared code
 One copy of read-only (reentrant) code shared among processes (i.e., text
editors, compilers, window systems)
 Similar to multiple threads sharing the same process space
 Also useful for interprocess communication if sharing of read-write pages is
allowed
 Private code and data
 Each process keeps a separate copy of the code and data
 The pages for the private code and data can appear anywhere in the logical
address space
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SHARED PAGES EXAMPLE

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STRUCTURE OF THE PAGE TABLE

 Memory structures for paging can get huge using straight-forward

methods
 Consider a 32-bit logical address space as on modern computers
 Page size of 4 KB (212)
 Page table would have 1 million entries (232 / 212)
 If each entry is 4 bytes, each process may need up tó 4 MB of physical address
space / memory for page table alone
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables
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HIERARCHICAL PAGE TABLES

 Break up the logical address space into multiple page tables

 A simple technique is a two-level page table
 We then page the page table

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TWO-LEVEL PAGE-TABLE SCHEME

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TWO-LEVEL PAGING EXAMPLE

 A logical address (on 32-bit machine with 1K page size) is divided into:
 a page number consisting of 22 bits
 a page offset consisting of 10 bits
 Since the page table is paged, the page number is further divided into:
 a 12-bit page number
 a 10-bit page offset
 Thus, a logical address is as follows:

 Where p is an index into the outer page table, and p is the displacement within the
1 2
page of the inner page table
 Known as forward-mapped page table 60
ADDRESS-TRANSLATION SCHEME

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THREE-LEVEL PAGING SCHEME

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VIRTUAL MEMORY

 Virtual memory is a technique that allows the execution of processes

that are not completely in memory
 One major advantage of this scheme is that programs can be larger
than physical memory.
 Further, virtual memory abstracts main memory into an extremely
large, uniform array of storage, separating logical memory as viewed
by the user from physical memory

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BACKGROUND

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DEMAND PAGING

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BASIC CONCEPTS

 When a process is to be
swapped in, the pager guesses
which pages will be used before
the process is swapped out
again.
 Instead of swapping in a whole
process, the pager brings only
those pages into memory.
 It avoids reading into memory
pages that will not be used
anyway, decreasing the swap 66
time and the amount of
STEPS IN HANDLING A PAGE FAULT

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PERFORMANCE OF DEMAND PAGING

 The effective access time:

effective access time = (1 − p) * ma + p * page fault time.
 ma ranges from 10 to 200 nanoseconds.
 page fault time takes ~ 8 milliseconds (A typical hard disk has an
average latency of 3 milliseconds, a seek of 5 milliseconds, and a
transfer time of 0.05 milliseconds)
effective access time = (1 − p) * (200) + p * (8 milliseconds)
= (1 − p) * 200 + p * 8,000,000
= 200 + 7,999,800 * p
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PAGE REPLACEMENT

1. Find the location of the desired page on

the disk
2. Find a free frame:
a. If there is a free frame, use it
b. If there is no free frame, use a page-replacement
algorithm to select a victim frame
c. Write the victim frame to the disk; change the page
and frame tables accordingly

3. Read the desired page into the newly freed

frame; change the page and frame tables
4. Continue the user process from where the
page fault occurred

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PAGE REPLACEMENT

 FIFO Page Replacement

 OPT Page Replacement
 LRU Page Replacement

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FIFO PAGE REPLACEMENT

 A FIFO replacement algorithm associates with each page the time

when that page was brought into memory.

Page fault=?

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OPT(OPTIMAL) PAGE REPLACEMENT

 Replace the page that will not be used for the longest period of time.

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LRU PAGE REPLACEMENT

 Least Recently Used (LRU) algorithm.

 When a page must be replaced, LRU chooses the page that has not
been used for the longest period of time.

 Most Frequency Used (MFU): The page with the smallest count was
probably just brought in and has yet to be used.
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