Serial Peripheral Interface (SPI)

• The Serial Peripheral Interface (SPI) allows high-speed

synchronous data transfer between the ATmega32 and peripheral
devices or between several AVR devices.

• The ATmega32 SPI includes the following features:

• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Double Speed (CK/2) Master SPI Mode
SPI Master-slave Interconnection
• The system consists of
– two Shift Registers
– a Master clock generator.

• The SPI Master initiates the communication cycle when pulling low
the Slave Select SS pin of the desired Slave.

• Master and Slave prepare the data to be sent in their respective

Shift Registers, and the Master generates the required clock pulses
on the SCK line to interchange data.

• Data is always shifted from Master to Slave on the Master Out –

Slave In, MOSI, line, and from Slave to Master on the Master In –
Slave Out, MISO, line.
• When configured as a Master, the SPI interface has no automatic
control of the SS line.

• This must be handled by user software before communication can

start.

• When this is done, writing a byte to the SPI Data Register starts the SPI
clock generator, and the hardware shifts the eight bits into the Slave.

• After shifting one byte, the SPI clock generator stops, setting the end
of Transmission Flag (SPIF).

• The Master may continue to shift the next byte by writing it into SPDR,
or signal the end of packet by pulling high the Slave Select, SS line.
• When configured as a Slave, the SPI interface will remain sleeping
with MISO tri-stated as long as the SS pin is driven high.

• In this state, software may update the contents of the SPI Data
Register, SPDR, but the data will not be shifted out by incoming
clock pulses on the SCK pin until the SS pin is driven low.

• As one byte has been completely shifted, the end of Transmission

Flag, SPIF is set.

• The Slave may continue to place new data to be sent into SPDR
before reading the incoming data. The last incoming byte will be
kept in the Buffer Register for later use.
• The system is single buffered in the transmit direction and double
buffered in the receive direction.

• This means that bytes to be transmitted cannot be written to the

SPI Data Register before the entire shift cycle is completed.

• When receiving data, however, a received character must be read

from the SPI Data Register before the next character has been
completely shifted in. Otherwise, the first byte is lost.

• In SPI Slave mode, the control logic will sample the incoming signal
of the SCK pin.

• To ensure correct sampling of the clock signal, the minimum low

and high periods should be:
• Low periods: longer than 2 CPU clock cycles.
• High periods: longer than 2 CPU clock cycles.
 SS Pin Functionality
• Slave Mode
– When the SPI is configured as a Slave, the Slave Select (SS) pin is always
input.

– When SS is held low, the SPI is activated, and MISO becomes an output if
configured so by the user. All other pins are inputs.

– When SS is driven high, all pins are inputs except MISO which can be user
configured as an output, and the SPI is passive, which means that it will not
receive incoming data.

– Note that the SPI logic will be reset once the SS pin is driven high.

– The SS pin is useful for packet / byte synchronization to keep the slave bit
counter synchronous with the master clock generator.

– When the SS pin is driven high, the SPI Slave will immediately reset the send
and receive logic, and drop any partially received data in the Shift Register.
• Master Mode
– When the SPI is configured as a Master (MSTR in SPCR is set), the
user can determine the direction of the SS pin.

– If SS is configured as an output, the pin is a general output pin

which does not affect the SPI system. Typically, the pin will be
driving the SS pin of the SPI Slave.

– If SS is configured as an input, it must be held high to ensure Master

SPI operation.

– If the SS pin is driven low by peripheral circuitry when the SPI is

configured as a Master with the SS pin defined as an input, the SPI
system interprets this as another master selecting the SPI as a slave
and starting to send data to it.
– To avoid bus contention, the SPI system takes the following
actions:
• The MSTR bit in SPCR is cleared and the SPI system becomes a
slave. As a result of the SPI becoming a slave, the MOSI and
SCK pins become inputs.
• The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled,
and the I-bit in SREG is set, the interrupt routine will be
executed.

– Thus, when interrupt-driven SPI transmission is used in master

mode, and there exists a possibility that SS is driven low, the
interrupt should always check that the MSTR bit is still set.

– If the MSTR bit has been cleared by a slave select, it must be set
by the user to re-enable SPI master mode.
 SPI Control Register – SPCR

• Bit 7 – SPIE: SPI Interrupt Enable

– This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register
is set and the if the global interrupt enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

– When the SPE bit is written to one, the SPI is enabled. This bit must be set to
enable any SPI operations.

• Bit 5 – DORD: Data Order

– When the DORD bit is written to one, the LSB of the data word is transmitted
first.
– When the DORD bit is written to zero, the MSB of the data word is transmitted
first.
• Bit 4 – MSTR: Master/Slave Select
– This bit selects Master SPI mode when written to one, and Slave
SPI mode when written logic zero.
– If SS is configured as an input and is driven low while MSTR is
set, MSTR will be cleared, and SPIF in SPSR will become set.
– The user will then have to set MSTR to re-enable SPI Master
mode.

• Bit 3 – CPOL: Clock Polarity

– When this bit is written to one, SCK is high when idle.
– When CPOL is written to zero, SCK is low when idle.

• Bit 2 – CPHA: Clock Phase

– The settings of the Clock Phase bit (CPHA) determine if data is
sampled on the leading (first) or trailing (last) edge of SCK.
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
– These two bits control the SCK rate of the device configured as a
Master. SPR1 and SPR0 have no effect on the Slave.
 SPI Status Register – SPSR

• Bit 7 – SPIF: SPI Interrupt Flag

– When a serial transfer is complete, the SPIF Flag is set.
– An interrupt is generated if SPIE in SPCR is set and global interrupts
are enabled.
– If SS is an input and is driven low when the SPI is in Master mode,
this will also set the SPIF Flag.
– SPIF is cleared by hardware when executing the corresponding
interrupt handling vector.
– Alternatively, the SPIF bit is cleared by first reading the SPI Status
Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
– The WCOL bit is set if the SPI Data Register (SPDR) is written during
a data transfer.
– The WCOL bit (and the SPIF bit) are cleared by first reading the SPI
Status Register with WCOL set, and then accessing the SPI Data
Register.

• Bit 5..1 – Reserved Bits

• Bit 0 – SPI2X: Double SPI Speed Bit

– When this bit is written logic one the SPI speed (SCK Frequency) will
be doubled when the SPI is in Master mode.
– This means that the minimum SCK period will be two CPU clock
periods.
– When the SPI is configured as Slave, the SPI is only guaranteed to
work at fosc/4 or lower.
 SPI Data Register – SPDR

– The SPI Data Register is a read/write register used for data transfer
between the Register File and the SPI Shift Register.
– Writing to the register initiates data transmission.
– Reading the register causes the Shift Register Receive buffer to be
read.
• WAP to initialize the SPI in master, mode 0, with a
clock freq. = fosc/16 and transmit ‘G’ via SPI
repeatedly. The data should be displayed on Port A.
WAP to initialize the SPI in slave, mode 0, with a
clock freq. = fosc/16 and transmit ‘G’ via SPI
repeatedly. The received data should be
displayed on Port A.
 I2C (TWI) Protocol
• I2C or IIC : Inter-Integrated Circuit
• TWI : Two Wire Serial Interface
 Data Transfer and Frame Format

START, REPEATED START and STOP Condition

• Address Packet Format
DATA Packet Format
Address and Data Packet Format into Transmission
 Multi-master Bus Systems,
Arbitration and Synchronization
• For normal data transfer on the I2C bus only one master can be
active.

• If for some reason two masters initiate I2C command at the same
time, the arbitration procedure determines which master wins
and can continue with the command.

• Different masters may use different SCL frequencies.

• A scheme must be devised to synchronize the serial clocks from all

masters, in order to let the transmission proceed in a lockstep
fashion.
SCL Synchronization between Multiple Masters
Arbitration between Two Masters
• Multibyte Burst Write

• Multibyte Burst Read

 TWI Register Description

• TWI Bit Rate Register – TWBR

– Bits [7:0] – TWI Bit Rate Register

• TWBR selects the division factor for the bit rate
generator.
• The bit rate generator is a frequency divider which
generates the SCL clock frequency in the Master
modes.
– TWI Control Register – TWCR

• Bit 7 – TWINT: TWI Interrupt Flag

– This bit is set by hardware when the TWI has finished its current
job and expects application software response.

– The TWINT Flag must be cleared by software by writing a logic

one to it.

– Note that this flag is not automatically cleared by hardware

when executing the interrupt routine.
• Bit 6 – TWEA: TWI Enable Acknowledge Bit
– The TWEA bit controls the generation of the acknowledge
pulse.
– If the TWEA bit is written to one, the ACK pulse is generated
on the TWI bus if the following conditions are met :
» 1. The device’s own slave address has been received.
» 2. A general call has been received, while the TWGCE bit
in the TWAR is set.
» 3. A data byte has been received in Master Receiver or
Slave Receiver mode.
– By writing the TWEA bit to zero, the device can be virtually
disconnected from the Two-wire Serial Bus temporarily.

• Bit 5 – TWSTA: TWI START Condition Bit

– The application writes the TWSTA bit to one when it desires to
become a master on the Two wire Serial Bus.
– Bit 4 – TWSTO: TWI STOP Condition Bit
• Writing the TWSTO bit to one in Master mode will generate a STOP condition
on the Two-wire Serial Bus.

– Bit 3 – TWWC: TWI Write Collision Flag

• The TWWC bit is set when attempting to write to the TWI Data Register –
TWDR when TWINT is low.
• This flag is cleared by writing the TWDR Register when TWINT is high.

– Bit 2 – TWEN: TWI Enable Bit

• The TWEN bit enables TWI operation and activates the TWI interface.

– Bit 1 – Reserved Bit

• This bit is a reserved bit and will always read as zero.

– Bit 0 – TWIE: TWI Interrupt Enable

• When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt
request will be activated for as long as the TWINT Flag is high.
• TWI Status Register – TWSR

– Bits [7:3] – TWS: TWI Status

• These five bits reflect the status of the TWI logic and the Two-
wire Serial Bus.
– Bit 2 – Reserved Bit
• This bit is reserved and will always read as zero.
– Bits [1:0] – TWPS: TWI Prescaler Bits
• These bits can be read and written, and control the bit rate
prescaler.
• TWI Data Register – TWDR

– These eight bits contain the next data byte to be

transmitted, or the latest data byte received on
the Two-wire Serial Bus.
• TWI (Slave) Address Register – TWAR

– Bits 7..1 – TWA: TWI (Slave) Address Register

• These seven bits constitute the slave address of the TWI
unit.

– Bit 0 – TWGCE: TWI General Call Recognition Enable Bit

• If set, this bit enables the recognition of a General Call
given over the Two-wire Serial Bus.
Overview of the TWI Module
• SCL and SDA Pins
– The internal pullups in the AVR pads can be enabled
by setting the PORT bits corresponding to the SCL
and SDA pins.

• Bit Rate Generator Unit

– This unit controls the period of SCL when operating
in a Master mode.
– CPU clock frequency in the slave must be at least 16
times higher than the SCL frequency.
• Bus Interface Unit
– The TWDR contains the address or data bytes to be
transmitted, or the address or data bytes received.

– If the TWI has initiated a transmission as master, the

Arbitration Detection hardware continuously
monitors the transmission trying to determine if
arbitration is in process.

– If the TWI has lost an arbitration, the Control Unit is

informed. Correct action can then be taken and
appropriate status codes generated.
• Address Match Unit
– The Address Match unit checks if received address
bytes match the 7-bit address in the TWI Address
Register (TWAR).

– If the TWI General Call Recognition Enable (TWGCE)

bit in the TWAR is written to one, all incoming
address bits will also be compared against the
General Call address.

– Upon an address match, the Control Unit is informed,

allowing correct action to be taken.
• Control Unit
– As long as the TWINT Flag is set, the SCL line is held low. This allows
the application software to complete its tasks before allowing the
TWI transmission to continue.

– The TWINT Flag is set in the following situations:

• After the TWI has transmitted a START/REPEATED START
condition
• After the TWI has transmitted SLA+R/W
• After the TWI has transmitted an address byte
• After the TWI has lost arbitration
• After the TWI has been addressed by own slave address or
general call
• After the TWI has received a data byte
• After a STOP or REPEATED START has been received while still
addressed as a slave
• When a bus error has occurred due to an illegal START or STOP
DC Motor Interfacing