LCD Interfacing

• Liquid Crystal Display

LCD Pin Description
LCD Command Codes
• Sending Command & Data to LCD
– Initialize the LCD.
– Send command to the LCD.
– Send character to be shown to the LCD.
LCD Connection for 8-bit data
LCD Connection for 4-bit data
• Sending Command & Data to LCD
– Initialize the LCD.
– Send command to the LCD.
– Send character to be shown to the LCD.
Keyboard Interfacing
Flowchart
 USART
• The Universal Synchronous and Asynchronous serial Receiver and Transmitter
(USART) is a highly flexible serial communication device.

• The main features are:

• Full Duplex Operation (Independent Serial Receive and Transmit
Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High Resolution Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Three Separate Interrupts on TX Complete, TX Data Register Empty, and
RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
• Three main parts of the USART are :
– Clock Generator
– Transmitter
– Receiver.

• Clock Generator
– The clock generation logic consists of synchronization
logic for external clock input used by synchronous
slave operation, and the baud rate generator.
• The Transmitter
– The Transmitter consists of a
• Single write buffer
• A serial Shift Register
• Parity generator
• Control logic for handling different serial frame
formats.

– The write buffer allows a continuous transfer of data

without any delay between frames.
• The Receiver
– The receiver is the most complex part of the USART
module due to its clock and data recovery units.

– In addition to the recovery units, the receiver

includes a parity checker, control logic, a Shift
Register and a two level receive buffer (UDR).

– The receiver supports the same frame formats as

the transmitter, and can detect frame error, data
overrun and parity errors.
 Clock Generation
• The clock generation logic generates the base clock for the Transmitter
and Receiver.

• The USART supports four modes of clock operation:

– Normal Asynchronous
– Double Speed Asynchronous
– Master Synchronous
– Slave Synchronous

• The UMSEL bit in USART Control and Status Register C (UCSRC) selects
between asynchronous and synchronous operation.

• When using Synchronous mode (UMSEL = 1), the Data Direction Register
for the XCK pin (DDR_XCK) controls whether the clock source is internal
(Master mode) or external (Slave mode).
 Internal Clock Generation
( The Baud Rate Generator)
• Internal clock generation is used for the asynchronous and the
synchronous master modes of operation.

• The USART Baud Rate Register (UBRR) and the down-counter connected
to it function as a programmable prescaler or baud rate generator.

• The down-counter is loaded with the UBRR value each time the counter
has counted down to zero or when the UBRRL Register is written.

• This clock is the baud rate generator clock output (= fosc/16(UBRR+1)).

• The baud rate generator output is used directly by the receiver’s clock
and data recovery units.
• External Clock
– External clocking is used by the synchronous slave
modes of operation.
– External clock input from the XCK pin is sampled by a
synchronization register to minimize the chance of
meta-stability.

• Synchronous Clock Operation

– When Synchronous mode is used (UMSEL = 1), the
XCK pin will be used as either clock input (Slave) or
clock output (Master).
Clock Generation Logic ( Block Diagram )
Equations for Calculating Baud Rate Register
Setting
Synchronous Clock Operation
 Frame Formats
• A serial frame is defined to be one character of data bits with
synchronization bits (start and stop bits), and optionally a parity bit for
error checking.

• The USART accepts all 30 combinations of the following as valid frame

formats:
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits

• When a complete frame is transmitted, it can be directly followed by a

new frame, or the communication line can be set to an idle (high) state.
Frame Format
 USART Register Description
• USART I/O Data Register – UDR
– The Transmit Data Buffer Register (TXB) will be the
destination for data written to the UDR Register
location.
– Reading the UDR Register location will return the
contents of the Receive Data Buffer Register (RXB).
– For 5-bit, 6-bit, or 7-bit characters the upper unused
bits will be ignored by the Transmitter and set to zero
by the Receiver.
Simplified USART Block Diagram
• USART Control and Status Register A – UCSRA

– Bit 7 – RXC: USART Receive Complete

• This flag bit is set when there are unread data in the receive buffer and
cleared when the receive buffer is empty.
• The RXC Flag can generate a Receive Complete interrupt .

– Bit 6 – TXC: USART Transmit Complete

• This flag bit is set when the entire frame in the transmit Shift Register
has been shifted out and there are no new data currently present in the
transmit buffer (UDR).
• The TXC Flag bit is automatically cleared when a transmit complete
interrupt is executed, or it can be cleared by writing a one to its bit
location.
– Bit 5 – UDRE: USART Data Register Empty
• The UDRE Flag indicates if the transmit buffer (UDR) is ready to receive
new data.
• If UDRE is one, the buffer is empty, and therefore ready to be written.
• The UDRE Flag can generate a Data Register empty Interrupt.

– Bit 4 – FE: Frame Error

• This bit is set if the next character in the receive buffer had a Frame
Error when received.
• The FE bit is one when the stop bit of received data is zero.

– Bit 3 – DOR: Data OverRun

• This bit is set if a Data OverRun condition is detected.
• A Data OverRun occurs when the receive buffer is full, it is a new
character waiting in the receive Shift Register, and a new start bit
is detected.
• This bit is valid until the receive buffer (UDR) is read.
– Bit 2 – PE: Parity Error
• This bit is set if the next character in the receive buffer had a
Parity Error when received and the parity checking was enabled
at that point (UPM1 = 1).
• This bit is valid until the receive buffer (UDR) is read.

– Bit 1 – U2X: Double the USART Transmission Speed

• This bit only has effect for the asynchronous operation.
• Write this bit to zero when using synchronous operation.

– Bit 0 – MPCM: Multi-processor Communication Mode

• This bit enables the Multi-processor Communication mode.
• When the MPCM bit is written to one, all the incoming frames
received by the USART receiver that do not contain address
information will be ignored.
Baud rate Generation block diagram
• USART Control and Status Register B – UCSRB

– Bit 7 – RXCIE: RX Complete Interrupt Enable

• Writing this bit to one enables interrupt on the RXC Flag.
• A USART Receive Complete Interrupt will be generated only if the
RXCIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the RXC bit in UCSRA is set.

– Bit 6 – TXCIE: TX Complete Interrupt Enable

• Writing this bit to one enables interrupt on the TXC Flag.
• A USART Transmit Complete Interrupt will be generated only if the
TXCIE bit is written to one, the Global Interrupt Flag in SREG is written
to one and the TXC bit in UCSRA is set.
– Bit 5 – UDRIE: USART Data Register Empty Interrupt Enable
• Writing this bit to one enables interrupt on the UDRE Flag.
• A Data Register Empty Interrupt will be generated only if the UDRIE bit is
written to one, the Global Interrupt Flag in SREG is written to one and
the UDRE bit in UCSRA is set.

– Bit 4 – RXEN: Receiver Enable

• Writing this bit to one enables the USART Receiver.
• The Receiver will override normal port operation for the RxD pin when
enabled.
• Disabling the Receiver will flush the receive buffer invalidating the FE,
DOR, and PE Flags.

– Bit 3 – TXEN: Transmitter Enable

• Writing this bit to one enables the USART Transmitter.
• The Transmitter will override normal port operation for the TxD pin
when enabled.
• When disabled, the transmitter will no longer override the TxD port.
– Bit 2 – UCSZ2: Character Size
• The UCSZ2 bits combined with the UCSZ1:0 bit in UCSRC sets the
number of data bits (Character Size) in a frame the receiver and
transmitter use.

– Bit 1 – RXB8: Receive Data Bit 8

• RXB8 is the ninth data bit of the received character when operating
with serial frames with nine data bits.
• Must be read before reading the low bits from UDR.

– Bit 0 – TXB8: Transmit Data Bit 8

• TXB8 is the ninth data bit in the character to be transmitted when
operating with serial frames with nine data bits.
• Must be written before writing the low bits to UDR.
• USART Control and Status Register C – UCSRC

– Bit 7 – URSEL: Register Select

• This bit selects between accessing the UCSRC or the UBRRH Register.
• It is read as one when reading UCSRC.
• The URSEL must be one when writing the UCSRC.

– Bit 6 – UMSEL: USART Mode Select

• This bit selects between Asynchronous and Synchronous mode of
operation.
» 0 - Asynchronous Operation
» 1 - Synchronous Operation
– Bit 5:4 – UPM1:0: Parity Mode
• These bits enable and set type of parity generation and
check.
• If enabled, the transmitter will automatically generate and
send the parity of the transmitted data bits within each
frame.
• The Receiver will generate a parity value for the incoming
data and compare it to the UPM0 setting.
• If a mismatch is detected, the PE Flag in UCSRA will be set.
– Bit 3 – USBS: Stop Bit Select
• This bit selects the number of Stop Bits to be inserted
by the Transmitter.
• The Receiver ignores this setting.
– Bit 2:1 – UCSZ1:0: Character Size
• The UCSZ1:0 bits combined with the UCSZ2 bit in
UCSRB sets the number of data bits (Character Size) in a
frame the Receiver and Transmitter use.
– Bit 0 – UCPOL: Clock Polarity
• This bit is used for Synchronous mode only. Write this
bit to zero when Asynchronous mode is used.
• The UCPOL bit sets the relationship between data
output change and data input sample, and the
synchronous clock (XCK).
 USART Baud Rate Registers – UBRRL
and UBRRH

– Bit 15 – URSEL: Register Select

• This bit selects between accessing the UBRRH or the
UCSRC Register.
• It is read as zero when reading UBRRH.
• The URSEL must be zero when writing the UBRRH.
– Bit 14:12 – Reserved Bits
• These bits are reserved for future use.
• For compatibility with future devices, these bit must be
written to zero when UBRRH is written.

– Bit 11:0 – UBRR11:0: USART Baud Rate Register

• This is a 12-bit register which contains the USART baud rate.
• The UBRRH contains the four most significant bits, and the
UBRRL contains the 8 least significant bits of the USART
baud rate.
• Ongoing transmissions by the transmitter and receiver will
be corrupted if the baud rate is changed.
• Writing UBRRL will trigger an immediate update of the baud
rate prescaler.
 USART Initialization
• The USART has to be initialized before any communication can take
place.

• The initialization process normally consists of

– setting the baud rate
– setting frame format
– enabling the Transmitter or the Receiver depending on the
usage.

• For interrupt driven USART operation, the Global Interrupt Flag

should be cleared (and interrupts globally disabled) when doing the
initialization.

• WAP to initialize the USART in Synchronous TX mode with a Baud

Rate of 9600. (Frame format : 8 data bit, 2 stop bit)
void USART_Init ( unsigned int baud )
{
/* Set baud rate */
UBRRH = (unsigned char)(baud>>8);
UBRRL = (unsigned char)baud;
/* Enable receiver and transmitter */
UCSRB = (1<<RXEN)|(1<<TXEN);
/* Set frame format: 8data, 2stop bit */
UCSRC = (1<<URSEL)|(1<<USBS)|(3<<UCSZ0);
}
 Data Transmission – The USART Transmitter
• The USART Transmitter is enabled by setting the Transmit Enable
(TXEN) bit in the UCSRB Register.

• When the Transmitter is enabled, the normal port operation of

the TxD pin is overridden by the USART and given the function as
the transmitter’s serial output.

• The baud rate, mode of operation and frame format must be set
up once before doing any transmissions.

• If synchronous operation is used, the clock on the XCK pin will be

overridden and used as transmission clock.

• WAP to transmit a frame with 9 databits.

void USART_Transmit( unsigned int data )
{
/* Wait for empty transmit buffer */
while ( !( UCSRA & (1<<UDRE) ) ) ;
/* Copy 9th bit to TXB8 */
UCSRB &= ~(1<<TXB8);
if ( data & 0x0100 )
UCSRB |= (1<<TXB8);
/* Put data into buffer, sends the data */
UDR = data;
}
 Disabling the Transmitter
• The disabling of the transmitter (setting the TXEN to
zero) will not become effective until ongoing and
pending transmissions are completed, that is, when
the transmit Shift Register and transmit Buffer
Register do not contain data to be transmitted.

• When disabled, the transmitter will no longer

override the TxD pin.
 Data Reception – The USART Receiver
• The USART Receiver is enabled by writing the Receive Enable
(RXEN) bit in the UCSRB Register to one.

• When the receiver is enabled, the normal pin operation of the

RxD pin is overridden by the USART and given the function as the
receiver’s serial input.

• The baud rate, mode of operation and frame format must be set
up once before any serial reception can be done.

• If synchronous operation is used, the clock on the XCK pin will be

used as transfer clock.

• WAP for Receiving Frames with 9 Databits.

unsigned int USART_Receive( void )
{ unsigned char status, resh, resl;
/* Wait for data to be received */
while ( !(UCSRA & (1<<RXC)) ) ;
/* Get status and 9th bit, then data from buffer */
status = UCSRA;
resh = UCSRB;
resl = UDR;
/* If error, return -1 */
if ( status & (1<<FE)|(1<<DOR)|(1<<PE) )
return -1;
/* Filter the 9th bit, then return */
resh = (resh >> 1) & 0x01;
return ((resh << 8) | resl);
 Disabling the Receiver
• In contrast to the Transmitter, disabling of the Receiver will
be immediate.

• Data from ongoing receptions will therefore be lost.

• When disabled (that is, the RXEN is set to zero) the

Receiver will no longer override the normal function of the
RxD port pin.

• The receiver buffer FIFO will be flushed when the receiver

is disabled. Remaining data in the buffer will be lost
 Asynchronous Data Reception
• The USART includes a clock recovery and a data recovery unit
for handling asynchronous data reception.

• The clock recovery logic is used for synchronizing the

internally generated baud rate clock to the incoming
asynchronous serial frames at the RxD pin.

• The data recovery logic samples each incoming bit.

• The asynchronous reception operational range depends on

the accuracy of the internal baud rate clock, the rate of the
incoming frames, and the frame size in number of bits.
Asynchronous Clock Recovery

Start Bit Sampling

Sampling of Data and Parity Bit
Stop Bit Sampling and Next Start Bit Sampling
 Multi-processor Communication Mode

• Multi-processor Communication mode (MPCM) bit in

UCSRA enables a filtering function of incoming frames
received by the USART Receiver.

• Frames that do not contain address information will be

ignored and not put into the receive buffer.

• This effectively reduces the number of incoming frames

that has to be handled by the CPU, in a system with
multiple MCUs that communicate via the same serial bus.
• The Transmitter is unaffected by the MPCM setting, but
has to be used differently when it is a part of a system
utilizing the Multi-processor Communication mode.

• If the receiver is set up to receive frames that contain 5 to

8 data bits, then the first stop bit indicates if the frame
contains data or address information.

• If the receiver is set up for frames with nine data bits,

then the ninth bit (RXB8) is used for identifying address
and data frames.
• When the frame type bit (the first stop or the ninth bit) is one,
the frame contains an address.

• When the frame type bit is zero the frame is a data frame.

• The Multi-processor Communication mode enables several

slave MCUs to receive data from a master MCU.

• This is done by first decoding an address frame to find out

which MCU has been addressed.

• If a particular Slave MCU has been addressed, it will receive

the following data frames as normal, while the other slave
MCUs will ignore the received frames until another address
frame is received.