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IDDQ

IDDQ testing is an integrated circuit testing method that measures steady-state power-supply current to detect defects like gate-oxide shorts. It identifies physical defects by monitoring the IDDQ current, which increases significantly in the presence of faults. However, as technology advances, distinguishing between defect-free and defective currents becomes challenging due to increased leakage and overlapping current distributions.

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Karthik S
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9 views14 pages

IDDQ

IDDQ testing is an integrated circuit testing method that measures steady-state power-supply current to detect defects like gate-oxide shorts. It identifies physical defects by monitoring the IDDQ current, which increases significantly in the presence of faults. However, as technology advances, distinguishing between defect-free and defective currents becomes challenging due to increased leakage and overlapping current distributions.

Uploaded by

Karthik S
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPT, PDF, TXT or read online on Scribd
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IIDDQ

DDQ
Current
Current Testing
Testing

1
Basic
Basic Principle
Principle of
of IIDDQ Testing
DDQ Testing

 Measure IDDQ current through Vss bus


Basic
Basic Principles
Principles

 IDDQ testing refers to the integrated circuit (IC) testing


method based upon measurement of steady state power-
supply current.
 Iddq stands for quiescent Idd, or quiescent power-supply
current.
 in case of a defect such as gate-oxide short or short
between two metal lines, a conduction path from power-
supply (Vdd) to ground (Gnd) is formed and subsequently
the circuit dissipates significantly high current.
 This faulty current is a few orders of magnitude higher
than the fault-free leakage current.
 Iddq testing provides physical defect oriented testing
Physical
Physical Defects
Defects
 Wafer defects are found in clusters. These clusters are
randomly distributed over the whole wafer. Every part
of the wafer has an equal probability of having a defect
cluster.
 Any part of a diffusion, Polysilicon, or metal line may
have an open fault. Any contact between any two layers
may be open.
 Bridging may occur between any two electrical nodes,
whether they belong to one layer or different layers
 Only a small percentage of bridging and open faults can
be modeled at the stuck-at level. The actual distribution
varies and largely depends on the technology and
fabrication process.
Bridging
Bridging

Vdd Vdd
V1  rL1 V2  (rL1  x)

rL1  x  rH 2 
rL1  x  rH 2
Bridging
Bridging

in the presence of bridging, a


conduction path is formed
from Vdd to Gnd.
Subsequently, the circuit
dissipates a large current
through this path, and thus,
simple monitoring of the
supply current can detect
bridging.
Floating
Floating Gate
Gate Defects
Defects

 Small break in logic gate inputs (100 –


200 Angstroms) lets wires couple by
electron tunneling
 Delay fault and I
DDQ fault
 Large open results in stuck-at fault – not
detectable by IDDQ test
 If Vtn < Vfn < VDD - | Vtp | then
detectable by IDDQ test
Capacitive
Capacitive Coupling
Coupling of
of Floating
Floating
Gates
Gates
 Cpb – capacitance from poly to
bulk
 Cmp – overlapped metal wire
to poly
 Floating gate voltage
depends on capacitances and
node voltages
 If nFET and pFET get enough
gate voltage to turn them on,
then IDDQ test detects this
defect
NAND
NAND Open
Open Circuit
Circuit Defect
Defect –– Floating
Floating gate
gate
Open
Open

 Not very effective for open defects


 The vector AB=01 sensitizes the open
 In the presence of the open output of the gate is in high
impedance
 The vector before the sensitization vectors defines the logic
values at the output
Iddq
Iddq Testing
Testing in
in DSM
DSM
 The theoretical basis of Iddq testing is based upon
estimation of defect-free current in the circuit and then
setting a limit (popularly, called as Iddq threshold)
above which a circuit is considered defective.
Iddq
Iddq Testing
Testing in
in DSM
DSM

 When the density functions of defect-free and defective


current are separate from each other, the clear distinction
between the good and the defective IC can be made.
 However, with technology shrink (increased sub-threshold
leakage) and increasing number of gates in an IC, the
mean value of the distribution of defect-free current
increases and approaches the Iddq threshold limit (set
from earlier technology).
 Just changing the threshold limit to a higher number does
not resolve the issue because with high leakage in the
circuit, change in defect-free and defective current is very
small
Built
Built in
in current
current testing
testing

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