Synthesis and Optimization of Digital Circuits

Ch 7 – Sequential Logic Optimization

Under The Guidance of

Prof. Prithvi Pothupogu
Associate Professor

By
24ECM1R20
24ECM1R21
24ECM1R22
24ECM1R24
24ECM1R25

Department of Electronics and Communication Engineering

National Institute of Technology - Warangal
March - 2025
 Module 1

• Objective
• Motivation and assumptions for sequential synthesis
• Finite-state machine design and optimization
 Synchronous logic circuits

• Interconnection of
• Combinational logic gates
• Synchronous delay elements
• Edge-triggered, master/slave

• Assumptions
• No direct combinational feedback
• Single-phase clocking
• Extensions to
• Multiple-phase clocking
• Gated latches
 Modeling synchronous circuits

• Circuit are modeled in hardware languages

• Circuit model may be directly related to FSM model
• Description by: switch-case
• Circuit model may be structural
• Explicit definition of registers

• Sequential circuit models can be generated from high-level

models
• Control generation in high-level synthesis
 Modeling synchronous circuits

• State-based model:
• Model circuits as finite-state machines (FSMs)
• Represent by state tables/diagrams
• Apply exact/heuristic algorithms for:
• State minimization
• State encoding

• Structural model
• Represent circuit by synchronous logic network
• Apply
• Retiming
• Logic transformations
State-based optimization
 Modeling synchronous circuits
• Advantages and disadvantages of models
• State-based model
• Explicit notion of state
• Implicit notion of area and delay
• Structural model
• Implicit notion of state
• Explicit notion of area and delay
• Transition from a model to another is possible
• State encoding
• State extraction
 Sequential logic optimization

• Typical flow
• Optimize FSM state model first
• Reduce complexity of the model
• E.g., apply state minimization
• Correlates to area reduction
• Encode states and obtain a structural model
• Apply retiming and transformations
• Achieve performance enhancement
• Use state extraction for verification purposes
 Formal finite-state machine model

• A set of primary input patterns X

• A set of primary output patterns Y

• A set of states S

• A state transition function: δ: X × S → S

• An output function:
• λ: X × S → Y for Mealy models
• λ: S → Y for Moore models
 State minimization
• Classic problem
• Exact and heuristic algorithms are available
• Objective is to reduce the number of states and hence the area
• Completely-specified finite-state machines
• No don’t care conditions
• Polynomial-time solutions
• Incompletely-specified finite-state machines
• Unspecified transitions and/or outputs
• Usual case in synthesis
• Intractable problem:
• Requires binate covering
 State minimization
for completely-specified FSMs

• Equivalent states:
• Given any input sequence, the corresponding output sequence match

• Theorem:
• Two states are equivalent if and only if:
• They lead to identical outputs and their next-states are equivalent

• Equivalence is transitive
• Partition states into equivalence classes
• Minimum finite-state machine is unique
 State minimization
for completely-specified FSMs

• Stepwise partition refinement:

• Initially:
• All states in the same partition block
• Iteratively:
• Refine partition blocks
• At convergence:
• Partition blocks identify equivalent states

• Refinement can be done in two directions

• Transitions from states in block to other states
• Classic method. Quadratic complexity
• Transitions into states of block under consideration
• Inverted tables. Hopcroft’s algorithm.
 Example of refinement

• Initial partition:
• Π1 : States belong to the same block when outputs are
the same for any input
• Iteration:
• Πk+1 : States belong to the same block if they were
previously in the same block and their next states are in
the same block of Πk for any input
• Convergence:
• Πk+1 = Πk
Example
Example
 Example

• Π1 = { { s1, s2} , { s3,s4 }, { s5 } }

• Π2 = { { s1, s2} , { s3} , { s4 }, { s5 } }

• Π2 is a partition into equivalence classes

• No further refinement is possible
• States { s1, s2 } are equivalent
 State minimization
for incompletely-specified finite-state machines

• Applicable input sequences

• All transitions are specified
• Compatible states
• Given any applicable input sequence, the corresponding output
sequence match
• Theorem:
• Two states are compatible if and only if:
• They lead to identical outputs
• (when both are specified)
• And their next state is compatible
• (when both are specified)
 State minimization
for incompletely-specified finite-state machines

• Compatibility is not an equivalence relation

• Minimum finite-state machine is not unique

• Implication relation make the problem intractable

• Two states may be compatible, subject to other states being
compatible.
• Implications are binate satisfiability clauses
• a -> b = a’+b
Example
 Trivial method

• Consider all possible don’t care assignments

• n don’t care imply
• 2n completely specified FSMs
• 2n solutions

• Example:
• Replace * by 1
• Π1 = { { s1, s2} , { s3}, {s4 }, { s5 } }
• Replace * by 0
• Π1 = { { s1, s5} , { s2,s3 , s4 } }
 Compatibility and implications
Example

• Compatible states {s1 , s2}

• If {s3 , s4} are compatible

• Then {s1 , s5 } are also compatible

• Incompatible states {s2 , s5}

 Compatibility and implications
• Compatible pairs:
• {s1, s2}
• {s1, s5} ← {s3, s4}
• {s2, s4} ← {s3, s4}
• {s2, s3} ← {s1, s5}
• {s3, s4} ← {s2, s4} U {s1, s5}

• Incompatible pairs
• {s2, s5}
• {s3, s5}
• {s1, s4}
• {s4, s5}
• {s1, s3}
 Compatibility and implications

• A class of compatible states is such that all state pairs are

compatible
• A class is maximal
• If not subset of another class
• Closure property
• A set of classes such that all compatibility implications are
satisfied
• The set of maximal compatibility classes
• Has the closure property
• May not provide a minimum solution
 Maximum compatibility classes

• Example:
• {s1, s2}
• {s1, s5} ← {s3, s4}
• {s2, s3, s4} ← {s1, s5}

• Cover with all MCC has cardinality 3

 Exact problem formulation
• Prime compatibility classes:
• Compatibility classes having the property that they are not subset of other
classes implying the same (or subset) of classes

• Compute all prime compatibility classes

• Select a minimum number of prime classes

• Such that all states are covered
• All implications are satisfied

• Exact solution requires binate cover

• Good approximation methods exists

• Stamina
 Prime compatibility classes

• Example:
• {s1, s2}
• {s1, s5} ← {s3, s4}
• {s2, s3, s4} ← {s1, s5}

• Minimum cover:
• {s1, s5} , {s2, s3, s4}
• Minimum cover has cardinality 2
 State encoding

• Determine a binary encoding of the states

• Optimizing some property of the representation (mainly area)

• Two-level model for combinational logic

• Methods based on symbolic optimization
• Minimize a symbolic cover of the finite state machine
• Formulate and solve a constrained encoding problem

• Multiple-level model
• Some heuristic methods that look for encoding which privilege
cube and/or kernel extraction
• Weak correlation with area minimality
 Example
INPUT P-STATE N-STATE OUTPUT
0 s1 s3 0
1 s1 s3 0
0 s2 s3 0
1 s2 s1 1
0 s3 s5 0
1 s3 s4 1
0 s4 s2 1
1 s4 s3 0
0 s5 s2 1
1 s5 s5 0
 Example
• Minimum symbolic cover:
* s1s2s4 s3 0
1 s2 s1 1
0 s4s5 s2 1
1 s3 s4 1

• Encoded cover :

* 1** 001 0
1 101 111 1
0 *00 101 1
1 001 100 1
 Summary
finite-state machine optimization

• FSM optimization has been widely researched

• Classic and newer approaches

• State minimization and encoding correlate to area reduction

• Useful, but with limited impact

• Performance-oriented FSM optimization has mixed results

• Performance optimization is usually done by structural methods
 Module 2

• Objective
• Structural representation of sequential circuits
• Retiming
• Extensions
 Structural model for sequential circuits

• Synchronous logic network

• Variables
• Boolean equations
• Synchronous delay annotation

• Synchronous network graph

• Vertices ↔ equations ↔ I/O, gates
• Edges ↔ dependencies ↔ nets
• Weights ↔ synchronous delays ↔ registers
Example
Example
 Approaches to sequential synthesis

• Optimize combinational logic only

• Freeze circuit at register boundary
• Modify equation and network graph topology

• Retiming
• Move register positions. Change weights on graph
• Preserve network topology

• Synchronous transformations
• Blend combinational transformations and retiming
• Powerful, but complex to use
Example of local retiming
 Retiming

• Global optimization technique

• Change register positions

• Affects area:
• Retiming changes register count
• Affects cycle-time:
• Changes path delays between register pairs

• Retiming algorithms have polynomial-time

complexity
 Retiming assumptions
• Delay is constant at each vertex
• No fanout delay dependency
• Graph topology is invariant
• No logic transformations
• Synchronous implementation
• Cycles have positive weights
• Each feedback loop has to be broken by at least one register
• Edges have non-negative weights
• Physical registers cannot anticipate time
• Consider topological paths
• No false path analysis
 Retiming

• Retiming of a vertex v
• Integer rv
• Registers moved from output to input: rv positive
• Registers moved from input to output: rv negative

• Retiming of a network
• Vector whose entries are the retiming at various vertices
• A family of I/O equivalent networks are specified by:
• The original network
• A set of vectors satisfying specific constraints
• Legal retiming
 Example
7 7 7
Original graph 0 0 Delay: 24
vg vf ve 0
0
3
0 0 0 0
vh vd
3 3 3
1 vb 1
va vc
1 1

7 7 7
1 1
Retimed graph vg vf ve 0
Delay: 13
0
3
0
vh 1 0 0 vd
3 3 3
0 vb 1
va vc
1 0
 Definitions and properties
• Definitions:
• w( vi, v j) weight on edge ( vi, vj )
• ( vi, …, vj ) path from vi to vj
• w( vi, …, vj ) weight on path from vi to vj
• d( vi, …, vj ) combinational delay on path from vi to vj

• Properties:
wij
• Retiming of an edge ( vi, vj ) vi vj
• ŵij = wij + rj – ri
• Retiming of a path ( vi, …, vj )
• ŵ ( vi, …, vj) = w (vi, …, vj) + rj – ri
• Cycle weights are invariant
 Legal retiming

• A retiming vector is legal iff:

• No edge weight is negative
• ŵij ( vi, vj) = wij (vi, vj) + rj – ri ≥ 0 for all i, j
• Given a clock period φ:
• Each path ( vi, …, vj) with d ( vi, …, vj) > φ
has at least one register:
• ŵ ( vi, …, vj) = w (vi, …, vj) + rj – ri ≥ 1 for all i, j
• Equivalently, each combinational path delay is less than φ
 Refined analysis

• Least-register path
• W (vi, vj) = min w (vi, …, vj) over all paths between vi and vj

• Critical delay:
• D (vi, vj) = max d (vi, …, vj) over all paths between vi and vj
with weight W (vi, vj)

• There exist a vertex pair (vi, vj) whose delay D (vi, vj) bounds
the cycle time
 Example
7 7 7
0 0
vg vf ve 0
0
3
0
vh 0 0 0 vd
3 3 3
1 vb 1
va vc
1 1

•Vertices: va, ve
•Paths: (va, vb, vc , ve) and (va, vb, vc, vd, ve)
•W(va, ve) = 2
•D(va, ve) = 16
 Minimum cycle-time retiming problem
• Find the minimum value of the clock period φ
such that there exist a retiming vector where:
• ri – rj ≤ wij for all ( vi, vj )
• All registers are implementable
• ri – rj ≤ W (vi, vj) – 1 for all ( vi, vj ) such that D (vi, vj) > φ
• All timing path constraints are satisfied
• Solution
• Given a value of φ
• Solve linear constraints A r ≤ b
• Mixed integer-linear program
• A set of inequalities has a solution if the constraint graph has no positive cycles
• Bellman-Ford algorithm – compute longest path
• Iterative algorithm
• Relaxation
 Minimum cycle-time retiming algorithm
• Compute all pair path weights W (vi, vj) and delays D (vi, vj)
• Warshall-Floyd algorithm with complexity O( |V|3 )

• Sort the elements of D (vi, vj) in decreasing order

• Because an element of D is the minimum φ

• Binary search for a φ in D (vi, vj) such that

• There exists a legal retiming
• Bellman-Ford algorithm with complexity O( |V|3 )

• Remarks
• Result is a global optimum
• Overall complexity is O( |V|3 log |V| )
 Example: original graph
7 7 7
0 0
vg vf ve 0
0
3
0
vh 0 0 0 vd
3 3 3
1 vb 1
va vc
1 1

•Constraints (first type):

• ra - rb ≤ 1 or equivalently rb ≥ ra – 1
• rc - rb ≤ 1 or equivalently rc ≥ rb – 1
•…
 Example: constraint graph
7 7 7
0 0
rg rf re 0
0
3
0
rh 0 0 0 rd
3 3 3
-1 rb -1
ra rc
-1 -1

•Constraints (first type):

-1
• ra - rb ≤ 1 or equivalently rb ≥ ra – 1 ra rb

• rc - rb ≤ 1 or equivalently rc ≥ rb – 1
•…
 Example
• Sort elements of D:
• 33,30,27,26,24,23,21,20,19,17,16,14,13,12,10,9,7,6,3

• Select φ = 19
• 33,30,27,26,24,23,21,20,19,17,16,14,13,12,10,9,7,6,3
• Pass: legal retiming found

• Select φ = 13
• 33,30,27,26,24,23,21,20,19,17,16,14,13,12,10,9,7,6,3
• Pass: legal retiming found

• Select φ < 13
• 33,30,27,26,24,23,21,20,19,17,16,14,13,12,10,9,7,6,3
• Fail: no legal retiming found

• Fastest cycle time is φ = 13. Corresponding retiming vector is used

Example φ = 13

1 1

0 0
rg rf re 0
0 -1
-1
rh 0 0
-2
0 rd
-1 -1
ra rb rc
-1 -1
 Example φ = 13
1 1
• Constraint graph:
0 0
rg rf re 0
0 -1
-1
• Longest path from source rh 0 0
-2
0 rd
-[12232100] -1 -1
•
ra rb rc
-1 -1

7 7 7
1 1
• Retimed graph
vg vf ve 1
0
3
0
vh 1 1 0 vd
3 3 3
0 vb 0
va vc
0 1
 Example φ = 13
7 7 7
• The solution is not unique 1 1
vg vf ve 1
0
3
0
vh 1 1 0 vd
3 3 3
0 vb 0
va vc
0 1

7 7 7
1 1
vg vf ve 0
0
3
0
vh 1 0 0 vd
3 3 3
0 vb 1
va vc
1 0
 Relaxation-based retiming

• Most common algorithm for retiming

• Avoids storage of matrices W and D
• Applicable to large circuits

• Rationale
• Search for decreasing φ in fixed step
• Look for values of φ compatible with peripheral circuits
• Use efficient method to determine legality
• Network graph is often very sparse
• Can be coupled with topological timing analysis
 Relaxation-based retiming

• Start with a given cycle-time φ

• Look for paths with excessive delays

• Make such paths shorter

• By bringing the terminal register closer
• Some other paths may become longer
• Namely, those path whose tail has been moved

• Use an iterative approach

 Relaxation-based retiming

• Define data ready time at each node

• Total delay from register boundary
• Iterative approach
• Find vertices with data ready > φ
• Retime these vertices by 1
• Algorithm properties
• If at some iteration there is no vertex with data ready > φ,
a legal retiming has been found
• If a legal retiming is not found in |V| iterations,
then no legal retiming exists for that φ
 Example φ = 13 iteration = 1

7 7 7 7 7 7
0 0
vg vf ve 0 vg vf ve
0
3 3
0 0
vh 0 0 0 vd vh vd
3 3 3 3 3 3
1 vb 1
va vc va vb vc
1 1
 Example φ = 13 iteration = 2

7 7 7 7 7
0 1 7
vg vf ve 0 vg vf ve
0
3 3
0
vh 1 1 0 vd vh 0
vd
3 3 3 3 3
3
0 vb 1
va vc va vb vc
1 1
 Example φ = 13 iteration = 3

7 7 7 7 7
1 1 7
vg vf ve 0 vg vf ve
0
3 3
0
vh 1 1 0 vd vh 0
vd
3 3 3 3 3
3
0 vb 1
va vc va vb vc
0 1
 Retiming for minimum area

• Find a retiming vector that minimizes the number of

registers
• Simple area modeling
• Every edge with a positive weight denotes registers
• Total register area is proportional to the sum of all weights
• Register sharing model
• Every set of positively-weighted edges with common tail is
realized by a shift register with taps
• Total register area is proportional to the sum, over all vertices, of
the maxima of weights on outgoing edges
Example
 Minimum area retiming
simple model

• Register variation at node v

• rv ( indegree(v) – outdegree(v) )

• Total area variation:

• Σ rv ( indegree(v) – outdegree(v) )

• Area minimization problem:

• Min Σ rv ( indegree(v) – outdegree(v) )
• Such that ri – rj ≤ wij for all ( vi, vj )
 Minimum area retiming
under timing constraint

• Area recovery under timing constraint

• Min Σ rv ( indegree(v) – outdegree(v) ) such that:
• ri – rj ≤ wij for all ( vi, vj ) and
• ri – rj ≤ W (vi, vj) – 1 for all ( vi, vj ) such that D (vi, vj) > φ

• Common implementation is by integer linear program

• Problem can alternatively be transformed into a matching problem and
solved by Edmonds-Karp algorithm
• Register sharing
• Construct auxiliary network and apply this formulation.
• Auxiliary network construction takes into account register sharing
 Other problems related to retiming

• Retiming pipelined circuits

• Balance pipe stages by using retiming
• Trade-off latency versus cycle time
• Peripheral retiming
• Use retiming to move registers to periphery of a circuit
• Restore registers after optimizing combinational logic
• Wire pipelining
• Use retiming to pipeline interconnection wires
• Model sequential and combinational macros
• Consider wire delay and buffering
 Summary of retiming

• Sequential optimization technique for:

• Cycle time or register area
• Applicable to
• Synchronous logic networks
• Architectural models of data paths
• Vertices represent complex (arithmetic) operators
• Exact algorithm in polynomial time
• Extension and issues
• Delay modeling
• Network granularity
 Module 3

• Objective
• Relating state-based and structural models
• State extraction
 Relating the sequential models

• State encoding
• Maps a state-based representation into a structural one

• State extraction
• Recovers the state information from a structural model

• Remark
• A circuit with n registers may have 2n states
• Unreachable states
 State extraction
• State variables: p, q

• Initial state p=0; q=0;

• Four possible states

 State extraction

• Reachability analysis
• Given a state, determine which states are reachable for some
inputs
• Given a state subset, determine the reachable state subset
• Start from an initial state
• Stop when convergence is reached

• Notation:
• A state (or a state subset) is represented by an expression over
the state variables
• Implicit representation
 Reachability analysis
• State transition function: f
• Initial state: r0

• States reachable from r0

• Image of r0 under f
• States reachable from set rk
• Image of rk under f
• Iteration
• rk+1 = rk U ( image of rk under f)
• Convergence
• rk+1 = rk for some k
Example
 Example
• Image of p’q’ under f:
• When ( p = 0 and q = 0 ), f reduces to [ x’ x ]T
• Image is [ 0 1 ]T U [ 1 0 ]T
• States reachable from the reset state:
• (p = 1; q = 0) and ( p = 0; q = 1)
• r1 = p’q’ + pq’ + p’q = p’ + q’
• States reachable from r1:
• [ 0 0 ]T U [ 0 1 ] T U [ 1 0 ] T
• Convergence:
• s0 = p’q’; s1 = pq’; s2 = p’q;
 Completing the extraction
• Determine state set
• Vertex set

• Determine transitions and I/O labels

• Edge set
• Inverse image computation
• Look at conditions that lead into a given state
 Example

• Transition into s0 = p’q’

• Patterns that make f = [ 0 0 ]T are:

(x’p’q’ + pq)’(xp’ + pq’)’ = x’p’q

• Transition from state s2 = p’q under

input x’ s0 s1

• And so on … 0

s2
 Remarks

• Extraction is performed efficiently with implicit methods

• Model transition relation χ (i,x,y) with BDDs

• This function relates possible triples:
• ( input, current_state, next_state )
• Image of rk:
• Si,x ( χ(i,x,y) rk (x) )
• Where rk depends on inputs x
• Smoothing on BDDs can be achieved efficiently
 Summary

• State extraction can be performed efficiently to:

• Apply state-based optimization techniques
• Apply verification techniques

• State extraction is based on forward and backward state

space traversal:
• Represent state space implicitly with BDDs
• Important to manage the space size, which grows exponentially
with the number of registers