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SAR ADC 05jan

The document provides an overview of the Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), detailing its components such as the comparator, sample and hold circuit, and DAC array, which work together to convert analog signals to digital values. It includes specifications for the SAR ADC, such as process node, speed, and power dissipation, as well as details on the strong-arm comparator used within the ADC. Additionally, it discusses the calculation of Signal-to-Noise and Distortion Ratio (SNDR) and the design considerations for the sample and hold circuit, comparator, and DAC.

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ashish agarwal
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8 views9 pages

SAR ADC 05jan

The document provides an overview of the Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), detailing its components such as the comparator, sample and hold circuit, and DAC array, which work together to convert analog signals to digital values. It includes specifications for the SAR ADC, such as process node, speed, and power dissipation, as well as details on the strong-arm comparator used within the ADC. Additionally, it discusses the calculation of Signal-to-Noise and Distortion Ratio (SNDR) and the design considerations for the sample and hold circuit, comparator, and DAC.

Uploaded by

ashish agarwal
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PPTX, PDF, TXT or read online on Scribd
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SAR ADC

Presented bY SAURABH
GAIROLA AND CHANDAN
MEHTA
Block diagram of SAR ADC
comparator
Sample and hold
The comparator in a SAR ADC compares
the input voltage (VinV_{in}Vin​) with
The Sample and Hold (S/H) circuit in a SAR
the reference voltage
ADC captures the analog input signal and
(VDACV_{DAC}VDAC​) generated by the
holds it constant during the conversion
DAC. It outputs a binary decision (high
process. This ensures stable input for
or low) that guides the Successive
accurate comparisons and prevents errors
Approximation Register to adjust the
SAR logic
caused by changes in the signal while the
digital code, ensuring accurate
ADC determines the digital output.
conversion of the analog input to a
digital value. The SAR logic/register controls the
conversion process in a SAR ADC. It
iteratively adjusts each bit of the digital
output, starting from the MSB to the LSB,
based on the comparator's decision. The
SAR register updates the digital code to
refi ne the approximation, storing the
fi nal result once all bits are processed.

DAC array

The DAC array in a SAR ADC converts the


digital code from the Successive
Approximation Register into an analog
reference voltage (VDACV_{DAC}VDAC​) .
This reference voltage is compared with
the input voltage (VinV_{in}Vin​) by the
comparator during each iteration,
enabling the ADC to refi ne the digital
output bit by bit for accurate conversion.
Specification of
SAR
Process node 180nm

Speed(KS/S) 100

ENOB 11.74

SNDR(dB) 70.3

Power dissipation(mW) <0.077

Vdd(v) 1.3

FOM(fj/conv-step) 144

Resolution 12

INPUT FREQUENCY <10KHz

Input signal range (0-1.3)V


Strong arm comparator

Working of a Strong-Arm Comparator


A strong-arm comparator is a high-speed, low-power dynamic comparator commonly used
in ADC circuits (especially SAR ADCs). It is a clocked comparator, meaning it operates in
distinct precharge and evaluation phases.

Circuit Components and Structure

A typical strong-arm comparator consists of:


1.Input Differential Pair (M1 & M2 - NMOS): Compares the input voltages.
2.Cross-Coupled Inverters (M3, M4 - NMOS & M5, M6 - PMOS): Provides positive feedback
for regeneration.
3.Precharge PMOS Transistors (M7, M8, M9, M10): Precharges output nodes before
evaluation.
4.Tail Current Source (M11 - NMOS): Controls current flow and sets gain.

.
Specification of strong-arm latch automated design

Parameters Specification Result

Offset voltage 0.5mv 0.46mV

Clock period 1GHz 1GHz

Power 80uW 65uW

Delay 120ps 152ps

Kickback noise 0.01mv 0.001mV


Schematic
Calculation of SNDR for entire ADC

1) INL and DNL


2) Quantization noise
3) Comparator noise(kickback and thermal noise)
4) Sample and hold circuit noise(Thermal noise and harmonic distortion)
5) Gain error in DAC
6) Noise from the previous circuitry
7) Others(clock jitter, Flicker noise)

For the EEG signal SNDR should be more than 70 db for reliable operation
N=(70-6.02)/1.6=11.78
N=12 bits

Noise from previous circuitry <=50n v^2


Quantization noise=(del)^2/12=7.152n v^2

Noise + Distortion power=(A^2/2)/10^(SNDR/10)=84.5n V^2

It sets limit on other noise source


Sample and hold noise +comparator noise +other non linearilties<=(84.5-50-7.152)=27 n V^2
Designing of sanple
Designing of Designing of DAC
and hold by
Comparator by and finding
considering(C)
timing budget,noise reference switches
thermal noise and(R)
and power by considering gain
SNDR optimization
consideration error compensation
by fft calculation

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