Lecture 2.1.1 (Design of Control Unit-Hardwired Control Unit)
Lecture 2.1.1 (Design of Control Unit-Hardwired Control Unit)
ASSISTANT PROFESSOR
BE-CSE
DESIGN OF CONTROL
UNIT
Two decoders, sequence counter and logic gates make up a Hardwired Control.
The instruction register stores an instruction retrieved from the memory unit
(IR).
An instruction register consists of the operation code, the I bit, and bits 0
through 11.
A 3 x 8 decoder is used to encode the operation code in bits 12 through 14.
The decoder’s outputs are denoted by the letters D0 through D7.
The bit 15 operation code is transferred to a flip-flop with the symbol I.
The control logic gates are programmed with operation codes from bits 0 to 11.
The sequence counter (or SC) can count from 0 to 15 in binary.
Designing of Hardwired Control Unit
The following are some of the ways for constructing hardwired control logic that
have been proposed:
The basic data for control signal creation is contained in the operation code of an
instruction. The operation code is decoded in the instruction decoder. The
instruction decoder is a collection of decoders that decode various fields of the
instruction opcode.
As a result, only a few of the instruction decoder’s output lines have active signal
values. These output lines are coupled to the matrix’s inputs, which provide control
signals for the computer’s executive units. This matrix combines the decoded
signals from the instruction opcode with the outputs from that matrix which
generates signals indicating consecutive control unit states, as well as signals from
the outside world, such as interrupt signals. The matrices are constructed in the
same way that programmable logic arrays are.
Hardwired control unit
Generation of a Signal
• Control signals for instruction execution must be generated during the whole-
time range that corresponds to the cycle of instruction execution, not just at a
single moment in time.
• The control unit organises the appropriate sequence of internal states based on
the structure of this cycle.
• The control signal generator matrix sends a number of signals back to
the inputs of the following control state generator matrix. This matrix
mixes these signals with the timing signals created by the timing unit
depending on the rectangular patterns typically provided by the quartz
generator.
• The control unit is in the beginning state of new instruction, fetching
whenever a new instruction arrives at it.
Generation of a Signal
• Instruction decoding permits the control unit to enter the first state relevant to
the new instruction execution, which lasts as long as the computer’s timing
signals as well as other input signals, such as flags and state
information, stay unchanged.
• A change in any of the previously stated signals causes the control unit’s
status to change.
Result
A new corresponding input for the control signal generator matrix is formed as a
result of this. When an external signal (such as an interrupt) comes, the control
unit enters the next control state, which is concerned with the response to the
external signal (for example, interrupt processing). The computer’s flags and
state variables are utilised to choose appropriate states for the cycle of instruction
execution.
The cycle’s last states are control states that begin fetching the program’s next
instruction: sending the program’s counter content to the address of the main
memory buffer register and then reading the instruction word into the
computer’s instruction register. The control unit enters an OS state, where it
waits for the next user directive when the running instruction is the stop
instruction, which terminates programme execution.
Advantages of Hardwired Control Unit
Reference Books:
J.P. Hayes, “Computer Architecture and Organization”, Third Edition.
Mano, M., “Computer System Architecture”, Third Edition, Prentice Hall.
Stallings, W., “Computer Organization and Architecture”, Eighth Edition,
Pearson Education.
Text Books:
Carpinelli J.D,” Computer systems organization &Architecture”, Fourth
Edition, Addison Wesley.
Patterson and Hennessy, “Computer Architecture”, Fifth Edition Morgaon
Kauffman.
Reference Website:
https://www.youtube.com/watch?v=MxvZQLR6zqM
https://www.youtube.com/watch?v=gXXVX64yhME
https://youtu.be/1q2JKX3qg-4?si=dUjGIZjK8JVg78Xy