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Lecture 2.3.4 (Interrupt Driven, DMA)

The document discusses modes of data transfer in computer systems, specifically focusing on Interrupt-driven I/O and Direct Memory Access (DMA). It explains how Interrupt-driven I/O allows peripherals to signal the CPU for data transfer, enhancing efficiency, while DMA enables direct communication between peripherals and memory, freeing the CPU for other tasks. The document also outlines the operations, advantages, and disadvantages of both methods, along with the functioning of DMA controllers.

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95 views21 pages

Lecture 2.3.4 (Interrupt Driven, DMA)

The document discusses modes of data transfer in computer systems, specifically focusing on Interrupt-driven I/O and Direct Memory Access (DMA). It explains how Interrupt-driven I/O allows peripherals to signal the CPU for data transfer, enhancing efficiency, while DMA enables direct communication between peripherals and memory, freeing the CPU for other tasks. The document also outlines the operations, advantages, and disadvantages of both methods, along with the functioning of DMA controllers.

Uploaded by

aashishmahajan300
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© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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University Institute of Engineering

Department of Computer Science & Engineering

COMPUTER ORGANIZATION & ARCHITECTURE


(23CST-204/23ITT-204)

ER. SHIKHA ATWAL


E11186

ASSISTANT PROFESSOR

BE-CSE
MODES OF TRANSFER

Data transfer to and from the peripherals may be done in any of


the three possible ways
1.Programmed I/O
2.Interrupt-driven I/O
3.Direct memory access (DMA)
2. Interrupt-driven I/O
Interrupt driven I/O is an alternative scheme dealing with I/O. Interrupt I/O is
a way of controlling input/output activity whereby a peripheral or
terminal that needs to make or receive a data transfer sends a signal. This
will cause a program interrupt to be set.
At a time appropriate to the priority level of the I/O interrupt relative to the
total interrupt system, the processors enter an interrupt service routine. The
function of the routine will depend upon the system of interrupt levels
and priorities that is implemented in the processor. The interrupt
technique requires more complex hardware and software, but makes far
more efficient use of the computer’s time and capacities. Figure below shows
the simple interrupt processing.
Isolated I/O Memory Mapped I/O
Isolated I/O uses separate memory Memory mapped I/O uses memory
space. from the main memory.
Limited instructions can be used. Any instruction which references to
Those are IN, OUT, INS, OUTS. memory can be used.
The address for Isolated I/O devices Memory mapped I/O devices are
are called ports treated as memory locations on the
memory map.

For input, the device interrupts the CPU when new data has arrived and is
ready to be retrieved by the system processor. The actual actions to perform
depend on whether the device uses I/O ports or memory mapping.
For output, the device delivers an interrupt either
when it is ready to accept new data or to
acknowledge a successful data transfer.
Memory-mapped and DMA-capable devices
usually generate interrupts to tell the system they
are done with the buffer.
Here the CPU works on its given tasks
continuously. When an input is available, such as
when someone types a key on the keyboard, then
the CPU is interrupted from its work to take care
of the input data. The CPU can work continuously
on a task without checking the input devices,
allowing the devices themselves to interrupt it
as necessary.
Basic Operations of Interrupt

1.CPU issues read command.


2.I/O module gets data from peripheral whilst CPU does other work.
3.I/O module interrupts CPU.
4.CPU requests data.
5.I/O module transfers data.
Interrupt Processing

1.A device driver initiates an I/O request on behalf of a


process.

2.The device driver signals the I/O controller for the proper
device, which initiates the requested I/O.

3.The device signals the I/O controller that is ready to


retrieve input, the output is
complete or that an error has been generated.

4.The CPU receives the interrupt signal on the interrupt-


request line and transfer control over the interrupt handler
routine.
5. The interrupt handler determines the cause of the
interrupt, performs the necessary processing and executes a
“return from” interrupt instruction.

6.The CPU returns to the execution state prior to the


interrupt being signalled.

7.The CPU continues processing until the cycle begins


again.
Advantages of Interrupt-Driven I/O

 Fast
 Efficient

Disadvantages of Interrupt Drive I/O

 can be tricky to write if using a low-level language


 can be tough to get various pieces to work well together
 usually done by the hardware manufacturer / OS maker, e.g. Microsoft
3. Direct Memory Access (DMA)
The data transfer between a fast storage
media such as magnetic disk and memory
unit is limited by the speed of the CPU.
Thus we can allow the peripherals directly
communicate with each other using the
memory buses, removing the intervention of
the CPU. This type of data transfer
technique is known as DMA or direct
memory access. During DMA the CPU is
idle and it has no control over the memory
buses. The DMA controller takes over the
buses to manage the transfer directly
between the I/O devices and the memory
unit.
DMA

 Large blocks of data transferred at a high speed to or from high-speed


devices, magnetic drums, disks, tapes, etc.
 DMA controller Interface that provides I/O transfer of data directly to and
from the memory and the I/O device
 CPU initializes the DMA controller by sending a memory address and the
number of words to be transferred
 Actual transfer of data is done directly between the device and memory
through DMA controller -> Freeing CPU for other tasks

The transfer of data between the peripheral and memory without the interaction
of CPU and letting the peripheral device manage the memory bus directly is
termed as Direct Memory Access (DMA).
The two control signals Bus Request and Bus
Grant are used to fascinate the DMA transfer.
The bus request input is used by the DMA
controller to request the CPU for the control of
the buses. When BR signal is high, the CPU
terminates the execution of the current
instructions and then places the address, data,
read and write lines to the high impedance state
and sends the bus grant signal. The DMA CPU bus signal for DMA transfer
controller now takes the control of the buses and
transfers the data directly between memory and
I/O without processor interaction.
When the transfer is completed, the bus request signal is made low by DMA. In
response to which CPU disables the bus grant and again CPU takes the control of
address, data, read and write lines.
The transfer of data between the memory and I/O of course facilitates in two ways
which are DMA Burst and Cycle Stealing.

DMA BURST: The block of data consisting a number of memory words is


transferred at a time.
CYCLE STEALING: DMA transfers one data word at a time after which
it must return control of the buses to the CPU.

 CPU is usually much faster than I/O (DMA), thus CPU uses the most of the
memory cycles
 DMA Controller steals the memory cycles from CPU
 For those stolen cycles, CPU remains idle
 For those slow CPU, DMA Controller may steal most of the memory cycles
which may cause CPU remain idle long time
DMA CONTROLLER

The DMA controller communicates with the CPU through the data bus and control
lines. DMA select signal is used for selecting the controller, the register select is
for selecting the register.
When the bus grant signal is zero, the CPU communicates through the data bus to
read or write into the DMA register. When bus grant is one, the DMA controller
takes the control of buses and transfers the data between the memory and I/O.
Block diagram of DMA controller
The address register specifies the desired location of the memory which is
incremented after each word is transferred to the memory.
The word count register holds the number of words to be transferred which is
decremented after each transfer until it is zero. When it is zero, it
indicates the end of transfer.
After which the bus grant signal from CPU is made low and CPU returns to its
normal operation. The control register specifies the mode of transfer which is
Read or Write.
DMA TRANSFER

 DMA request signal is given from I/O device to DMA controller.


 DMA sends the bus request signal to CPU in response to which CPU disables its
current instructions and initialize the DMA by sending the following information.
oThe starting address of the memory block where the data are available (for
read) and where data to be stored (for write)
oThe word count which is the number of words in the memory block
oControl to specify the mode of transfer
oSends a bust grant as 1 so that DMA controller can take the control of the
buses
oDMA sends the DMA acknowledge signal in response to which
peripheral device puts the words in the data bus (for write) or receives a word
from the data bus (for read).
DMA transfer in a
computer system
DMA OPERATION

 CPU tells DMA controller:


oRead/Write
oDevice address
oStarting address of memory block for data o Amount of data to be
transferred
 CPU carries on with other work
 DMA controller deals with transfer
 DMA controller sends interrupt when finished
References

Reference Books:
 J.P. Hayes, “Computer Architecture and
Organization”, Third Edition.
 Mano, M., “Computer System Architecture”, Third
Edition, Prentice Hall.
 Stallings, W., “Computer Organization and Architecture”, Eighth Edition,
Pearson Education.

Text Books:
 Carpinelli J.D,” Computer systems organization &Architecture”, Fourth
Edition, Addison Wesley.

 Patterson and Hennessy, “Computer Architecture”, Fifth Edition Morgaon


Kauffman.
Other References

 http://www.ecs.csun.edu/~cputnam/Comp546/Input-Output-Web.pdf
 http://www.ioenotes.edu.np/media/notes/computer-organization-and-architec
ture- coa/Chapter7-Input-Output-Organization.pdf
 https://www.geeksforgeeks.org/io-interface-interrupt-dma-mode/
 I/O Interface (Interrupt and DMA Mode) - GeeksforGeeks

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