AVR Architecture

Dr. R.Girisha
Professor,
Dept. of C.S & E.,
P. E. S. College of Engineering, Mandya.
Atmel Atmega32
 Central Processing Unit
 Arithmetic Logic Unit (ALU) performs the actual arithmetic, logical,
and bit-functions
 Memory – SRAM, EEPROM, Flash, etc.
 Clock circuit – internal/external
 I/O – Input/Output; video, serial, parallel, USB, SCSI, etc.
AVR architecture
o Harvard architecture
 supports parallelism
 Separate memories for program
& data
 Next instruction is fetched while
current is executed
 Fast access register file with
32x8-bit general purpose
register,
Atmel Atmega32 highlights
o An 8-bit microcontroller featuring:
 3 separate on-chip memories (Harvard architecture)
 2KB SRAM (for data – volatile; data lost on power off)
 1KB EEPROM (for persistent data storage – holds data after power off)

Native data size is 1 byte (SRAM and EEPROM)

 32KB Flash (organized as 16K of 16-bit words for persistent program code)

16-bit data addressing




8-pin I/O ports named A, B, C, and D, configurable as:

 Up to 64 KB (216 bytes) of data memory can be accessed

 Digital input (for reading discrete external signals on each pin (0v or 5v)
as data values 0 or 1)
 Digital output (for writing binary data values as discrete output signals (0v
or 5v)
 Analog input (for reading continuous external signals (0v-5v) as data
values)
 Serial/Parallel (for reading or writing streams of bytes)
 Pulse accumulator (for counting #changes of external signals)
Von Neumann Model for Stored Program Computers
Harvard Architecture
The Atmega32 design is based on a Harvard Architecture:

o Assigns data and program

instructions to different memory
spaces.
Program data occupies a different and
separate memory from the program itself.


o Each memory space has a separate

bus, allowing:
Different timing, size, and structure for
program instructions and data


Concurrent access to data and instructions

(increases speed)


Clear partitioning of data and instructions

(better security)

Microprocessors use a von Neumann Architecture
o Data and instructions are both stored in the same main memory
o The content of any part of memory is addressable by location
without regard to what is stored in that location – program or data
o Instructions are executed sequentially. In case of accidental or
intentional programming errors, data can be executed – a common
attack used by viruses

Data

CPU Main Memory

+
Program
Word length & Bits
o Word length
 Number of bits the CPU can process at any one time (e.g. 16, 32, 64). Also
affects the number of addressable memory locations.
o BIT
 Binary Digit - 0 or 1 that combine to form a “word”
o Byte
 Eight bits together that represent a single character of data.
o Bus
 Physical wiring connecting computer components
o Bus Width
 Number of bits a bus line can transfer at one time (e.g. 16, 32, 64)
Example Memory Components:
o Volatile:
 Random Access Memory (RAM):
 DRAM "dynamic"

 SRAM "static"

o Non-volatile:
 Read Only Memory (ROM):
 Mask ROM "mask programmable"

 EPROM "electrically programmable"

 EEPROM "erasable electrically programmable"

 FLASH memory - similar to EEPROM with programmer integrated on

chip Page 10
Volatile Memory Comparison
o SRAM Cell o DRAM Cell

word line word line

bit line bit line

 Larger cell  lower density,

bit line

 Smaller cell  higher density,

higher cost/bit lower cost/bit
 No refresh required  Needs periodic refresh, and
 Simple read  faster access refresh after read
 Standard IC process  natural  Complex read  longer access
time
for integration with logic
 Special IC process  difficult to
FLASH Memory
o Electrically erasable
o In system programmability and erasability (no special
system or voltages needed)
o On-chip circuitry (FSM) to control erasure and programming
(writing)
o Flash memory provides exciting opportunities to increase
the flexibility of an embedded product.
o Flash Memory is solid state non-volatile memory.
o It stores electrical charges rather than magnetic media.
o Flash memory is light, compact, energy efficient and less
expensive.
o It is a ideal storage medium for digital camera, smart card
FLASH Memory
o Flash Memory
 Like EEPROM (electrically erasable and programmable read-only
memory).
 Also used as rewritable ROM in embedded systems

o From an embedded system designer’s perspective

 the key difference between flash memory and EEPROM is that flash
devices are block structured; that is, while flash memory locations are
individually programmable, they are not individually erasable the way
they are with EEPROM.
 Flash memory is erased in sections whose sizes and locations in the chip
are defined by the part’s manufacturer.
 As a result, once a flash memory location is programmed, the entire
section containing the location must be erased before that location can
AVR Memory architecture
oAn AVR microcontroller has three types of memory
 Flash:
 Non volatile memory for storing the program. ATmega32 has
32KB of Program memory.

 RAM:
 Volatile memory for storing the runtime state of the program
being executed. ATmega32 has 2KB bytes of RAM memory.

 EEPROM:
 Electrically Erasable Programmable ROM. Is a non volatile
memory. Individual bytes can be erased and rewritten. Used to
store semi permanent data. ATmega32 has 1KB of data EEPROM.
Programs are stored here

Temporary data is stored here

Permanent data is stored here

AVR Memory architecture
3 Separate on-chip memories
o 2KB SRAM
 For temporary data storage
 Memory is lost when power is shut off (volatile)
 Fast read and write
o 1KB EEPROM
 For persistent data storage
 Memory contents are retained when power is off (non-volatile)
 Fast read; slow write
 Can write individual bytes
o 32KB Flash Program Memory
 Used to store program code
 Memory contents retained when power is off (non-volatile)
 Fast to read; slow to write
 Can only write entire “blocks” of memory at a time

Flash Program Memory layout
o There are 32KB of program
Reset and interrupt vector section
memory (Flash memory)
 Organized as 16K 2-byte words
42 words (84 bytes)
$002A

 Because program instructions are either

2 or 4 bytes long
o Each word (not byte) in memory
has a unique address
 Beginning address $0000
 Ending address $3FFF

$3C00 o Some memory is reserved or

protected
 First 42 words (reserved)
1024 words (2048 bytes)
Registers are special-purpose memory
o There are relatively few
registers
o Directly accessed by the
CPU/ALU (very fast R/W)
o Registers are used to contain:
 address of the next instruction to fetch
from program memory
 machine instruction to be executed
 “input” data to be operated upon by the
ALU
 “output” data resulting from an ALU
operation
 Status of an ALU operation
General Purpose Registers
o There are 32 8-bit GP
registers R0-R31
 Used as accumulators – for most

math and logic

o X, Y, Z are 16-bit registers

that overlap R26-R31
 Used as address pointers

 Or to contain larger values (>255)

AVR Memory architecture Data RAM
o The data memory
comprises of three
sections
 General Purpose Registers
(GPRs)
 I/O memory (Special
function Registers)
 Internal data SRAM
Data RAM General Purpose Registers(GPRs)
o There are 32 General
purpose registers in
ATmega32
o Numbered from R0 to R31
o Located in the lowest
location of memory address
o All registers are 8 bit
o Used by CPU to store data
temporarily
o Can be used by all
arithmetic and logic
operations
Data RAM General Purpose Registers(GPRs)
o The GPRs take location
address from $00-$FF in the
data memory space
regardless of the AVR chip
number.
o Register operations are
faster.
o Fetching operands from
register, performing the
operation and storing the
result in memory happens in
one clock cycle
o Registers from R26 to R31
can be paired as three 16 bit
AVR General Purpose Registers
oR26-R27  X register

oR28-R29  Y register

oR30-R31  Z register

oThese registers can

be used for storing
(16-bit) address of
memory locations for
indirect addressing
of data
Special-purpose registers

 Stores return address of

o Stack pointer (SP, 16-bit)

subroutine/interrupt calls
 Storing temporary data
and local variables
o Program counter (PC, 16-
bit)
 Holds address of next program
instruction to be loaded and
executed
 Automatically incremented when
the ALU executes an instruction

o Status Register (SREG, 8-

bit)
Data RAM I/O Memory
o Dedicated to special functions
such as status register, timer,
serial communication etc.
o Function of an I/O register and
its address is fixed by the CPU
designer and cannot be
changed.
o Number of I/O registers can vary
with different microcontroller
o However, all AVRs have at least
64bytes of I/O memory.
o ATmega32 has 64 bytes of I/O
memory
Data RAM I/O Memory
Data RAM Internal data SRAM
o Used for storing data and
parameters
o Generally called ‘scratch pad’
o Each location can be
accessed by its address.
o 8 bit wide.
o Any data of 8 bit wide can be
stored in it, may it be data or
address.
o Size of SRAM can vary from
chip to chip.
o ATmega32 has 2KB of data
SRAM.
AVR Memory of typical microcontrollers
ATmega32
AVR Status Register - SREG
o Flag register to indicate arithmetic conditions such as
carry bit
o Flag register in AVR is called Status Register – SREG
 An 8-bit register
 In ATmega32 SREG has data memory address of $5F and I/O
address of $3F
 The function of each bit is as follows...
D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

SREG($5F)
AVR Status Register-SREG C- Carry flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o C flag is set whenever there is a carry out from the D7 th

 The flag is affected after an 8 bit addition or subtraction

bit

 Is used to detect errors in unsigned arithmetic operation

AVR Status Register - SREG Z - Zero flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o The zero flag reflects the result of an arithmetic or logic

 If the result is zero then Z=1 or

operation

 Z=1 if result is not zero

AVR Status Register - SREG N - Negative flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o Negative flag reflects the result of an arithmetic

 If D7th bit of the result is zero then N=0

operation

 If the D7th bit is 1 then N=1

AVR Status Register- SREG V - Overflow flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o Whenever the result of a signed number operation is too

large, and the high-order bit overflows into the sign

 Used to detect errors in signed arithmetic operation

bit(D7th bit), V flag is set.
AVR Status Register-SREG S- Sign flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o This flag is the result of EX-Oring of N and V flags.

AVR Status Register-SREG H- Half carry flag

D7 D6 D5 D4 D3 D2 D1 D0
I T H S V N Z C

o Sets whenever there is a carry from D3 to D4 during ADD

 Used in BCD arithmetic.

or SUB operation.

 Function same as that of Auxiliary carry flag in some

microprocessors