SRAM BASED FPGAs

Introduction
• SRAM based FPGAs are very popular
• Example for SRAM programming based FPGA is Xilinx Family
• In this chapter, three types of Xilinx family FPGAs are discussed
• such as Xilinx 2000, 3000 and 4000.
• An SRAM-programmable FPGA is programmed by loading
configuration memory cells from an external source.

• The configuration memory cells control the logic and interconnect

that perform the application function of the FPGA.

• There is no separate RAM area on the chip, the memory cells are
distributed among the logic they control.

• The configuration memory is written only once for each application

so, unlike commercial static RAM memory chips, high-speed read and
write is not important. Stability and density are primary concerns.
• The CMOS five transistor memory cell used in Xilinx FPGAs. The
Read/Write pass transistor (RIW) is used both to load the cell and to
read back the programming. During normal operation it is off, and the
cell holds its programming.
• The six-transistor memory cell used in CMOS memories uses the data bit in both
the true and complement form providing fast read and write times at the cost of
another transistor.

• The four-transistor memory cell often used in high-density SRAMs has polysilicon
resistors instead of the P-channel pullup transistors.

• These giga-ohm resistive paths increase sensitivity to soft errors such as alpha-
particle upsets.

• The internal signals in the memory cell in figure 2.2.1a are always connected to
one of the two power supplies with a low-resistance path, so the cell is very
 Advantages and Disadvantages of
SRAM Programming
• Volatility:
SRAM programming has an obvious drawback -- volatility. When the power is turned off, the IC loses
its programming, so an SRAM FPGA must be reprogrammed each time power is applied.

External Memory:
• A related disadvantage of SRAM programming is that it requires an external memory for
permanent storage of the program.

• Although multiple FPGAs can share a single external memory, this multiple-chip solution may be
inappropriate where board space is crucial.
• Reprogrammability: The disadvantage of volatility provides the
advantage of reprogrammability.

• Reprogrammability makes SRAM-programmable FPGAs ideal for prototype

development.

• Since the FPGA can be reprogrammed without cost. A designer can load a
design into the part, try it at-speed in the system and debug the design.

• If necessary, a modified version of the design can be loaded into the FPGA
and tried in the system without removing the chip.
Quality:

• Indirectly, reprogrammability leads to very high quality parts because each

part can be fully tested at the factory without destroying it. Every
programming point and every path is tested.

• SRAM FPGA tests cover all the typical stuck-at faults as well as many other
pattern faults that ASIC test generators might miss.
Process Leadership:

• The SRAM process used to build FPGAs is the same CMOS process used to make
ASICs and is very similar to the process used for CMOS memories, so SRAM
programmable FPGAs are among the first logic products to take advantage of
process improvements driven by semiconductor memories.

• Since improved processes are both denser and faster than older ones, those
advantages apply to SRAM programmed FPGAs as well.
Low Power
• SRAM-based FPGAs implement logic in static gates, so SRAM
programmable FPGAs have low power consumption even for very
large amounts of logic and have zero standby current.

• In contrast, EPLD-style FPGAs have passive pullup and sense amplifier

circuitry that leads to prohibitively-high static power dissipation for
high capacity or high-speed parts.
Device Architecture
 Device Architecture
• All three Xilinx FPGA families consist of an array of Configurable Logic Blocks (CLBs) embedded

in a configurable interconnect structure and surrounded by configurable I/O blocks

• Each family architecture was driven by a different set of assumptions and a different model of

use.

• These different design pressures led to different block, I/O and wiring architectures, as well as

other unique features of each FPGA.

• Family members differ in their number of blocks and I/Os, with CLB array sizes ranging from 8x8

to 24x24 blocks.

• These chips support designs in excess of ten thousand gates, with system clock speeds in the

tens of megahertz.
Xilinx 2000 FPGA –XC2000
• The Xilinx XC2000 family [Carter 1986] was the first commercially-available
FPGA.
• Introduced in 1985 and still used today, the XC2000 architecture was
developed without supporting software to verify logic density or capacity.
• The block structure was derived from a general understanding of the way
logic is decomposed in typical applications and from manual
implementations of existing MPGA designs.
• A crucial concern in the design of the XC2000 family was to build a chip that
was small enough to be manufacturable with the IC process available at the
time.
• Therefore, a smaller, slower cell was preferred to a larger, faster cell.
XC2000 CLB
 XC2000 CLB
• The XC2000 CLB combinational logic section (figure 2.3.8) consists of two
three input lookup tables producing the F and G signals.
• The two lookup table outputs can be multiplexed together to produce any
function of the four inputs on both outputs.
• Hill [1991] describes this arrangement as a single four-input lookup table with
two outputs.
• The CLB includes a single storage element that can be configured as an edge
sensitive D-type flip-flop or as a level sensitive D-type latch.
• The data input to the storage element comes from the output of the F lookup
table.
• The clock input can come from the G lookup table, the C input to the CLB or
from a separate clock input, K.
XC2000 CLB
• Either of the CLB outputs can be configured to be the result of the F
lookup table, the G lookup table or the sequential result, Q.
• The output of the flip-flop can be recycled directly to the inputs of
the lookup table, providing an efficient method of generating state
machines and counters.
XC2000 lOB
The XC2000 IO Block

• Figure shows the XC2000 110 block structure. All chip outputs can be
three stated and bidirectional.
• The three-state control can be fixed in the configuration bitstrearn to
make the block input-only or output-only, or it can come from a signal
in the FPGA interconnect, so on-chip logic can control the direction of
the 110 pads.
• The input signal can be latched in the lOB, reducing hold times for
latched inputs that would otherwise have to be wired to a CLB flip-
flop.
XC3000
 IOB of XC4000
• Signals to be output from the chip can be
registered before output and enabled by a
separate control signal.
• Outputs can be optionally pulled up or
down, and the output driver can be
configured with either fast or slow slew-
rate.
• Inputs from the pad can be brought into
the interior of the chip directly, registered
or both to facilitate multiplexed bus
interfaces.
• Furthermore, inputs can drive dedicated
decoders, built into the edge interconnect,
for fast recognition of addresses.
IOB of XC4000
• The XC4000 lOB includes boundary scan logic compatible with the
ANSI IEEE 1149.1 (JTAG) boundary scan standard [IEEE 1989]
[Maunder 1990]. The logic is not shown in figure.
• Boundary scan can check internal logic or external logic.
• Scan operations can take place before or after the FPGA is
programmed and do not interfere with the operation of the part.
• The scan path and control signals are available internally in the FPGA,
so additional test paths and registers can be implemented on
• the FPGA to make customized tests.
Wiring Architecture
• Figure shows an overview of the general-purpose interconnect in the
XC4000.
• This wiring includes single-length general-purpose interconnect, like
the XC2000 and XC3000, and double-length lines that bypass alternate
switchboxes.
• Since signal delay is more dependent on the number of pips through
which a signal passes than on the length of the segments, the double-
length lines allow a signal to travel twice the distance in the same
amount of time, or to travel a given distance in half the time.
 Switch Box Connections
• The switchbox connections in the XC4000 are
significantly fewer than those in the XC2000 and XC3000.
• Inside the switch box, each segment can connect to
three others, one on each of the other three sides of the
switchbox.
• Fewer pips means less load and faster interconnect.
• The drawback of fewer pips is that wiring may be more
difficult.
• As a result, the XC4000 has more interconnect segments
in the channel than an equivalent XC3000 would have.
 Long Line connections in XC4000 FPGA
• The XC4000 interconnect includes more long lines and
global lines than were available in the XC2000 and XC3000
for high fanout and high-speed wiring.
• Two of the long lines in each row can be configured as
three-state busses. The XC4000 long lines can be broken in
the center of the chip to provide two half-long lines to
improve routability.
• The half-long line has half the capacitance of the complete
long line, thus decreasing the delay.
• Four of the vertical long lines in figure are the global long
lines.
• Signals on global long lines can originate on-chip or off-
chip. They are driven by dedicated high-drive clock buffers
and wired through the core of the chip to all CLBs to
minimize clock skew.