Digital System Design
Dr. Hasanujjaman
Assistant Professor
Department of Electronics & Communication
Engineering
Combinational Circuit
Comparator
Multiplexer
De Multiplexer
Decoder
Encoder
Mar 6, 202 Chapter 2-i: Combinational Logic Circuits (2.1-- 2.5) PJF - 2
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One bit Comparator
One bit Comparator
Multiplexer
“Selects” binary information from one of
many input lines and directs it to a single
output line.
Also know as the “selector” circuit,
Selection is controlled by a particular set
of inputs lines whose depends on the of
the data input lines.
For a 2n-to-1 multiplexer, there are 2n data
input lines and n selection lines whose bit
combination determines which input is
selected.
Typical Application of a
Multiple Sources
MUX
Selector Single
Destination
MP3 Player
Docking Station
D0
Laptop
MUX
D1
Sound Card Y
D2
D3
Surround Sound System
Digital Selected
Satellite B A
Source
0 0 MP3
0 1 Laptop
Digital 1 0 Satellite
Cable TV 1 1 Cable TV
Multiplexer (cont.)
Multiplexer (cont.)
Combinational
Mar 6, 202 Logic
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2-to-1-Line Multiplexer
Since 2 = 21, n = 1
The single selection variable S has two values:
S = 0 selects input I0
S = 1 selects input I1
The equation:
Y = S’ I0 + SI1
The circuit:
Enabling
Decoder Circuits
I0
Y
S
I1 Combinational
Mar 6, 202 PJF - 9 Logic
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Example: 4-to-1 MUX using Cell
Library Based Design
Combinational
Mar 6, 202 Logic
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Multiplexer: Application
A
A B Y A Y
0 0 0
0 0 0
0 1 0 Y
Y = AB 1 0 0 1 B B 1
1 1 1
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What is a Demultiplexer
(DEMUX)?
A DEMUX is a digital Demultiplexer
switch with a single input Block Diagram
(source) and a multiple
outputs (destinations).
DEMUX
The select lines 1 2N
Input Outputs
determine which output (source) (destinations)
the input is connected to.
DEMUX Types N
1-to-2 (1 select line) Select
1-to-4 (2 select lines) Lines
1-to-8 (3 select lines)
1-to-16 (4 select lines)
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Typical Application of a
Single Source
DEMUX
Selector Multiple
Destinations
B/W Laser
Printer
Fax
Machine
D0
DEMUX
X D1
D2 Color Inkjet
Printer
D3
Selected
B A
Destination
Pen
0 0 B/W Laser Printer Plotter
0 1 Fax Machine
1 0 Color Inkjet Printer
1 1 Pen Plotter
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1-to-4 De-Multiplexer (DEMUX)
D0
DEMUX
D1
X
D2
D3
B A
D D D D
B A
0 1 2 3
0 0 X 0 0 0
0 1 0 X 0 0
1 0 0 0 X 0
1 1 0 0 0 X
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Decoders
A combinational circuit that converts
binary information from n coded
inputs to a maximum 2n coded
outputs
n-to- 2n decoder
n-to-m decoder, m ≤ 2n
Examples: BCD-to-7-segment
decoder, where n=4 and m=10
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Decoders (cont.)
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1-2 Decoder
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2-to-4 Decoder
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3-to-8 Decoder
address
data
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3-to-8 Decoder (cont.)
Three inputs, A0, A1, A2, are decoded into
eight outputs, D0 through D7
Each output Di represents one of the
minterms of the 3 input variables.
Di = 1 when the binary number A2A1A0 = i
Shorthand: Di = mi
The output variables are mutually
exclusive; exactly one output has the
value 1 at any time, and the other seven
are 0.
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Decoder with enable
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Implementing Boolean
functions using decoders
Any combinational circuit can be constructed
using decoders and OR gates! Why?
Here is an example:
Implement a full adder circuit with a decoder
and two OR gates.
Recall full adder equations, and let X, Y, and
Z be the inputs:
S(X,Y,Z) = X+Y+Z = m(1,2,4,7)
C (X,Y,Z) = m(3, 5, 6, 7).
Since there are 3 inputs and a total of 8
minterms, we need a 3-to-8 decoder.
Mar 6, 202
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Implementing a Binary Adder
Using a Decoder
S(X,Y,Z) = SUM m(1,2,4,7)
C(X,Y,Z) = SUM m(3,5,6,7)
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Encoder Example
Example: 8-to-3 binary encoder (octal-to-binary)
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
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Encoders
An encoder is a digital circuit that
performs the inverse operation of a
decoder. An encoder has 2n input
lines and n output lines.
The output lines generate the binary
equivalent to the input line whose
value is 1.
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Encoders (cont.)
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Encoder Example (cont.)
Mar 6, 202 PJF - 29
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Encoder Design Issues
There are two ambiguities associated
with the design of a simple encoder:
1. Only one input can be active at any given
time. If two inputs are active simultaneously,
the output produces an undefined
combination (for example, if D3 and D6 are 1
simultaneously, the output of the encoder will
be 111.
2. An output with all 0's can be generated when
all the inputs are 0's,or when D0 is equal to 1.
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Priority Encoders
Solves the ambiguities mentioned
above.
Multiple asserted inputs are allowed;
one has priority over all others.
Separate indication of no asserted
inputs.
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Example: 4-to-2 Priority
Encoder
Truth Table
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4-to-2 Priority Encoder
(cont.)
The operation of the priority encoder
is such that:
If two or more inputs are equal to 1 at
the same time, the input in the
highest-numbered position will take
precedence.
A valid output indicator,
designated by V, is set to 1 only when
one or more inputs are equal to 1. V
= D3 + D2 + D1 + D0 by inspection.
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Example: 4-to-2 Priority
Encoder
K-Maps
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Example: 4-to-2 Priority
Encoder
Logic Diagram
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