Tackling low ATPG test

coverage in Tessent

The Future, Connected

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 Importance of
Coverage

Factors Affecting Coverage

Agenda
Fault Categories for
Coverage
Improvement

Miscellaneous details
for Coverage
Improvement
 Importance of
Coverage
Stuck-At Coverage Manufactured Chips Average used Chips with Faults
99% 1M Chips 1053
95% 1M Chips 5254

• Above table shows how coverage can impact number of chips which are used with
structural faults still exist

Application Stuck-At Coverage Transition Coverage

Normal Applications 97% 85%
Life Critical Applications 99% 90%

• Above table shows the coverage to be targeted based on the chip applications

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Factors Affecting Coverage
Details
• Make design easily testable and manufactural
• Minimum clocks in the design – Ideally one
Synchronous Circuit • No combinational logic should drive set or reset
• Buffers should be used to delay clock
• Logic should not be used to delay clock

Details
• Minimal percentage of design should be of asynchronous part
• Whole asynchronous part should be in a individual block and
isolated
Asynchronous Circuit
• Asynchronous signals should not set/reset flip-flops –
Asynchronous set/reset are taken care by adding gating logic and
controlling other input by top level test pin

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Factors Affecting Coverage
Details
• There is coverage loss if feedback loops are existing in the circuit
Feedback Loops • If X is propagating in the loop tools considers it as TIEX and
coverage is impacted

Details
• If clocks of flops are not directly controlled/gated with some logic
there is coverage loss
Gated Clocks
• This is taken care by adding mux in the path and directly
propagating clock to the flops

Details
• More pins are been constrained the more coverage loss is
Pins Constraints encountered – It is taken care by reviewing all the constarints and
converting them from ‘C’ to ‘CT’ so fault category changes and
less coverage loss is encountered

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Factors Affecting Coverage
Details
• Black boxes are major source for X propagation or are X
Black Boxes generators – This is the case when atpg models for required block
is not given if all the models are given during atpg no black boxes
are encountered

Details
• There is coverage loss due to the paths which are not targeted in
Path with timing transition patterns
exceptions (at-speed) • False paths which are defined in sdc cannot be checked at
functional frequency

Details
• There is considerable affect of design rule checks on coverage
DRC’s • There are several DRC’s which should be resolved to improve
coverage like : A(RAM), C1 C6 C16 C22(Clock), D1 D12(Design),E10

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Factors Affecting Coverage
Details
• Test points are either used to improve test coverage or decrease
Test Points pattern count
• In tessent versa test points are used for both the purposes
simultaneously, to increase coverage and decrease pattern count

Details
• Coverage improvement can be done by analyzing majorly three
Fault Categories fault categories : AU - ATPG Untestable, UO – Unobservable and
UC - Uncontrollable. Command to analyze faults in detail is
report_faults -detail

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Fault Category for Coverage Improvement
Details
ATPG Untestable.
Pin Constraint(AU.PC) • Faults in this category are due to pin constraints applied in the
design

ATPG Untestable. Details

Tied Cell(AU.TC) • Faults in this category are due to tied cell in the design
Details
• This category consists of faults with non_scan cells that requires
multiple clock cycles to propagate fault to observation point.
• To target this faults set_pattern_type command is used to get the
ATPG Untestable. current sequential depth targeted by the tool
Sequential(AU.SEQ) • Use analyze_fault –observe <flop number> -display to get the
value of required sequential depth for targeting that flop
• Sequential depth is changed as per requirement and faults in this
category are targeted

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Fault Category for Coverage Improvement
Details
ATPG Untestable.
Unclassified • There is no specific method to analyze and target this fault
category for coverage improvement. This faults are analyzed using
visualizer and required actions are taken

Details
UnObservable.UO • This contains the nodes which are not observable

Details
UnControllable.UC • This contains the nodes which are not controllable

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Miscellaneous details for Coverage Improvement

Details
• The mentioned format gives pin details in the visualizer
• CV (Constrained) - If the pin is constrained then its value is
defined here or ‘-’ is mentioned if pin is having no constraints
• FV (Forbidden) - If some value is not allowed for the pin then it is
CV/FV/B mentioned here or ‘-’ is mentioned if pin is having no forbidden
value
• B (Blocked) - If the pin value is block for propagation then ‘B’ is
mentioned here or ‘-’ is mentioned if pin is having no blockage

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Miscellaneous details for Coverage Improvement
Details

• In visualizer for the clock pin two possible values are defined ‘101’
or ‘010’ where for both cases the output of flop will differ

2nd Frame
• Post Leading Edge - Transition Occurs
Event • Post Trailing Edge - Holds Value 1st Frame 3rd Frame
Simulation(Clock
Pulses) for DFF and 100 100
• ‘101’ : 1 frame(1) - Transition occurs
st
Latches 2nd frame(0) - Retains its previous value
3rd frame(1) - Transition occurs 101

100 000
• ‘010’ : 1st frame(0) - Retains its previous value
2nd frame(0) - Transition occurs
3rd frame(1) - Retains its previous value 010

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