GITAM

(Deemed to be University)
Bengaluru Campus
School of Technology

VLSI Design
EECE3051
VLSI ?
What Should be the way to learn VLSI
Design
Semiconductor Industry Development Cycle
Text Books : 1. Design through verilog HDL by T.R.
Padmanabhan
2. Fundamentals of Digital logic with
verilog by Stephen Brown

Digital Design with Verilog EEC346 5

 Module-1

Modeling Digital Circuits with HDLs

Digital Design with Verilog EEC346 6

 Module-1

 Hardware description languages, Verilog description of

combinational circuits, Verilog modules, Verilog
assignments, procedural assignments,
 modeling flip-flops using always block,
 delays in Verilog, compilation, simulation, and synthesis
of Verilog code,
 Verilog data types and operators,
 simple synthesis examples,
 Verilog models for multiplexers,
 modeling registers, counters and finite state machines
using Verilog always statements,
 behavioral and structural Verilog, testing a Verilog model
 HDL
• Hardware description language (HDL) is a
computer language used to describe the
structure and behavior of electronic circuits,
and most commonly, digital logic circuits.
• VHDL and Verilog are two HDL used widely.

Digital Design with Verilog EEC346 8

Introduction on VERILOG

Digital Design with Verilog EEC346 9

 VERILOG AS AN HDL
 Verilog is HDL - Hardware Description Language to design
the digital system.
Verilog is case sensitive (keywords are in lower case).

 Verilog is a language using which a designer can specify the

behaviour or structure or functionality of some given hardware.

 Verilog is only for Digital IC not for Analog IC.

 Verilog = Verify + Logic.

 VHDL is other hardware description language..

Digital Design with Verilog EEC346 10

 Contd….
 Virtually ever chip (FPGA, ASIC etc.) is designed in part
using one of these languages.

Verilog was introduced in 1985 by Gateway Design System

Automation.

 Verilog is an accepted IEEE standard.

 In 2001, IEEE 1364 – 2001 was approved and this is the latest
Verilog Standard.

Digital Design with Verilog EEC346 11

 Contd….
 HDL – Hardware (VLSI chip (IC)).

 Why HDL is required???????

1. All electronics circuits are mostly complicated, we learn

the electronics through drawing circuit diagram.
2. let us take an example, if the circuit is used in Pentium,
uses 10^8 transistors (100 millions). So its better to understand
Hierarchy.
3. In 8085, there is an interconnection between Register
file, ALU, Instruction Decoder, Bus Interface. Once we
understand the connections then we can open an ALU which
consists of (adder, subtractor, shift register, series of AND gates
etc.), this is known as Hierarchy.
Digital Design with Verilog EEC346 12
 Contd ….
 HDL involves two complexity parts (Design and Synthesis) .

 Therefore the Descriptions and Synthesis are two opposite

ends of the journey.

 Verilog is similar to C language but not like that because

Software is Sequential and Hardware is Concurrent.

 Verilog is synthesizable (design any circuit in gate level) while

‘C’ is not.

 What is an Electronic design????????

Digital Design with Verilog EEC346 13

 Difference between Verilog and VHDL : -
Verilog :-
It has very good acceptance in ASIC (application specific integrated
circuit), particularly lower level designs (register level transfer and below).
It results in fast simulation, relatively simple, easy in fast contacts,
especially for C Language users.
In long term might have problems with handling system level
designs.
Based on C language.
VHDL :-
It is relatively weaker in lower level designs, but superior in higher
system level design.
It results in slower simulation, but constantly improving.
It is very flexible,, but also difficult, complex character, very popular in
academia.
It is based on Ada and Pascal language.
Digital Design with Verilog EEC346 14
Contd ………..
Detail of Ada (not important for exam) -VHDL is similar to
Ada Language (Software Language). Ada is a structured,
statically typed, imperative, and object-oriented high-level
computer programming language, extended from Pascal and
other languages. Ada is mostly used for embedded systems.

Digital Design with Verilog EEC346 15

 Levels of Design Description : -

There are five levels of design descriptions i.e. –

1. Circuit level or Switch level – It is lowest level of abstraction
2. Gate level
3. Data flow
4. Behavioral level – It is highest level of abstraction
5. Overall design structure in Verilog

Digital Design with Verilog EEC346 16

1. Circuit Level or Switch Level
 A switch level circuit comprises of a net list of MOS
transistors. Two types of switches supported: ideal or resistive.
A switch is the basic element with which digital circuits
are built.
 Switches are combined to form inverters and other gates
at the next higher level of abstraction.
 Verilog has the basic MOS switches built into its constructs,
which can be used to build basic circuits like inverters, basic
logic gates, simple 1 bit dynamic and static memories.
 It can be used to built up larger designs to simulate at the
circuit level, to design performance critical circuits.

Digital Design with Verilog EEC346 17

 Example

Digital Design with Verilog EEC346 18

 2. Gate Level
 In gate level, the design is carried out in terms of basic
gates, e.g. AND gate, OR gate. Hence the circuit is described in
terms of gates.
 Here, all the basic gates are available as ready modules called
Primitives.
In gate level, gate primitives are predefined in verilog. There
are two classes of gate primitives i.e. multiple input gate
primitives and single input gate primitives.
The gate level modeling or structural modeling, is also called
akin(similar character) to building a digital circuit on a bread
board or on a PCB.

Digital Design with Verilog EEC346 19

• Gate level OR gate modeling:

Digital Design with Verilog EEC346 20

Contd ……….
 Multiple input gate primitives
include AND, NAND, NOR, XOR,
XNOR. These are multiple inputs and
one output.
Single input gate primitives include
NOT, Buffer. These have single input
and one output.
 Syntax : AND Gate
and (output , input, input);
Example:
and (c, a, b);

Syntax : OR Gate
or (output , input, input);
Example:
or (c, a, b); Digital Design with Verilog EEC346 21
 Do and Don’t do
Example:
and (c, a, b);

Example:
AND (c, a, b);

Example:
and (C, A, B);
 Keyword word / Syntax word like and, or, nand, nor, not, xor,
xnor – all should be in sentence case.
 No restrictions for I/O declarations.

Digital Design with Verilog EEC346 22

3. Data Flow
 It is the next higher level of abstraction.
 Here all operations on signal and variables are
represented by assignments (defines the continuous
functioning of the concerned block).
 To design a circuit in this abstraction level the designer
should be aware of data flow of the design.
In dataflow modeling, most of the design is implemented
using continuous assignments, which are used to drive a
value onto a net (nodes in a circuit).
 The gate level modeling becomes very complex for a VLSI
circuit, hence dataflow modeling became a very important way
of implementing the design.

Digital Design with Verilog EEC346 23

• Dataflow style modeling of OR gate:

module or_gate (c, a, b);

input a, b;
output c;
assign c= a|b;
endmodule

Digital Design with Verilog EEC346 24

 Bit-wise operator

The bitwise AND operator ( & ) compares each bit of the

first operand to the corresponding bit of the second
operand, and assign the resultant into output.
For example:

Digital Design with Verilog EEC346 25

Syntax : AND Gate
assign output = input & input;
Example:
assign c = a & b;

Syntax : OR Gate
assign output = input | input;
Example:
assign c = a | b;

Digital Design with Verilog EEC346 26

4. Behavioral Level
 It constitutes the highest level of design description; it
essentially at the system level itself.
 With the assignment possibilities, looping constructs and
conditional branching possible, the design description
essentially looks like C program.

Syntax : AND Gate

1’b0 means 1 bit in binary with value 0

Digital Design with Verilog EEC346 27

5. Overall design structure in Verilog
 The possibilities of design description statements and
assignments at different levels necessary their accommodation in
a mixed mode.

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Verilog description of combinational circuits,
Verilog modules

Digital Design with Verilog EEC346 29

 Verilog Language Concept
1. Concurrency
2. Simulation and Synthesis
3. Functional Verification
4. System Tasks
5. Programming Language Interface (PLI)

Digital Design with Verilog EEC346 30

 1. Concurrency
 In typical programming language such as C++, the code is
executed sequentially.
 However, Verilog follows concurrency. Means, there is no
specified order in assignment statement.
The order of execution is defined only by the events occurring
on the signals that the assignments are sensitive to.

Example:
xor (sum, a, b);
and (carry, a, b);
Example:
and (carry, a, b);
xor (sum, a, b);
Digital Design with Verilog EEC346 31
2. Simulation and Synthesis

Digital Design with Verilog EEC346 32

Hardware and Software
* Hardware Kit Name -> Xilinx
Family Name-> Artix -7

* Software -> Vivado (18.2 Cracked Version)

Programming Language -> Verilog
Modelling -> Gate level and behavioral level
 3. Functional Verification
 Testing is an essential ingredient of the VLSI design process
with any hardware ckt.
It has two dimension
1. functional test
2. timing test
Test Bench - Testing or functional verification is carried out by
setting up “Test Bench” for the design
It is especially applicable for Behavioral level.
Example :
1. Flipflops – Counters

Digital Design with Verilog EEC346 34

4. system tasks

• The system tasks are used to perform some

operations like displaying the messages, terminating
simulation, generating random numbers, etc.
 E.g,
$display (“a = %b”, a);
$display (“a = %h”, a);
integer value = $random;

Digital Design with Verilog EEC346 35

5. Programming Language Interface (PLI)

• Verilog PLI (Programming Language Interface)

is a mechanism to invoke C or C++ functions
from Verilog code.
• To customize the capability of the Verilog
language by defining their own system tasks
and functions.

Digital Design with Verilog EEC346 36

Module:
• A module is a basic building block that declares
the input and output signals and specifies the
internal operation of the module. It is declared
under keyword “module”.
• Used to declare the three ports
1. Input port-to entry the inputs
2. Output port-to entry the outputs
3. Inout port-to entry both inputs and outputs
Digital Design with Verilog EEC346 37
 Signifies declaration of the

Syntax module

module module name (output1, input1, input2);

input input1,input2;
Name Assign to module
output output1;
statement1; Termination of the
statement
Statement2;
……
…...
endmodule Termination of the module

Digital Design with Verilog EEC346 38

 Gate Level Modeling
AND Gate – a combinational circuit

module and_gate (c, a, b);

input a, b;
output c;
and (c, a, b);
End module

Digital Design with Verilog EEC346 39

 Gate Level Modeling-
OR Gate – a combinational circuit

module or_gate (c, a, b);

input a, b;
output c;
or (c, a, b);
end module

Digital Design with Verilog EEC346 40

 Dataflow Level Modeling
AND Gate
module and_gate (c, a, b);
input a, b;
output c;
assign c= a&b;
endmodule

Digital Design with Verilog EEC346 41

 Dataflow Level Modeling-
OR Gate
module or_gate (c, a, b);
input a, b;
output c;
assign c= a|b;
endmodule

Digital Design with Verilog EEC346 42

• Lexical Tokens
1. White space
2. Comments
3. Operators
4. Numbers
5. Strings
6. Identifiers
7. keywords

Digital Design with Verilog EEC346 43

 Strings :-
 A strings is a sequence of character enclosed within
double quotes.
 A string must be contained on a single line, i.e. it can not
be carried over of two lines with a carriage return.

Example :- “ Hello verilog world”

Digital Design with Verilog EEC346 44

 Logic values :-
 1 signifies the 1 or high or true level.

 0 signifies the 0 or low or false level.

 x represent on unknown or uninitialized value. This

corresponds to the don’t care in logic circuits.

 z represent a high impedance state.

Digital Design with Verilog EEC346 45

 Strengths :-

Verilog allows signals to have

1. logic values : Logic values are 0 , 1 , x , and z .
2. strength values. Logic strength values are used to
resolve combinations of multiple signals and to
represent behavior of actual hardware elements as
accurately as possible. Several logic strengths are
available

Verilog has 4 driving strengths, 3 capacitive strengths

and high impedance

Digital Design with Verilog EEC346 46

Strength Name Strength level Element modelled Declaration
Abbrevation
Supply Drive 7 Power supply Supply1 (su1)
connection Supply0 (su0)

Strong Drive 6 Default gate & assign Strong1 (st1)

output strength Strong0 (st0)

Pull Drive 5 Gate & assign output Pull1 (pu1)

strength Pull0 (pu0)

Large Capacitor 4 Size of trireg net Large1 (La1)

capacitor Large0 (La0)

Digital Design with Verilog EEC346 47

Contd …………..
Strength Name Strength Level Element Modelled Declaration
Abbrivation

Weak Drive 3 Gate &assign Weak1 (we1)

output strength Weak0 (we0)

Medium Capacitor 2 Size of trireg net Medium1 (me1)

capacitor Medium0 (me0)

Small Capacitor 1 Size of trireg net Small1 (sm1)

capacitor Small0 (sm0)

High Impedance 0 Tri-stated line High1 (Hi1)

High0 (Hi0)

Digital Design with Verilog EEC346 48

 Contd …………..
 When a signal line is driven simultaneously from two sources
of different strength levels, the stronger one is consider.

Example :-
If a signal line ‘P’ is driven by two sources,
Q at 1 level with strength strong1
R at 0 level with strength pull0

→ P will take which value????????

Digital Design with Verilog EEC346 49

 Data Types :-

The data handled in verilog has two categories;

1. Net data type – again two types: (i) wire and (ii) tri
2. Variable data type – Register referred as reg is variable
data type.
 It also includes reg, time, interger, real.

Digital Design with Verilog EEC346 50

Net data type

a. A net signifies a connection from one circuit unit to

another.
b. A net must be continuously driven.
c. A net carries the value of signal, it is connected to and
transmit the circuit blocks connected to it.
d. It can't store a value, and it is not a keyword.
• Example of Net type:-
 wire :- It represents a simple wire doing an interconnection.
Only one output is connected to a wire and is driven by that.
 tri :- It represent a simple signal line as wire. A tri can be
driven by more than one signal outputs

Digital Design with Verilog EEC346 51

The Verilog has following net types:

wire or tri simple interconnecting wire

wor or trior wired outputs OR together

wand or triand wired outputs AND together

tri0 pulls down when tri-stated

tri1 pulls up when tri-stated
supply0 constant logic 0 (supply strength)
supply1 constant logic 1 (supply strength)
trireg stores last value when tri-stated
(capacitance strength)
Digital Design with Verilog EEC346 52
Variable data type :-
a. It is used for storage device. It can be declared through a
keyword reg and stores the value of a logic level: 0, 1, x,
z.
b. A net or wire connected to a reg takes on the value stored
in the reg and can be used as input to other circuit
elements.
c. The output of a circuit cannot be connected to a reg.
d. The value stored in a reg is changed through a fresh
assignment in the program.

Digital Design with Verilog EEC346 53

 Scalars and Vectors :-

Scalars :- It represents a single bits whether the bit is stored,

changed or transferred.
Vectors :- It is the multiple lines carry signals in a cluster like
data bus, address bus.

Digital Design with Verilog EEC346 54

Digital Design with Verilog EEC346 55
Contd ……….
Examples :-
wire[3: 0] a; /* a is 4 – bit vector of net type, bits are
designated as a[3], a[2], a[1], a[0] */

reg[2:0] b; /* b is 4 – bit vector of reg type, bits are

designated as b[2], b[1], b[0] */

reg[4:2] c; /* c is 4 – bit vector of reg type, bits are

designated as c[4], c[3], c[2] */

Digital Design with Verilog EEC346 56

PPT page 60 to 70 have
Verilog examples to
demonstrate the use of “wire”
&
Various modeling styles of Verilog

Digital Design with Verilog EEC346 57

 Gate Level Modelling of Combinational
circuits
• Do the given exercise
• Draw the circuit diagram for
1. 1-bit Full adder
2. 4- bit full adder
3. 2:1 mux ; 4:1 mux
4. 1:2 demux; 4:1 demux
5. 2:4 decoder; 3:8 decoder
6. 4:2 encoder; 8:3 encoder
7. NAND gate- XOR gate, AND gate
8. Half adder using NAND gate
9. Full adder using NAND gate
Digital Design with Verilog EEC346 58
 Half adder

module ha (sum, carry, a, b);

input a, b;
output sum carry;
xor (sum, a, b);
and (carry, a, b);
endmodule

//ha.v
Digital Design with Verilog EEC346 59
Example: Full Adder using Gate level modeling
S=x⊕y⊕Cin
Cout=x.y+x.cin+y.cin

Digital Design with Verilog EEC346 60

Example: Full Adder using Data Flow modeling

• Full Adder Verilog code:

Digital Design with Verilog EEC346 61

Digital Design with Verilog EEC346 62
• Home work.
• Implement F= ab +c using Verilog gate level
modeling.

Digital Design with Verilog EEC346 63

• Example: Mux 8:1 using Behavioural
modelling

Digital Design with Verilog EEC346 64

• 1:4 Demux:

Digital Design with Verilog EEC346 65

Digital Design with Verilog EEC346 66
 Levels of Design Description or Verilog modeling styles
(same as page 16) : -

• We studied example of OR gate, AND gate, Half

Adder, Full Adder etc. with Gate level modeling
Digital Design with Verilog EEC346 67
• Behavioral for Half Adder:

Digital Design with Verilog EEC346 68

• Data Flow style for Half Adder:

Digital Design with Verilog EEC346 69

• Gate level modeling:

Digital Design with Verilog EEC346 70

 Delay in Verilog
• Delay in Verilog can be categorized into two models:
I. inertial delay
II. transport delay
• Transport delay: it is intended to model the delay introduced
by wiring; it simply delays an input signal by the specified
delay time.
• Inertial delay: It delays the assignment, however an input
pulse that is shorter than the delay of the assignment does
not propagate to the output.

Digital Design with Verilog EEC346 71

• Example:

Digital Design with Verilog EEC346 72

• assign #5 D = A && B;
to model an AND gate with a propagation delay of
5ns (assuming its time unit is ns).
It is inertial delay.
• Net delay: Another type of delay in Verilog which
refers to the time it takes from any driver on the net
to change value to the time when the net value is
updated and propagated further.

Digital Design with Verilog EEC346 73

• Example:

Digital Design with Verilog EEC346 74

• Various Verilog delays with example:

Digital Design with Verilog EEC346 75

• Inter-assignment delay: Going from one statement to
next first Wait for delay time. Then right hand side
(RHS) is executed and then assigned to LHS.
#5 C <= a & b;
• Intra-assignment delay: RHS is executed instantly,
then wait for delay time, then assigned in LHS.
C = #5 a & b;

Digital Design with Verilog EEC346 76

• Example 1:

Digital Design with Verilog EEC346 77

Simulation Result

Digital Design with Verilog EEC346 78

• Example 2:

Digital Design with Verilog EEC346 79

Simulation Result

Digital Design with Verilog EEC346 80

• Example 3:

Digital Design with Verilog EEC346 81

Example of Inter-assignment delay:
module del4;
integer a, b;
always b = #2 a ;
initial
begin
a =0 ; b = 0 ;
#2 a=1;
#2 a=2;
#2 a=3;
#2 a=4;
#2 a=5;
end
initial $monitor ($ time, “ a = % d, b= % d” , a, b) ;
initial # 20 $ finish ;
endmodule
Digital Design with Verilog EEC346 82
Output:

t a b
0 0 0
2 1 X
4 2 1
6 3 2
8 4 3

Digital Design with Verilog EEC346 83

 • Concept of Delay assignments :-

In delay assignment, the delay is an expression, it is evaluated

and execution delayed by the number of time steps.
Example
always #(b + c) a = a +1 ; the algebraic addition
of b and c is to be done. The incrementing value of a is assigned
to a with a time delay (b+c).

• Concept of Zero delay :-

A delay of 0 ns does not really cause any delay is known as zero
delay.

Digital Design with Verilog EEC346 84

 wait construct :-
The wait construct makes the simulator wait for the specified
expression to be true before proceeding with the following
assignment or group of assignments.

wait (alpha) assignment1; alpha is a variable, if alpha is

an expression, it is first evaluated; if true, assignment1 is carried
out.
For edge sensitive nature, it is declared as
@clk a = b; assign the value of b to a when clk changes.
Example :-
Verilog code for 4 - bit up counter with wait construct

Digital Design with Verilog EEC346 85

• Blocking and Non-blocking statement in
Verilog:

Digital Design with Verilog EEC346 86

 Verilog built-in primitive
• The built-in primitives are predefined modules which provide
a means of gate level modeling and switch level modeling.
I. Single input gate primitives have a single input and one
or more outputs. The gate primitive are not, buf, notif,
and bufif.
notif and bufif also have a control signal.
II. Multiple input gate primitives include and, or, xor, nand,
nor, and xnor. They may have multiple inputs and a
single output.

Digital Design with Verilog EEC346 87

• Important built-in primitives and syntax are:

Digital Design with Verilog EEC346 88

• buf and not gates:
These gates have one input and one or more
outputs.
The truth table:

Digital Design with Verilog EEC346 89

• tri state gates
 buf gate and not gate with tri-state are the following:
bufif1, bufif0, notif1, notif0.
 Symbol and truth table for bufif0 and notif0: (note that
the truth table is not important for exam)

 The L and H symbols have a special meaning. The L symbol

means that the output has 0 or z value. The H symbol means that
the output has 1 or z value. Any transition to H or L is treated as
a transition to x.Digital Design with Verilog EEC346 90
• Delay with tri state gates:

For tri state gates the delays associated with the control signals
can be different from those of the input as well as the output.
Expression of bufif1 with delay:

bufif1 #(1, 2, 3) g1(out, in, control)

Delay associated with positive transition (rise delay)

Delay associated with negative transition (fall delay)
Delay for the output to go to “z” state as control signal changes
from 1 to 0
Example :-
bufif1 (3,4,7) g1 (out, in, control);

Digital Design with Verilog EEC346 91

 Contd ……….
Maximum delay :- The maximum value of the delay in a batch.
Minimum delay :- The minimum value of the delay in a batch.
Typical delay :- Typical or representative value of the delay.
Example :-
and #(2:3:4) g1 (a1, a2, a3); Max = 4, Min = 2, Typ = 3

delay with both positive as well as negative transition

and #(1:2:3, 4:5:6) g1 (a1, a2, a3); Max = 3, Min = 1, Typ = 2

delay with positive transition delay with negative transition

Digital Design with Verilog EEC346 92

• and #(1:2:3, 4:5:6, 7:8:9) g1 (a1,
a2, a3);
 delay with positive transition Max = 1, Min = 2, Typ = 3
 delay with negative transition Max = 4, Min = 5, Typ = 6
 output turn off time Max = 7, Min = 8, Typ = 9
 Instance name is g1
 Output a1, inputs a2, a3.

Digital Design with Verilog EEC346 93

Strength :- When the output of two gates are joined together the
signal level is decided by the relative magnitudes of the source
impedances.
Strength of Gate Primitives:-
buf (supply1, pull0) (out, in);

strength of 1 strength of 0 state in output

state in output

Digital Design with Verilog EEC346 94

• Example of built-in primitive:

Digital Design with Verilog EEC346 95

• Net Types :-
1. Wire - A wire represents a physical wire in a circuit and is
used to connect gates or modules.
2. Wand (wired-AND) - The value of a wand depends on
logical AND of all the drivers connected to it.
3. Wor (wired-OR) - The value of wor depends on the logical
OR of all the drivers connected to it.
4. Tri (three-state) - All drivers connected to a tri must be z,
except one that determines the tri's value.
5. Supply0 and Supply1 - Supply0 and supply1 define wires
tied to logic 0 (ground) and logic 1 (power).

Digital Design with Verilog EEC346 96

Net Types :-
wand is a wire declaration, which resolves to AND logic in
case of contention.
 wor is a wire declaration, which resolves to OR logic in
case of contention.
(i) Wand type :-
When i1 = 1 and i2 = 0, the stronger signal i1 at the 1
level prevails and out = 1. The contention is resolved
according to the strengths.
When i1 = 0 and i2 = 1, both signals being equally
strong, the value of out is decided according to AND gate.

Digital Design with Verilog EEC346 97

 Contd ………..
Example 1:-
(ii) Wor type :-
When i1 = 1 and i2 = 0, the stronger signal i1 at the 1
level prevails and out = 1. The contention is resolved
according to the strengths.
When i1 = 0 and i2 = 1, both signals being equally
strong, the value of out is decided according to OR gate.
Example 2:-

(iii) Tri :- The keyword tri has a function identical to wire.

When a net is driven by more than one tri state gate, it is
declared as tri rather than as wire.

Digital Design with Verilog EEC346 98

Contd ……….
(iv) Tri0 and Tri1:-
If the output of a tri state buffer is to be pulled up to the 1
state when tri stated, it is declared as net tri1.
If the output of a tri state buffer is to be pulled up to the 0
state when tri stated, it is declared as net tri0.
Example –
tri0 o1;
tri1 o2;
wire o3;
bufif1 g0(o1,i,en), g1(o2,i,en);
bufif1 g2(o3,i,en);

Digital Design with Verilog EEC346 99

 Design of Basic Circuit -
Step 1:- Draw the circuit in terms of gates.
Step 2:- Name gates and signals.
Step 3:- Using the same nomenclature as above, do the design
description.
Step 4:- As the functional blocks like encoder, decoder, half
adder, full adder etc. gets more and more involved, treat as a
building block with corresponding inputs and outputs.
Step 5:- Make more involved circuits in terms of the building
blocks as far as possible.

Digital Design with Verilog EEC346 100

 Verilog Assignments
• Two types of assignment in the Verilog:
I. continuous assignments : wire on the left-hand side of the
assignment operator is continuously driven with the value
of the expression on the right hand side. using this
concurrent statements are run to implement
combinational circuit.
a. explicit continuous assignment:
wire C;
assign C = A || B;
b. implicit continuous assignment:
wire D = E && F;
II. procedural assignments: used in sequential logic where
the changes depends on the clock.
a. Initial – initial block execute only once at time zero
Digital Design with Verilog EEC346 101
b. always – always block loop executes over and over again
Digital Design with Verilog EEC346 102
 Behavioral Modeling :-

Operations and Assignments of Behavioral Modeling –

The design description at the behavioral level is done
through a sequence of assignments, are called procedural
assignments. The procedural assignment is characterized by the
following :
 The assignment is done using “ =” symbol (or “<=” symbol).
 An operation is carried out and the result assigned through the
“ = ” operator to an operand. Ex., N (operand) = ~ N (operator).
 The operand on the right side can be of the net or variable
type. They can be scalar or vector.
 The operator on the left side can be variable (reg) type. It can
be scalar and vector.

Digital Design with Verilog EEC346 103

Function of Behavioral Modeling –
 Design description in behavioral level is done in terms of
procedures of two types: “always” and “initial”

Initial Construct rules:-

 An initial blocks starts at time 0, executes exactly once during
a simulation, and then does not execute again.
 If there are multiple initial blocks, each blocks starts to
execute concurrently at time 0.
 Multiple behavioral statements must be grouped, using
keyword begin and end.
 If there is only one behavioral statement, grouping is not
necessary.
Digital Design with Verilog EEC346 104
// test bench
reg x, y, a,b, m;
initial
m = 1’b0; // single statement, grouping is not required
initial
begin
# 5 a = 1’b 1;
# 25 b = 1’b 0; // multiple statement
end
initial
begin
# 10 x = 1’b 0;
# 25 y = 1’b 1;
end
initial # 50 $ finish
endmodule
Digital Design with Verilog EEC346 105
Contd ………….
Time Statement executed
0 m=0
5 a=1
10 x=0
30 b=0
35 y=1
50 $ finish

Digital Design with Verilog EEC346 106

Event Control

The always block is executed repeatedly and endlessly. It is

necessary to specify a condition or a set of conditions, which
will control the system to the execution of the block. This
control can be done by event control “ @ “ .
 @ (negedge clk): executes the following block at the
negative edge of the reg (variable)
 @ (posedge clk): executes the following block at the
positive edge of the reg (variable)
 @ clk: executes the following block at both edges of the clk
 @ (posedge clk1 or negedge clk2) : Whenever the clock
clk1 changes from 0 to 1 or the clock clk2 changes from 1 to
0. one can specify more elaborate events by ORing individual
ones.

Digital Design with Verilog EEC346 107

 Contd ………………..
 @ (posedge clk1 or clk2): execute the block following if clk1
goes to 1 state or clk2 changes state (whether 0 to 1 or 1 to 0).
 @ (posedge clk1 or posedge clk2): execute the block
following if clk1 goes to 1 state or clk2 goes to 1 state.

Digital Design with Verilog EEC346 108

• Modeling Counter in Verilog: Mod-10 Counter

Module counter( clk, rst, enable, count);

Input clk, rst, enable;
Output reg [3:0] count;
always @(posedge clk)
begin
if (rst | count=4’b1001)
Count<= 4’b0000;
elseif (enable)
Count<= count+1;
end
endmodule

Digital Design with Verilog EEC346 109

• Modeling Register in Verilog: Cyclic Shift Register

Digital Design with Verilog EEC346 110

• Question:

Digital Design with Verilog EEC346 111

• 4 bit up counter:
– Positive edge triggered 4 bit up-Counter.

Digital Design with Verilog EEC346 112

• Clocked D Flip flop with positive edge trigger
 Block diagram and table:

 Verilog Model:
module dff1(CLK, D, Q);
input CLK, D;
output Q;
always @(posedge CLK)
begin
Q <= D;
end
endmodule

Digital Design with Verilog EEC346 113

• Verilog Code for a D Flip-Flop with Asynchronous Clear

Digital Design with Verilog EEC346 114

• Modeling clocked T flip-flop

module tff1(CLK, T, Q);

input CLK, T;
output Q;
always @(posedge
CLK)
begin
if (T)
Q <= ~Q;
else
Q <= Q;
end
endmodule
Digital Design with Verilog EEC346 115
 Multiple always blocks

 All the activities within an always block are scheduled for

sequential execution.
 In the figure, activity A1 accepts x as input, and it generates B
and p as output, now P and y as input to activity A2 and generates
output is C and q after activity A1 completed. Similarly for A3.
 If one or more of these are clocked events, execution may be
sequential.

Digital Design with Verilog EEC346 116

 Blocking and Non-blocking Assignment
Blocking Assignment :-
 General syntax is :
Variable_name = [delay or event_control] expression;
 The “ = ” operator is used to specify blocking assignment.
 Blocking assignment statements are executed in the order they
are specified in a procedural block.
(a) The targets of an assignment gets updated before the
next sequential statements in the procedural block is executed.
(b) They do not block execution of statements in other
procedural blocks.
 This is the recommended style for modeling combinational
logic. It also generate sequential circuit elements during synthesis.

Digital Design with Verilog EEC346 117

 Contd …….
Non – blocking Assignment :-
 General syntax is
Variable_name <= [delay or event_control] expression;
 The “ <= ” operator is used to specify non–blocking
assignment.
 Non– blocking assignments allows scheduling of assignment
without blocking execution of statements that follow within the
procedural block.
(a) The assignment to the target gets scheduled for the
end of the simulation cycle (at the end of procedural block).
(b) Statements subsequent to the instruction under
consideration are not blocked by the assignment.
(c) Allow concurrent procedural assignment, suitable for
sequential logic.
Digital Design with Verilog EEC346 118
 case statement
 The case statement is an elegant and simple construct for
multiple branching in a module.
 The keywords case, endcase and default are associated with
case construct.
 Format for case :
case (expression)
Ref1 : statement1;
Ref2 : statement2;
Ref3 : statement3;
…….
…….
default : statementd;
endcase
Digital Design with Verilog EEC346 119
 Contd ………..
 First expression is evaluated, if the evaluated value matches
ref1, statement1 is executed and simulator exists the block; else
expression is compared with ref2, statement2 is executed and so
on.
 If none of ref1, ref2, etc., matches the value of expression, the
default statement is executed.

Digital Design with Verilog EEC346 120

 if and if-else Construct
 The if construct checks a specific condition and decides
execution based on the results.
…….
assignment1;
if(condition)assignment2;
assignment3;
assignment4;
……
 In the above, after execution of assignment1, the condition is
checked. If it satisfied, assignment2 is executed after that
assignment3 and assignment4 is executed; if not, it is skipped and
assignment3 and assignment4 is executed.

Digital Design with Verilog EEC346 121

Contd ………..

Flowchart of the if loop

Digital Design with Verilog EEC346 122

 Contd ………
 If the number of assignments associated with the if condition is more than 1, then
whole of them can be grouped within a begin-end block.
The if-else loop is more useful as compared to if loop alone.
………..
assignment1;
if(condition)
begin // alternative1
assignment2;
assignment3;
end
else
begin // alternative2
assignment4;
assignment5;
end
assignment6;
…………..
Digital Design with Verilog EEC346 123
Contd …………

Flowchart of the if-else loop

Digital Design with Verilog EEC346 124
Contd ………..
 After the execution of assignment1, if the condition is
satisfied, alternative1 is followed and assignment2 and
assignment3 are executed proceeds with assignment6.
assignment4 and assignment5 is skipped.
 If the condition is not satisfied, alternative2 is followed and
assignment4 and assignment5 are executed proceeds with
assignment6. assignment2 and assignment3 is skipped.
Example :
Verilog code of 1-to-4 DEMUX using if and if-else
construct.

Digital Design with Verilog EEC346 125

 assign-deassign construct
 The assign – deassign constructs allows continuous assignments within a
behavioral block.
always@(posedge clk) a = b;
In the above declaration, at the positive edge of clk the value of b is assigned to
a and value of a remains unchanged in negative edge of clk.
always@(posedge clk) assign c = d;
In the above declaration, at the positive edge of clk the value of d is assigned to
c in continuous manner. If any changes in d directly changes will be assigned to
c. so the declaration can be changes to
always
begin
@(posedge clk) assign c = d;
@(negedge clk) deassign c;
end
By the declaration of deassign in negative edge of clk, the value of c is
removed.
Digital Design with Verilog EEC346 126
 Contd ………….
 The assignment to c in the above case is known as
“procedural continuous assignment”.

Example
Verilog code 1-to-4 DEMUX using procedural
continuous assignment.

Digital Design with Verilog EEC346 127

 Modeling of Data flow level

Continuous Assignment Structure:-

The data flow format for two input AND gate is given by;
assign c = a && b;
 Here, assign is the keyword which carrying out the
assignment operation. This type of assignment is called a
continuous assignment.
 “a and b” are the operands and “&&” is a logic operator.
 In general an operand can be one of the following; continuous
number, net of a scalar or vector type, register variables of a
scalar or vector type, memory element.
Example: AND gate with data flow level

Digital Design with Verilog EEC346 128

 Contd ………
An A-O-I gate circuit:

data flow level assignment statement is;

assign e = a && b, f = c && d, g1 = e | f, g = ~ g1;
assign e = a && b, f = c && d ;
assign g1 = e | f, g = ~ g1;
// commas separate the different assignment and semicolon
terminates an assignment statement.
Digital Design with Verilog EEC346 129
 Contd ………

 assign e = a && b;
assign f = c && d ;
assign g1 = e | f;
assign g = ~ g1;
Example: write the verilog code for A-O-I gate in data flow level.
(a) Combining assignment and Net declaration:
The assignment statement can be combining with the net
declaration itself making the assignment implicit in the net
declaration itself.
The AND gate can be declared as;
wire c;
assign c = a && b; both can be combined as
wire c = a && b;
Digital Design with Verilog EEC346 130
 Contd ……
Verilog code for A-O-I gate using combining assignment

module aoigate(g,a,b,c,d);
input a,b,c,d;
output g;
wire g;
wire e = a && b;
wire f = c && d ;
wire g1 = e | f;
assign g = ~ g1; Digital Design with Verilog EEC346 131
 Contd …………
(b) Continuous Assignment and Strength :
A net to which a continuous assignment is being made can
be assigned strength for its logic levels. The procedure is similar to
the strength allocation to the outputs of primitives.
The output of A-O-I gate (g) can be combined with the
wire declaration into a single statement as
wire (pull1, strong0) g = ~ g1;

Digital Design with Verilog EEC346 132

 Contd ……..
Verilog code for A-O-I gate using combining assignment

module aoigate(g,a,b,c,d);
input a,b,c,d;
output g;
wire g;
wire e = a && b;
wire f = c && d ;
wire g1 = e | f;
= ~Design
assign (pull1, strong0) gDigital g1;with Verilog EEC346 133
 Delay and Continuous Assignment

Delays can be incorporated at the data flow level in

different ways
wire c, a, b;
assign #2 c = a & b;
Here the assignment takes effect with a time delay of 2 time steps
(i.e. if a and b changes then c will be change but after 2 ns delays) .
Example
If a changes at 0ns, 2ns, 5ns, 8ns, 9ns, 12ns and 13ns
b changes at 0ns, 2ns, 6ns, 8ns and 13ns
Then c changes in 2ns, 4ns, 7ns, 8ns, 10ns, 11ns, 14ns
respectively.

Digital Design with Verilog EEC346 134

 Assignment to vectors
Concatenation of vectors :-
 Concatenation is used for combining two or more vectors to
form a single vector.
 In verilog, concatenation operator can be used to either join
two or more vectors/split a vector into small subvectors.
 The concatenated vector is enclosed within braces {,}. Commas
separate the components.
Example
{a, b, c} : If a is 8 bit, b is 4 bit and c is a scalar. Then
concatenated vector of 13 bit width.
 When it is necessary to replicate vectors, scalars etc., to form
other vectors the same can be arrived in a compact manner using
repetition multiplier.
Digital Design with Verilog EEC346 135
 Contd ……..
Example
{2{p}} = {p, p}
{2{p}, q} = {p, p, q }
{a, 3{{b, c}, d}} = {a, b, c, b, c, d, b, c, b, c, d, b, c, b, c, d }
 The concatenation expression can be either an identifier or a
sized number. Unsized number are illegal because the size of all
operands is required to calculate the size of an entire
concatenation.

Digital Design with Verilog EEC346 136

 Operators :-

 Unary Operator :- this operator associated with a single

operand (data items).
+ A, - B
 Binary Operator :- This operator associated with two
operands (data items).
A + B, A – B, A % (modulus) B, a* * (exponentiation)3,
(a+b) / (a - b)
 Ternary Operator :- This operator associated with three
operands. The two operators (? and : ) together constitute a
ternary operation. The two operators separate the three
operands.
a?b:c
Digital Design with Verilog EEC346 137
Verilog Operators

Digital Design with Verilog EEC346 138

Digital Design with Verilog EEC346 139
 Unary sign operators indicates sign, e.g., - 5, + 4.
 Reduction and operators reduces the operand by taking the
AND of each bit present in the operand. E.g., c = &4’b1100
evaluates to c = 1’b0 as 1’b1 & 1’b1 & 1’b0 & 1’b0 is 0
 Logical negative ! inverts only least significant bit. i.e., a =
00; b = ! a = 01;
 bitwise negation ~ inverts all bits. i.e., a = 00; c = ~ a =
11;

Digital Design with Verilog EEC346 140

 Operators
Verilog provides different types of operators i.e. arithmetic,
logical, relational, equality, bitwise, reduction, shift, concatenation
and replication opeartors.
(a) Arithmetic Operators :-
(i) Binary Operator:
 Binary operators are multiply (*), divide (/), add (+), subtract
(-), power (**) and modulus (%). Binary operators take two
operands.
 If any operands value is “x”, then the result of the entire
expression is “x”.
 Modulus operator produce the remainder from the division of
two numbers.

Digital Design with Verilog EEC346 141

 (ii) Unary Operators:

The operators + and – can also work as unary operators. They are
used to specify the positive or negative sign of the operand.
+A, - B
(b) Logical Operators:-
Logical operators are logical-and (&&), logical-or(ll), logical-not
(!). Logical and & logical or are binary operators and logical not is
unary operator.
 Logical operators always evaluate to a 1-bit value: 0(false),
1(true), x(ambiguous).
 If an operand is not equal to zero, it is equivalent to logical
1(true condition) & if an operand is equal to zero, it is equivalent to
logical 0(false condition).
 If an operand bit is “x” or “z”, it is equivalent to x & it is treated
as false condition.
Digital Design with Verilog EEC346 142
 (c) Relational Operator :-
Relational operators are greater – than (>), less – than (<), greater-
than-or-equal (>=) & less-than-or-equal (<=).
 If relational operators are used in an expression, the expression
return a logical value of 1, if the expression is true and 0 if the
expression is false.
 If there are x or z bits in the operands, the expression takes a
value of x.

Digital Design with Verilog EEC346 143

 (d) Equality operators :-
Equality operators are logical equality (= =), logical inequality
(! =), case equality (= = =) & case inequality (! = =).
 When used in an expression, equality operators return
logical value 1 if true, 0 if false.
 These operators compare the two operands bit by bit, with zero
filling if the operands are of unequal length.
Expression Description Possible
logical value
a==b a equal to b, result unknown if x or z in a or b 0,1,x
a!=b a not equal to b, result unknown if x or z in a or b 0,1,x

a===b a equal to b, including match in x and z 0,1

a!==b a not equal to b, including match in x and z 0,1

Digital Design with Verilog EEC346 144

 (e) Bitwise Operators :-
The bitwise operators are negation (~), and (&), or (l), xor (^) and
xnor (~^, ^~).
 Bitwise operators perform a bit by bit operation on two
operands.
 They take each bit in one operand and perform the
operation with the corresponding bit in the other operand.
 If one operand is shorter than the other operand, it will be bit
extended with zeros to match the length of longer operand.
 A “z” is treated as an “x” in bitwise operation.

Digital Design with Verilog EEC346 145

Contd …………

Digital Design with Verilog EEC346 146

 (f) Reduction Operators :-
Reduction operators are and (&), or (l), nor (~l), xor (^) and xnor
(~^, ^~).
 Reduction operators take only one operand. Reduction operator
perform a bitwise operation on a single vector operand and yield a
1 – bit result.
 The reduction operator work bit by bit from right to left.

Example:
X= 4’b 1010
& X= 1 & 0 & 1 & 0 // Ans : 0
^ X = 1 xor 0 xor 1 xor 0 // Ans : 0
~ X= 0101
~ ^ X= 1
Digital Design with Verilog EEC346 147
 (g) Shift Operators :-
Shift operators are right shift (>>), left shift (<<), arithmetic right
shift (>>>) and arithmetic left shift (<<<).
 Regular shift operators shift a vectors operand to the right or
left by a specified number of bits.
 When the bits are shifted, for right & left shift, the vacant
bit positions are filled with zeros.
 When the bits are shifted, for arithmetic shift right and shift
left, the vacant bit positions are filled with “1” if the first bit of
operand is signed number & “0” if the operand is unsigned
number.

Digital Design with Verilog EEC346 148

 Examples
• X= 4’b11001
• Y= X>>1 // 1 1 0 0 1
0 1 1 0 0
Y = X >> 2 // 0 0 1 1 0

Y = X << 1 // 11001 = 10010

Y = X << 2 // 00100

Digital Design with Verilog EEC346 149

 Examples
• X= 4’b11001
• Y= X>>>1 // 1 1 0 0 1
1 1 1 0 0
Y = X >>>2 // 1 1 1 1 0

Y = X <<< 1 // 11001 = 10011

Y = X <<< 2 // 00111

Digital Design with Verilog EEC346 150

(h) Concatenation Operators :-
The concatenation operator {,} provides a mechanism to append
multiple operands. The operands must be sized.
Examples:
A= 1’b1; B= 2’b 00; C= 2’b10; D= 3’b110
Y = { B, C} // 4’b 00 10 // 4’b0010
B C
Y = {A, B, C, D} // 8’b 1 00 10 110 // 8’b 10010110
Y= {A, B, C, D, 3’b001} // 11’b 10010110 001 // 10010110001
Y = { A, B[0], c[1]} // 3’b 1 0 1

Digital Design with Verilog EEC346 151

(i) Replication Operators :-
• Repetitive concatenation of the same number can
be expressed by using a replication constant. The
replication constant specifies how many times to
replicate the number inside the brackets.
• Examples:
• A= 1’b1; B= 2’b 00; C= 2’b10; D= 3’b110
• Y= {4 {A}} // 4’ b 1111
• Y={ 4 {A}, 2 {B}} // 8’b 1111 0000

Digital Design with Verilog EEC346 152

 Verilog Testbench
• A Verilog testbench is a simulation environment used to verify
the functionality and correctness of a digital design described
in the Verilog.
• Example 1:
 Verilog modeling of Half adder:

Digital Design with Verilog EEC346 153

 Testbench for Half Adder

Digital Design with Verilog EEC346 154

• Example 2:
 Full Adder test bench

Digital Design with Verilog EEC346 155

 Switch level modeling
Basic Transistor Switches :-
 Consider an NMOS transistor of depletion & enhancement
type: it has following modes of operations,
(i) When gate voltage (Vg) < source voltage (Vs), the transistor
is OFF & offers very high impedance across the source and
drain.
(ii) When gate voltage (Vg) ≈ source voltage (Vs), the transistor
is active & offers a resistance between the source and drain.
(iii) When gate voltage (Vg) > source voltage (Vs), the transistor
is ON & offers very low impedance (0 Ω) across the source
and drain.

Digital Design with Verilog EEC346 156

 Contd ………….
 Consider an PMOS transistor of depletion & enhancement
type: it has following modes of operations,
(i) When gate voltage (Vg) ≈ source voltage (Vs), the transistor
is OFF & offers very high impedance across the source and
drain.
(ii) When gate voltage (Vg) is slightly greater than source
voltage (Vs), the transistor is moderately ON, representing a
resistive mode of operation.
(iii) When gate voltage (Vg) >> source voltage (Vs), the
transistor is ON & offers a very low resistance (0 Ω) between
source and drain.

Digital Design with Verilog EEC346 157

 Basic Switch Primitives :-
 Consider an NMOS as switch, it is declared as,
nmos (out, in, control);
(i) When the control input is 1 (high) state,
the switch is ON. It connects the input lead to
the output side & offers zero impedance
(output is same as input).
(ii) When the control input is 0 (low) state, the switch is OFF &
the output is in z – state.
(iii) When the control input is x or z state, the output may take
corresponding input values.

Digital Design with Verilog EEC346 158

 Contd ……….
0 1 X controlZ
0 Z 0 L L
Input 1 Z 1 H H
X Z X X X
Z Z Z Z Z

Consider an PMOS as switch, it is declared as,

pmos (out, in, control);
(i) When the control input is 0 (low) state,
the switch is ON. It connects the input lead to
the output side & offers zero impedance
(output is same as input).
(ii) When the control input is 1 (high) state, the switch is OFF & the output is
in z – state.
(iii) When the control input is x or z state, the output may take corresponding
input values. Digital Design with Verilog EEC346 159
Contd …………

0 1 X Z
control
0 0Jsdhfdjoikgrk
Z L L
1 1 Z H H
X X Z X X
Z Z Z Z Z

Digital Design with Verilog EEC346 160

 Resistive Switches :-
 nmos & pmos represent switches of low impedance in ON
state. rnmos & rpmos represent the resistive counterparts & it is in
the form;
rnmos (output1, input1, control1);
rpmos (output2, input2, control2);
 In rnmos, if control1 input is 1 (high) state, the switch is ON &
define a resistance. It connects input1 to output1 through a
resistance.
If control1 input is 0 (low) state, the switch is OFF &
leaves output1 is floating.
If control1 input is x or z state, the output may takes
corresponding input1 values.

Digital Design with Verilog EEC346 161

 Contd …………
 In rpmos, if control1 input is 0 (low) state, the switch is ON &
define a resistance. It connects input1 to output1 through a
resistance.
If control1 input is 1 (high) state, the switch is OFF &
leaves output1 is floating.
If control1 input is x or z state, the output may takes
corresponding input1 values.

Digital Design with Verilog EEC346 162

 Pullup & Pulldown :-

 A MOS transistor functions as a resistive element when in the

active state. Pullup & pulldown represent such resistive elements.
Pullup (x); // net x is pulled up to the supply1 through a resistance.
Pulldown (y); // net y is pulled down to the supply0 through a
resistance.
 Pullup & pulldown primitives are used to connect in Vcc and
Ground.
 Pullup & pulldown are pull1 & pull0 respectively.
Pullup (strong1) (x); // a resistive pullup net x to supply1.
Pulldown (strong0) (y); // a resistive pulldown net y to supply0.

Digital Design with Verilog EEC346 163

 Contd ………….
supply (strong1)

Ground (strong0)
 Pulldown network consists of nmos because it pass strong0 (i.e.
it is OFF when gate is 0).
 Pullup network consists of pmos because it pass strong1 (i.e. it
is OFF when gate is 1)

Digital Design with Verilog EEC346 164

 CMOS Inverter :-
NMOS PMOS
Vg = 0 OFF ON
Vg = 1 ON OFF

When gate input is low (0 v), transistor Qn is

OFF & Qp is ON. So, supply1 is connected to
The output. Hence the output is high (1).
 When gate input is high (1 v), transistor Qn is ON & Qp is OFF.
So, supply0 is connected to the output. Hence the output is low (0).

In CMOS, AND functions are connected in series.

OR functions are connected in parallel.

Digital Design with Verilog EEC346 165

 Contd ………………..
 CMOS 2 input NAND gate
 CMOS 2 input NOR gate
 CMOS 3 input NAND gate
 CMOS Half adder design
 CMOS Full adder design
 CMOS Half subtractor design
 CMOS Full subtractor design

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 CMOS switch
 A CMOS switch is formed by connecting a PMOS and an
NMOS switch in parallel, the input leads are connected together in
one side and output leads are connected together in other side.
 NMOS transistor is ON when gate is 1 and PMOS transistor is
ON when gate is 0.
 When n_ctr is 1 & p_ctr is 0, the switch conducts and n_ctr is 0
& p_ctr is 1, the switch is high impedance value.

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 Finite State Machines using Verilog always
statements
• State Machine: A state machine is often used
to control a digital system that carries out a
step-by-step procedure or algorithm.
• State diagrams or state graphs with circles
representing states and arcs representing
transitions have traditionally been used to
specify the operation of the controller state
machine.

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• State Machine Charts: SM charts resemble
software flow charts.
• An SM chart differs from an ordinary flow
chart in that certain specific rules must be
followed in constructing the SM chart. When
these rules are followed, the SM chart is
equivalent to a state graph, and it leads
directly to a hardware realization.

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