8086 PIN DIAGRAM
40 PIN
16 – BIT CPU
3 CLOCK RATES(5,8,10MHz)
•AD 15- AD0
•These are the time multiplexed memory I/O
address and data lines
•Address remains on the lines during T1 state,
while data is available on the data bus during
T2,T3, Tw and T4
•Here T1, T2,T3, Tw and T4 are clock states of a
machine cycle
•Tw is a wait state
•These lines are active high and float to a tristate
during interrupt acknowledge and local bus hold
acknowledge cycles.
•A19/S6,A18/S5,A17/S4,A16/S3
•These are the time multiplexed address and
status lines
•During T1, these are the most significant
address lines for memory operations
• The status of the interrupt enable flag bit
(displayed on S5) is updated at the
beginning of each clock cycle
• The S4 and S3 together indicate which
segment register is presently being used
for memory accesses
• These lines float to tri-state off (tristated)
during the local bus hold acknowledge
• The status line S6 is always low (logical)
• The address bits are separated from the
status bits using latches controlled by the
ALE signal
S4 S3 Indications
0 0 Alternate
Data
0 1 stack
1 0 Code or none
1 1 Data
BHE bar /S7-Bus
High Enable
/Status BHE A0 INDIC
The bus high BAR ATIO
enables signal is N
used to indicate the 0 0 Whole
transfer of data
word
over the higher
order (D15-D8) 0 1 Odd
data bus is as addre
shown in table ss
It goes low for the
1 0 Even
data transfers over
D15-D8 and is used addre
to derive chip ss
selects of odd 1 1 none
address mem bank
BHE bar is low during T1 for read, write,
interrupt acknowledgement when ever byte
is transferred on the higher byte of data bus
Status information is available during
T2,T3,T4
S7 is not currently used
Vcc: +5 volt power supply for internal
circuit
GND: ground for internal circuit
CLK: Clock input: the clock input is
provided basic timing for processor
operation and bus control activity.
Asymmetrical square wave with 33% duty cycle
Frequency : 5MHz-10MHZ
RESET:
This input causes processor to terminate the
current activity and starts execution from
FFFF0 H
The signal is active high and must be active for
atleast 4 clock cycles
It restarts execution when RESET returns low
RESET is also internally synchronized
NMI:
This is an edge triggered input which causes
Type 2 interrupt
This NMI input is not maskable internally by
software
This input is internally synchronized
A transition from low to high initiates the
interrupt respond at the end of current
instruction
TEST bar:
This input is examined by a WAIT instruction
If TEST bar input goes low , execution will continue
If TEST bar input goes high , processor remains in
idle state
This input is synchronized internally during each
clock cycle on the leading edge of clock
RD bar: READ:
Read signal , when low indicates the peripheral that
the processor is performing a memory/ I/O
operation
RD bar is active low and shows the state for
T2,T3,Tw of any read cycle
This signal remains tristate during hold
acknowledge
INTR: interrupt request:
This is a level triggered input
If any of interrupt request is pending then
processor enters interrupt acknowledge cycle
This can be internally masked by resetting the
IF flag
This signal is active high and internally
synchronized
READY:
8284A(clock generator) to provide ready input
to 8086
This signal is active high
This is the acknowledgement from slower
device that have completed data trasfer
