A8455 - FPGA Design

Dr Babu Illuri Vardhaman College of

Engineering
 UNIT-I- Introduction to PLDs and FPGAs

 Introduction
 Simple PLDs, CPLDs, FPGAs
 Organization of FPGAs
 FPGA Programming Technologies
 Programmable Logic Block Architectures Programmable
Interconnects,
 Programmable I/O blocks in FPGAs

Dr Babu Illuri Vardhaman College of

Engineering
Lecture-One Introduction

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Engineering
FPGA Based System
Design

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Engineering
Reference

• Wayne Wolf, ‘FPGA-Based System Design’

Pearson Education, 2004

Dr Babu Illuri Vardhaman College of

Engineering
 Why VLSI?
 Integration improves the design:

higher speed;

lower power;

physically smaller.
 Integration reduces manufacturing cost (almost) - no
manual assembly.

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Integrated Circuits

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Engineering
 Full Custom ICs
 Can achieve very high transistor density (transistors per
square micron)
 design time can be very long (multiple months).
 Involves the creation of a completely new chip, which
consists of masks (for the photolithographic manufacturing
process)
 Benefits - Excellent performance, small size, low power

Dr Babu Illuri Vardhaman College of

Engineering
 Standard Cell

 Designer uses a library of standard cells

 an automatic place and route tool does the layout

 Transistor density and performance degradation depends

on type of design being done.

 Design time can be much faster than full custom because

layout is automatically generated.

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Engineering
Gate Array
 Designer uses a library of standard cells.

 The design is mapped onto an array of transistors which is

already created on a wafer

 wafers with transistor arrays can be created ahead of time

 A routing tool creates the masks for the routing layers and
"customizes" the pre-created gate array for the user's design

 Transistor density can be almost as good as standard cell.

 Design time advantages are the same as for standard cell.

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Engineering
Semi-custom ICs
 Flexible as portion of the IC is customized by the user
 Suitable for specific applications
 Gate array + standard cell
 Paves way for application specific ICs (ASIC)

Dr Babu Illuri Vardhaman College of

Engineering
 Role of FPGA
 Microprocessors used in variety of environments

Rely on software to implement functions

Generally slower and more power-hungry than custom
chips
 When FPGAs?

Design economics

Shortest time to market

Lowest NRE cost

Highest unit cost

Make quick grab for market share

Same FPGA reused in several designs

Dr Babu Illuri Vardhaman College of

Engineering
Programmable logic devices
 Programmable Logic Device (PLD):

An integrated circuit chip that can be configured by
end user to implement different digital hardware

Also known as “Field Programmable Logic Device
(FPLD) “

Dr Babu Illuri Vardhaman College of

Engineering
 PLD
 PLD as a Black Box

Logic gates
Inputs and Outputs
(logic variables) programmable (logic
switche
functions)
s

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Engineering
 Programmable Logic Array (PLA)
x1 x2 xn


Use to implement
circuits in SOP form
Input
buffers
and

The connections in the AND inverters
plane are programmable
x1 x1 xn xn

P1

The connections in the OR
plane are programmable AND plane OR plane
Pk

DrKrishna
N Babu Illuri
Engineering
Vardhaman
Prakash, Amrita School ofCollege of
Engineering
f1 fm
 Gate Level Version of PLA
x1 x2
x3
Programmab
le
connections
f1 = OR
P1 plane
x1x2+x1x3'+x1'x2'x3

f2 =
P2
x1x2+x1'x2'x3+x1x3

P3

P4

AND
plane
Dr Babu Illuri Vardhaman College of
Engineering f1 f2
 Customary Schematic of a PLA
x1 x2
x3

OR
f1 = plane
x1x2+x1x3'+x1'x2'x3 P1

f2 =
P2
x1x2+x1'x2'x3+x1x3

P
x marks the connections left in AND
place after programming plane
Dr Babu Illuri Vardhaman College of
Engineering f1 f2
 Limitations of PLAs
 Typical size is 16 inputs, 32 product terms, 8 outputs

Each AND gate has large fan-in - this limits the number of
inputs that can be provided in a PLA

16 inputs 216 = possible input combinations; only 32
permitted (since 32 AND gates) in a typical PLA

32 AND terms permitted  large fan-in for OR gates as well

 This makes PLAs slower and slightly more expensive than

some alternatives to be discussed shortly

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Engineering
Programmable ROM (PROM)

N 2Nx M
input M output
ROM

Address: N bits; Output word: M bits

ROM contains 2 N words of M bits each

The input bits decide the particular word that becomes available
on output lines

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Engineering
Logic Diagram of 8x3 PROM

Sum of minterms
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Combinational Circuit Implementation using
PROM

I0 I1 I2 F0 F1
F2
0 0 0 1 0 0
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 0 1 0
1 0 1 0 0 1
1 1 0 1 0 0
1 1 1 0 1 0 F0 F1
F2
Dr Babu Illuri Vardhaman College of
Engineering
PROM Types
 Programmable PROM

Break links through current pulses

Write once, Read multiple times
 Erasable PROM (EPROM)

Program with ultraviolet light

Write multiple times, Read multiple times
 Electrically Erasable PROM (EEPROM)/ Flash
Memory

Program with electrical signal

Write multiple times, Read multiple times

Dr Babu Illuri Vardhaman College of

Engineering
PROM: Advantages and Disadvantages
 Widely used to implement functions with large number
of inputs and outputs

 For combinational circuits with lots of don’t care terms,

PROM is a wastage of logic resources

Dr Babu Illuri Vardhaman College of

Engineering
 Programmable Array Logic (PAL)
x1 x2 xn


Also used to implement
circuits in SOP form
Input
buffers
and

The connections in inverters
fixed
connections
the AND plane are x1 x1 xn xn
programmable
P1
 The connections in
the OR plane are AND plane OR plane
Pk
NOT programmable

f1 fm
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Engineering
 Example Schematic of a PAL
x1 x2
x3

f1 =
x1x2x3'+x1'x2x3 P1

f2 = f1
x1'x2'+x1x2x3 P2

P3

f2
P4

AND
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Engineeringplane
 Comparing PALs and PLAs

 PALs have the same limitations as PLAs (small number of

allowed AND terms) plus they have a fixed OR plane  less
flexibility than PLAs

 PALs are simpler to manufacture, cheaper, and faster (better

performance)

 PALs also often have extra circuitry connected to the output of

each OR gate

The OR gate plus this circuitry is called a macrocell

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Engineering
 Macrocell
Selec
t Enabl
OR gate from 0
e
PAL f1
1

D Q
Flip-flop
Cloc
k

back to AND
plane

Dr Babu Illuri Vardhaman College of

Engineering
 Macrocell Functions

 Enable = 0 can be used to allow the output pin for f1 to be

used as an additional input pin to the PAL
Select
Enable
 Enable = 1, Select = 0 is normal 0
for typical PAL operation 1 f1

D
Q
 Enable = Select = 1 allows Clock
the PAL to synchronize the
output changes with a clock
back to AND plane
pulse

 The feedback to the AND plane provides for multi-level design

Dr Babu Illuri Vardhaman College of Engineering
 Multi-Level Design with PALs
 f = A'BC + A'B'C' + ABC' + AB'C = A'g
+ Ag'
A

B where g = BC + B'C' and C = h below
Sel =
En =
0
0 0
1
h

D
Q Sel =
Cloc En =
0
k 0 1
g
1

D
Q Selec
Cloc t
k 0
f
1

Q
Dr Babu Illuri Vardhaman College of
Engineering Clock
 Complex Programmable Logic Devices (CPLDs):

A CPLD contains a bunch of PLD

blocks whose inputs and outputs are
connected by a global interconnection
matrix.

Thus a CPLD has two levels of

programmability: each PLD block can
be programmed, and then the
interconnections between the PLDs
can be programmed.

Dr Babu Illuri Vardhaman College of Engineering

 Field Programmable Gate Arrays (FPGAs):

The FPGA consists of 3 main structures:

​
1. Programmable logic structure,
2. Programmable routing structure, and
3. Programmable Input/Output (I/O).

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Engineering
 Programmable logic structure
The programmable logic structure FPGA consists of a 2-dimensional array
of configurable logic blocks (CLBs).

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 2. Programmable routing structure
To allow for flexible interconnection of CLBs, FPGAs
have 3 programmable routing resources:

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Engineering
 FPGA Programming
 FPGAs implement multi-level logic
 Need both programmable logic blocks
and programmable interconnect
 Combination of logic and interconnect
is fabric

 Microprocessor is a stored-program
computer

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Engineering
Moore’s Law
 Gordon Moore: co-founder of Intel.
 Predicted that number of transistors per chip would
grow exponentially (double every 18 months).

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Engineering
Mask cost Vs technology line width

1,000,000
900,000
800,000
700,000
600,000
500,000
mask cost ($)
400,000
300,000
200,000
100,000
0
.25 micron .18 micron .13 micron .09 micron

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Engineering
Goals and Techniques
 Performance

Logic rate
 Power/
energy
 Design time
 Design cost

FPGA
tools less
expensive
than
custom
VLSI tools
 Manufacturi Dr Babu Illuri
Engineering
Vardhaman College of
Design Challenges
 Multiple levels of abstraction

 Power consumption

 Short design time

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Engineering
FPGA Abstractions

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Engineering
 Top-down design adds functional detail.

Create lower levels of abstraction from upper
levels.
 Bottom-up design creates abstractions from low-level
behavior.
 Good design needs both top-down and bottom-up
efforts.

Dr Babu Illuri Vardhaman College of

Engineering
Methodology
 Hardware Description logic (HDL)

VHDL

VerilogHDL

Dr Babu Illuri Vardhaman College of

Engineering
Major FPGA Vendors
 SRAM-based FPGAs

Xilinx, Inc
Share 80% of the market

Altera Corp.

Atmel

Lattice Semiconductor

 Flash & Antifuse FPGAs


Actel Corp.

Quick logic Corp.

Dr Babu Illuri Vardhaman College of

Engineering
FPGA Vendors and Device families
 Xilinx

Spartan

Virtex

Kintex

Artix
 Altera

Stratix

Cyclone

MAX 3000/7000 CPLD

MAX-II

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Xilinx Families

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Altera Families

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Switch Matrix

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Engineering
 Routing Resources in FPGA’s
PSM(Programmable Switch Matrix)

1. Local Routing – Connects adjacent logic blocks.

2. Global Routing – Connects logic blocks across FPGA regions.

3. Long-Line Routing – Spans large distances with minimal delay.
4. Direct Interconnects – Dedicated fast connections between
nearby blocks.
5. Programmable Interconnects (Switch Matrix) – Configurable
routing using switches.
6. Segment-Based Routing – Uses short, medium, and long wire
segments.
7. lock Routing – Distributes clock signals with minimal skew.

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FPGA Technologies

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Engineering
Difference Between CPLD and FPGA

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 Example Problem:

Design a combinational circuit to implement the following Boolean function

using a PAL:
F(A,B,C)=Σm(1,3,4,6)
Solution:
1. Simplify the Boolean Function using K-map:

2. PAL Implementation:
1. Write the simplified logic equation in terms of AND-OR gates.
2. Configure the PAL to implement this logic.
Diagram: Use a PAL with 3 inputs, a programmable AND array, and a fixed OR array.

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Engineering