CSIE30300 Computer Architecture

Unit 10: Improving Cache Performance

Hsin-Chou Chi

[Adapted from material by Patterson@UCB and Irwin@PSU]

Review: The Memory Hierarchy
 Take advantage of the principle of locality to present the
user with as much memory as is available in the cheapest
technology at the speed offered by the fastest technology
Processor
4-8 bytes (word)
Inclusive– what
is in L1$ is a
Increasing L1$
subset of what
distance 8-32 bytes (block) is in L2$ is a
from the
L2$ subset of what
processor in
is in MM that is
access time 1 to 4 blocks
a subset of is
Main Memory in SM
1,024+ bytes (disk sector = page)

Secondary Memory

(Relative) size of the memory at each level

 Review: Principle of Locality
 Temporal Locality
 Keep most recently accessed data items closer to the processor
 Spatial Locality Lower Level
To Processor Upper Level Memory
 Move blocks consisting Memory
of contiguous words From Processor
Blk X
to the upper levels Blk Y

 Hit Time << Miss Penalty

 Hit: data appears in some block in the upper level (Blk X)
- Hit Rate: the fraction of accesses found in the upper level
- Hit Time: RAM access time + Time to determine hit/miss
 Miss: data needs to be retrieve from a lower level block (Blk Y)
- Miss Rate = 1 - (Hit Rate)
- Miss Penalty: Time to replace a block in the upper level with a block
from the lower level + Time to deliver this block’s word to the processor
- Miss Types: Compulsory, Conflict, Capacity
Measuring Cache Performance
 Assuming cache hit costs are included as part of the
normal CPU execution cycle, then
CPU time = IC × CPI × CC
= IC × (CPIideal + Memory-stall cycles) × CC
CPIstall
 Memory-stall cycles come from cache misses (a sum of
read-stalls and write-stalls)
Read-stall cycles = reads/program × read miss rate
× read miss penalty
Write-stall cycles = (writes/program × write miss rate
× write miss penalty)
+ write buffer stalls
 For write-through caches, we can simplify this to
Memory-stall cycles = miss rate × miss penalty
Review: The “Memory Wall”
 Logic vs DRAM speed gap continues to grow

1000

Clocks per DRAM access

Clocks per instruction

100

10 Core
Memory
1

0.1

0.01
VAX/1980 PPro/1996 2010+
Impacts of Cache Performance
 Relative cache penalty increases as processor
performance improves (faster clock rate and/or lower CPI)
 The memory speed is unlikely to improve as fast as processor
cycle time. When calculating CPIstall, the cache miss penalty is
measured in processor clock cycles needed to handle a miss
 The lower the CPIideal, the more pronounced the impact of stalls
 A processor with a CPIideal of 2, a 100 cycle miss penalty,
36% load/store instr’s, and 2% I$ and 4% D$ miss rates
Memory-stall cycles = 2% × 100 + 36% × 4% × 100 = 3.44
So CPIstalls = 2 + 3.44 = 5.44

 What if the CPIideal is reduced to 1? 0.5? 0.25?

 What if the processor clock rate is doubled (doubling the
miss penalty)?
Reducing Cache Miss Rates #1
1. Allow more flexible block placement

 In a direct mapped cache a memory block maps to

exactly one cache block
 At the other extreme, could allow a memory block to be
mapped to any cache block – fully associative cache

 A compromise is to divide the cache into sets each of

which consists of n “ways” (n-way set associative). A
memory block maps to a unique set (specified by the
index field) and can be placed in any way of that set (so
there are n choices)
(block address) modulo (# sets in the cache)
 Set Associative Cache Example
Main Memory
0000xx
Cache 0001xx Two low order bits
define the byte in the
0010xx
Way Set V Tag Data word (32-b words)
0011xx
One word blocks
0 0100xx
0
1 0101xx
0 0110xx
1
1 0111xx
Q2: How do we find it?
1000xx
1001xx
1010xx
Use next 1 low order
Q1: Is it there?
1011xx
memory address bit to
1100xx
determine which
Compare all the cache
tags in the set to the 1101xx cache set (i.e., modulo
high order 3 memory 1110xx the number of sets in
address bits to tell if 1111xx the cache)
the memory block is in
the cache
Another Reference String Mapping
 Consider the main memory word reference string
Start with an empty cache - all
0 4 0 4 0 4 0 4
blocks initially marked as not valid

0 miss 4 miss 0 hit 4 hit

000 Mem(0) 000 Mem(0) 000 Mem(0) 000 Mem(0)

010 Mem(4) 010 Mem(4) 010 Mem(4)

 8 requests, 2 misses

 Solves the ping pong effect in a direct mapped cache

due to conflict misses since now two memory locations
that map into the same cache set can co-exist!
 Four-Way Set Associative Cache
 28 = 256 sets each with four ways (each with one block)
31 30 ... 13 12 11 ... 2 1 0 Byte offset

Tag 22 8
Index
Index V Tag Data V Tag Data V Tag Data V Tag Data
0 0 0 0
1 1 1 1
2 2 2 2
. . . .
. . . .
. . . .
253 253 253 253
254 254 254 254
255 255 255 255

32

4x1 select

Hit Data
Range of Set Associative Caches
 For a fixed size cache, each increase by a factor of two
in associativity doubles the number of blocks per set (i.e.,
the number or ways) and halves the number of sets –
decreases the size of the index by 1 bit and increases
the size of the tag by 1 bit

Used for tag compare Selects the set Selects the word in the block

Tag Index Block offset Byte offset

Increasing associativity
Decreasing associativity
Fully associative
Direct mapped (only one set)
(only one way) Tag is all the bits except
Smaller tags block and byte offset
Costs of Set Associative Caches
 When a miss occurs, which way’s block do we pick for
replacement?
 Least Recently Used (LRU): the block replaced is the one that
has been unused for the longest time
- Must have hardware to keep track of when each way’s block was
used relative to the other blocks in the set
- For 2-way set associative, takes one bit per set → set the bit when a
block is referenced (and reset the other way’s bit)
 N-way set associative cache costs
 N comparators (delay and area)
 MUX delay (set selection) before data is available
 Data available after set selection (and Hit/Miss decision). In a
direct mapped cache, the cache block is available before the
Hit/Miss decision
- So its not possible to just assume a hit and continue and recover later
if it was a miss
Benefits of Set Associative Caches
 The choice of direct mapped or set associative depends
on the cost of a miss versus the cost of implementation
12
4KB
10 8KB
16KB
8
Miss Rate

32KB
6 64KB
128KB
4 256KB
512KB
2
Data from Hennessy &
0 Patterson, Computer
1-way 2-way 4-way 8-way Architecture, 2003
Associativity
 Largest gains are in going from direct mapped to 2-way
(20%+ reduction in miss rate)
Reducing Cache Miss Rates #2
2. Use multiple levels of caches

 With advancing technology have more than enough

room on the die for bigger L1 caches or for a second
level of caches – normally a unified L2 cache (i.e., it
holds both instructions and data) and in some cases
even a unified L3 cache
 For our example, CPIideal of 2, 100 cycle miss penalty (to
main memory), 36% load/stores, a 2% (4%) L1I$ (D$)
miss rate, add a UL2$ that has a 25 cycle miss penalty
and a 0.5% miss rate

CPIstalls = 2 + .02×25 + .36×.04×25 + .005×100 +

.36×.005×100 = 3.54
(as compared to 5.44
with no L2$)
Multilevel Cache Design Considerations
 Design considerations for L1 and L2 caches are very
different
 Primary cache should focus on minimizing hit time in support of
a shorter clock cycle
- Smaller with smaller block sizes
 Secondary cache(s) should focus on reducing miss rate to
reduce the penalty of long main memory access times
- Larger with larger block sizes

 The miss penalty of the L1 cache is significantly reduced

by the presence of an L2 cache – so it can be smaller
(i.e., faster) but have a higher miss rate
 For the L2 cache, hit time is less important than miss rate
 The L2$ hit time determines L1$’s miss penalty
 L2$ local miss rate >> the global miss rate
Key Cache Design Parameters

L1 typical L2 typical
Total size (blocks) 250 to 2000 4000 to
250,000
Total size (KB) 16 to 64 500 to 8000
Block size (B) 32 to 64 32 to 128
Miss penalty (clocks) 10 to 25 100 to 1000
Miss rates 2% to 5% 0.1% to 2%
(global for L2)
Two Machines’ Cache Parameters

Intel P4 AMD Opteron

L1 organization Split I$ and D$ Split I$ and D$
L1 cache size 8KB for D$, 96KB for 64KB for each of I$ and D$
trace cache (~I$)
L1 block size 64 bytes 64 bytes
L1 associativity 4-way set assoc. 2-way set assoc.
L1 replacement ~ LRU LRU
L1 write policy write-through write-back
L2 organization Unified Unified
L2 cache size 512KB 1024KB (1MB)
L2 block size 128 bytes 64 bytes
L2 associativity 8-way set assoc. 16-way set assoc.
L2 replacement ~LRU ~LRU
L2 write policy write-back write-back
4 Questions for the Memory Hierarchy

 Q1: Where can a block be placed in the upper level?

(Block placement)

 Q2: How is a block found if it is in the upper level?

(Block identification)

 Q3: Which block should be replaced on a miss?

(Block replacement)

 Q4: What happens on a write?

(Write strategy)
Q1&Q2: Where can a block be placed/found?

# of sets Blocks per set

Direct mapped # of blocks in cache 1
Set associative (# of blocks in cache)/ Associativity (typically
associativity 2 to 16)
Fully associative 1 # of blocks in cache

Location method # of comparisons

Direct mapped Index 1
Set associative Index the set; compare Degree of
set’s tags associativity
Fully associative Compare all blocks tags # of blocks
Q3: Which block should be replaced on a miss?
 Easy for direct mapped – only one choice
 Set associative or fully associative
 Random
 LRU (Least Recently Used)

 For a 2-way set associative cache, random

replacement has a miss rate about 1.1 times higher
than LRU.
 LRU is too costly to implement for high levels of
associativity (> 4-way) since tracking the usage
information is costly
Q4: What happens on a write?
 Write-through – The information is written to both the
block in the cache and to the block in the next lower level
of the memory hierarchy
 Write-through is always combined with a write buffer so write
waits to lower level memory can be eliminated (as long as the
write buffer doesn’t fill)
 Write-back – The information is written only to the block in
the cache. The modified cache block is written to main
memory only when it is replaced.
 Need a dirty bit to keep track of whether the block is clean or dirty
 Pros and cons of each?
 Write-through: read misses don’t result in writes (so are simpler
and cheaper)
 Write-back: repeated writes require only one write to lower level
 Improving Cache Performance
0. Reduce the time to hit in the cache
 smaller cache
 direct mapped cache
 smaller blocks
 for writes
- no write allocate – no “hit” on cache, just write to write buffer
- write allocate – first check for hit, then write

1. Reduce the miss rate

 bigger cache
 more flexible placement (increase associativity)
 larger blocks (16 to 64 bytes typical)
 Improving Cache Performance
2. Reduce the miss penalty
 smaller blocks
 use a write buffer to hold dirty blocks being replaced so don’t
have to wait for the write to complete before reading
 use multiple cache levels – L2 cache not tied to CPU clock rate
 faster backing store/improved memory bandwidth
- wider buses
- memory interleaving, page mode DRAMs
Summary: The Cache Design Space
 Several interacting dimensions Cache Size
 cache size
 block size Associativity
 associativity
 replacement policy
 write-through vs write-back
 write allocation Block Size

 The optimal choice is a compromise

 depends on access characteristics
Bad
- workload
- use (I-cache, D-cache, TLB)
 depends on technology / cost Good Factor A Factor B

 Less More
Simplicity often wins