Architecture and

Features of
PIC18F52
Microcontroller
 Introduction to PIC18F Series
Agenda Comparison Between PIC16F and PIC18F
Architecture of PIC18FXX2
Memory Organization
Clock and Reset System
Input/Output (I/O) Ports
Timers
Capture/Compare/PWM (CCP) Modules
Analog-to-Digital Converter (ADC)
Interrupt System
Exercises
Conclusion
Overview of PIC18F Series

Voltage and Speed

• Operates at 2.0V - 5.5V
• Speeds up to 40MHz
Development Background
• Upgrade from PIC16F series
• Addresses limitations of PIC16F
Design Purpose
• High-pin-count, high-density applications
• Supports RTOS, TCP/IP, USB, CAN, and ZigBee
Key Instruction Set
• 77 instructions

Features of • Source code compatible with PIC16F

Memory
PIC18F • Program memory addressing up to 2MB
• Data memory up to 4KB
Series Architecture
Hardware Features
Timers
Analog-to-Digital Converter (ADC)
Communication Protocols
Additional Features
Enhanceme Doubled Instruction Set
• Increased efficiency and performance

nts in 16-bit Instruction Word

• Improved processing capability
PIC18F Hardware Multiplier
• Faster arithmetic operations

More Interrupts with Priority Levels

• Better control and management of tasks

Larger Stack and Higher Memory

• Enhanced storage and data handling

Phase-Locked Loop (PLL) Clock Multiplier

Enhanced I/O Port Architecture
Similarities

Similarities between PIC16F and PIC18F

• Same package and pinout
• Similar SFR names and functions
• Similar peripheral devices
Overview of PIC18FXX2
Series
PIC18FXX2 Series Overview
• Includes PIC18F242, PIC18F252, PIC18F442, and PIC18F452
Device Pin Configurations
• 28-pin devices: PIC18F242, PIC18F252
• 40-pin devices: PIC18F442, PIC18F452
Additional Features in 40-pin Versions
• More I/O ports
• More ADC channels
CPU
Components
8-bit ALU and WREG
• 8-bit Arithmetic Logic Unit
• 8-bit Working Register
8×8 Hardware Multiplier
• Efficient multiplication operations
Program Memory
• Flash memory up to 32Kbytes
Data Memory
• RAM up to 1.5KB
EEPROM
• 256 bytes of EEPROM
Program Memory

21-bit Address Bus

• Supports up to 2MB of memory
Actual User Space
• Address range from 00000H to 7FFFH
Reset and Interrupt Vectors
• Reset vector located at 0000H
• Interrupt vectors at 0008H and 0018H
Hardware Stack
• 31-entry hardware stack
Data Memory

Memory Banks
• 16 banks available
• 256 bytes each
• 6 banks used in PIC18F452
General Purpose Registers (GPR)
• Used for temporary storage
Special Function Registers (SFR)
• Used for peripheral control
Bank Switching
• Handled by compiler
Clock and External Clock Sources
• Crystal

Reset • Resonator
• RC oscillator

System PLL (Phase-Locked Loop)

• Multiplies frequency by 4
• Enhances performance

Reset Mechanisms
• Power-on Reset (POR)
• Brown-out Reset (BOR)
• Watchdog Timer (WDT)
I/O Ports Overview

PORTA
• 7-bit
PORTB
• 8-bit
• Interrupt-on-Change
PORTC
• 8-bit
• USART, SPI, I2C
PORTD
• 8-bit
• Parallel Slave Port support
PORTE
Port Latches

Ports in Microcontrollers
• Include latches such as LATA and LATB
• Store the last written values
Timers Timer 0
• 8-bit or 16-bit mode
• External/internal clock
Timer 1
• 16-bit
• Used for real-time clock applications
Timer 2
• 8-bit
• Used for PWM generation
Timer 3
• 16-bit
• Similar to Timer 1
CCP Module Functions

Capture Mode
• Records time of external event
Compare Mode
• Generates output when timer matches a preset value
PWM Mode
• Produces Pulse Width Modulation
• Used for motor control, LED dimming, etc.
Analog-to-Digital
Converter (ADC)
10-bit Resolution
• Provides precise digital representation
8 Input Channels
• Channels labeled AN0 to AN7
Conversion Time
• 34.5 µs maximum
• Maximum sampling rate of approximately 29kHz
Result Storage
• Uses ADRESH/ADRESL registers
• Stores 10-bit conversion results
Interrupt External Interrupts
• INT0

Sources • INT1
• INT2

Timer Interrupts
• TMR0
• TMR1
• TMR2
• TMR3

Serial Communication Interrupts

ADC Conversion Completion
EEPROM Write Completion
Interrupt Primary Interrupt Control Registers
• INTCON

Control • INTCON2
• INTCON3
Registers Interrupt Flags
• PIR1
• PIR2
Interrupt Enables
• PIE1
• PIE2
Interrupt Priorities
• IPR1
Interrupt Priorities and Vectors

Interrupt Priorities Interrupt Vector

Addresses
Two levels: High and Low High Priority: 00008H
Low Priority: 00018H
Conclusion Enhanced Processing Capabilities
• Improved performance for various applications

Extended Memory
• Supports larger and more complex programs

Advanced Peripherals
• Offers a range of built-in functionalities

Flexible Power Management

• Optimizes power consumption for efficiency

Ideal for Various Applications

• Embedded systems, industrial control, and
communication

Strong Foundation for Programming

• Understanding architecture aids in microcontroller
programming and interfacing
Program Memory Program Memory Overview
• Addressable size: Up to 2 MB
Overview (21-bit address bus)
• Actual memory size: 32 KB
(PIC18F452)
Flash Memory
• Stores the user program
permanently
Memory Addressing
• Byte-addressable
• Instructions stored as 16-bit or
32-bit words
• Supports In-Circuit Serial
Programming (ICSP)
Program Memory
Map
Address Space Sections
• 00000H - 7FFFH: User Program Memory (32 KB in
PIC18F452)
• 8000H - 1FFFFFH: Unimplemented Memory (returns
all 0s if accessed)
Key Memory Addresses
• 00000H: Reset Vector (execution starts here after
reset)
• 00008H: High-Priority Interrupt Vector
Memory Capacity
• Program memory addressing up to 2MB
• Data memory up to 4KB
Reset and Interrupt Microcontroller Start or Reset
• Execution begins at address
Vector Addresses 0000H (Reset Vector)
Interrupts Fixed Locations
• 0008H for High-priority
interrupt service routine (ISR)
• 0018H for Low-priority interrupt
service routine (ISR)
Interrupt Handling
• Program jumps to specific
addresses
• Executes corresponding
interrupt service routine
Program Counter (PC) and
Stack
Program Counter (PC)
• Keeps track of the current instruction being executed
• 21 bits wide, addressing up to 2MB of memory
• PIC18F452 uses only 15 bits, addressing up to 32 KB
Hardware Stack
• 31-level stack for subroutines and interrupts
• Stack Pointer (STKPTR) tracks function call levels
Instruction Execution

Instruction Cycle Phases

• Fetch: Instruction is fetched from program memory
• Decode: Instruction is decoded
• Execute: Instruction is executed
• Write-back: Results are stored
Pipelining
• Allows fetching and execution to overlap
• Improves speed
Table Read and Table
Write Operations
Table Read (TBLRD) Operation
• Enables reading data from program memory
• Used for accessing lookup tables like sine wave values, fonts, etc.
Table Write (TBLWT) Operation
• Allows writing or modifying certain areas of program memory
• Useful for updating lookup tables stored in program memory
Code Protection Code Protection Bits
• CP0 - CP3: Protects program
and Security memory from external reads
• WRT0 - WRT3: Protects memory
from being overwritten
Boot Block Protection (CPB)
• Protects the bootloader
Summary of Key Features

Feature Details
Up to 2MB (21-bit addressable), 32KB in
Memory Size
PIC18F452
Memory Type Flash (Reprogrammable)
Instruction Width 16-bit (some 32-bit)
Stack Depth 31 levels
Interrupt Vectors 0008H (High), 0018H (Low)
Execution Speed Pipelined, 4 cycles per instruction
Data
Data Memory Overview
• Organized into a 12-bit addressable space

Memory • Access up to 4 KB of RAM

• Divided into banks for efficient addressing

Overview Components of Data Memory

• General Purpose Registers (GPRs) for temporary storage
• Special Function Registers (SFRs) for controlling system
operations and peripherals
• EEPROM (256 Bytes) for non-volatile data storage
• Access Bank (256 Bytes total) for direct access without
bank switching
Bank Allocation
• First 128 bytes (0x000 - 0x07F) from Bank 0 used as
GPRs
• Second 128 bytes (0x080 - 0x0FF) from Bank 15 used as
SFRs
 Section Size Purpose
General Used for
Purpose RAM 1.5 KB storing

Data Memory Map (GPR)

Special
variables
Controls
Function hardware
Varies
Registers and
(SFR) peripherals

- First 128
Data Memory Organization bytes from
Bank 0 →
• Organized into 16 banks General
Purpose
• Each bank has 256 bytes Registers
(0x000 -
Access Bank
Usage in PIC18F Models (256 Bytes
0x07F) -
Second 128
Total)
• Only a portion of banks used bytes from
Bank 15 →
• Example: PIC18F452 Special
Function
Registers
(0x080 -
0x0FF)

EEPROM
Stores data
(Non-Volatile 256 Bytes
permanently
Memory)
 Banked Memory Addressing
Banked Memory • Used to access more than 256 bytes of RAM

Organization
efficiently
• Each bank consists of 256 bytes
Bank Select Register (BSR)
• Used to select a specific bank
Access Bank
• 256 bytes allowing direct access without
bank switching
• First 128 bytes from Bank 0 (General Purpose
RAM)
• Second 128 bytes from Bank 15 (SFRs)
Example of Banked Memory Addressing
• MOVWF 0x20: Store value in GPR (requires
BSR selection)
• MOVWF 0xF80: Store value in SFR (direct
access)
General Purpose Registers
(GPRs)
Location and Usage
• Located in each bank
• Used for storing variables and program data
• Compiler handles bank switching automatically
Access Bank
• First 128 bytes (0x000 - 0x07F) of the Access Bank are GPRs from Bank
0
Example: Storing and Retrieving a Value in RAM
• MOVLW 0x55: Load WREG with 0x55
• MOVWF 0x20: Store in GPR memory (requires correct BSR)
• MOVF 0x20, W: Retrieve from GPR memory into WREG
Special Function Control Peripheral Operations
• Timers, ADC, USART, and interrupts
Registers (SFRs) Location of SFRs
• Upper half of Bank 15 (0xF80 - 0xFFF)
• Second 128 bytes (0x080 - 0x0FF) of the
REGISTER FUNCTION Access Bank

Accessibility
TMR0, TMR1, TMR2 Timer Registers
• Directly accessible without using the BSR
INTCON Interrupt Control
Important SFRs
PORTA, PORTB, etc. I/O Ports • Example: Setting PORTB as an output
• CLRF TRISB: Set all PORTB pins as output
Configure I/O
TRISA, TRISB, etc. • MOVLW 0xFF
Direction
• MOVWF PORTB: Turn ON all PORTB pins
ADC
ADCON0, ADCON1
Configuration
Access Bank Total Size of Access Bank
• 256 bytes (0x000 - 0x0FF)
Division of Access Bank
• First 128 bytes (0x000 - 0x07F)
• Second 128 bytes (0x080 -
0x0FF)
Contents of Each Section
• First 128 bytes: General
Purpose Registers (Bank 0)
• Second 128 bytes: Special
Function Registers (Bank 15)
Direct Access Capability
• Allows direct access to both
GPRs and SFRs without
switching banks
EEPROM EEPROM Characteristics
• Stores data permanently

(Non- • Retains data even when power is lost

EEPROM Write Sequence

Volatile • Requires specific write sequence for modification
• Controlled using EECON1, EECON2 registers
Memory) Example: Writing to EEPROM
• Enable write: BSF EECON1, WREN
• Load data: MOVLW 0xA5, MOVWF EEDATA
• Set address: MOVLW 0x10, MOVWF EEADR
• Disable interrupts: BCF INTCON, GIE
• Required write sequence: MOVLW 0x55, MOVWF
EECON2; MOVLW 0xAA, MOVWF EECON2
Feature Details
Total RAM Size 1.5 KB (PIC18F452) Stack and Stack
16 banks (256 bytes
Memory Banks
each)
256 bytes total (First
Pointer
128 bytes: GPRs from 31-level hardware stack
Access Bank Bank 0, Second 128
bytes: SFRs from • Used for storing return addresses
Bank 15)
Automatic management
General Purpose
GPRs • Managed during function calls and
Registers (RAM)
interrupts
Controls hardware
SFRs
and peripherals Dedicated memory space
256 Bytes, Non- • Stack does not use RAM
EEPROM
Volatile Storage
Peripheral devices
31 levels, separate
Stack • Similar peripheral devices
from RAM
Conclusion Memory Structure
• Organized into banks
• Includes RAM, SFRs, and
EEPROM
Access Bank
• 256 bytes for simplified access
• Direct access to GPRs and SFRs
Bank Switching
• Efficient memory management
• Access beyond the 256-byte
range