Digital Fundamental

Prof K.K. Arora

SVIT, Vasad
Sequential Circuits
 Sequential Circuits

Input
s Combination
al Logic

Nex
Storag Stat
e e t
Element Stat
s
★ Combinational Ckt : outputs at any instant ofetime
entirely dependent on the input present at that time.
★ Sequential Ckt : combinational ckt + memory elements
● Memory elements are devices capable of storing binary
information.
● The binary information stored at any given time defines state of the
sequential ckt.
● Output = external input + present state of the memory elements
Sequential Circuits Vs Combinational Circuits
 Types of Sequential Circuits

★ Depends on the times at which:

● storage elements observe their inputs, and
● storage elements change their state
★ Synchronous
● Behavior defined from knowledge of its signals at discrete
instances of time
● Storage elements observe inputs and can change state only
in relation to a timing signal (clock pulses from a clock)
★ Asynchronous
● Behavior defined from knowledge of inputs an any instant of time
and the order in continuous time in which inputs change
● If clock just regarded as another input, all circuits are
asynchronous!
 Sequential Circuits

★ Asynchronous
Input Output
s Combinational s
Circuit
Memory
Elements

★ Synchronous

Input Output
s Combinational s
Circuit
Flip-flops
Clock

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 Flip Flop/Latch

★ Memory elements used in sequential ckt

★ Binary cells capable of storing one bit of
information.
★ Has two output - one for normal value
★ - one for complement
value
★ A flip flop can maintain a binary state indefinitely
until directed by a input signal to switch state.
 SR Latch/FF

★ Can be constructed from 2 NOR/NAND gates

★ Cross-coupled connection forms a feedback path
★ Asynchronous sequential ckt
★ Has 2 input set(S) and reset( R)
★ Also called direct-coupled RS flip-flop or SR latch

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 Latches

★ SR Latch S R Q0 Q Q’
0 0 0 0 1 Q = Q0

0 0

0 1

Initial Value

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1 Q = Q0
0 0 1 1 0 Q=
0 1 Q0

0 0

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 0

0 1

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1 Q=0
1 1 0 1 1 0 1 Q=0

0 0

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 0 0 1 1 0 1
Q=0

1 0 0 1 0 Q=1

1 1

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1 0 1
Q=0

1 0 0 1 0 Q=1
1 0 1 1 0 Q=1

1 0

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 0 0 1 1 0 1
Q=0

1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’

1 1
0

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 Latches

★ SR Latch
S R Q0 Q Q’
0 0 0 0 1
Q = Q0
0 0 1 1 0
0 1 0 0 1
1 1 0 1 1 0 1
Q=0

0 1 0 0 1 0
Q=1
1 0 1 1 0
1 1 0 0 0 Q = Q’
1 1 1 0 0 Q=
Q’
1 0

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 Latches

★ SR Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q’=0 Invalid

S R Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
1 1 Q0 No
change
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 Latches

★ SR Latch
S R Q
0 0 Q0 No change
0 1 0 Reset
1 0 1 Set
1 1 Q=Q’=0 Invalid

S’ R’ Q
0 0 Q=Q’=1 Invalid
0 1 1 Set
1 0 0 Reset
1 1 Q0 No
change
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 Controlled Latches

★ SR Latch with Control Input

C S R Q
0 x x Q0 No change
1 0 0 Q0 No
1 0 1 0 change
1 1 0 1 Reset
1 1 1 Q=Q’ Set
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Invalid
 Controlled Latches

★ D Latch (D = Data) Timing Diagram

C

Q
C D Q
Output may
0 x Q0 No change t
change
1 0 0 Reset
1 1 1 Set

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 Controlled Latches

★ D Latch (D = Data) Timing Diagram

C

Q
C D Q Output may
0 x Q0 No change change
1 0 0 Reset
1 1 1 Set

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 Triggering of FF
★ State of FF is switched by a momentary change in
the input signal.
★ This momentary change is called a trigger.
★ Sequential ckt can be instable if the output of FF
changing while the output of the combinational ckt
which is input to the FF are being sampled by the
clock pulse.
★ It is not possible to rely on propagation delay of the
logic gates.
★ To ensure, FF are designed to sensitive/responsive
to the pulse transition rather than the pulse
duration. 21
 Flip-Flops

★ Controlled latches are level-triggered

★ Flip-Flops are edge-triggered

CL Positive Edge
K
CL Negative
K Edge

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 Triggering of FF

★ Can be achieved using capacitive coupling

★ Or
★ Using master-slave or edge triggered FF

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 Flip-Flops

★ Master-Slave D Flip-Flop
D D Q D Q Q
D Latch D Latch
C C
(Master) (Slave)
Master Slave
CLK
CL
K
D
Looks like it is negative
edge-triggered QMaster

QSlave 24
 Flip-Flops

★ JK Flip-Flop

J Q
D = JQ’ + K’Q
K Q
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 Flip-Flops

★ T Flip-Flop

T J Q T D Q

Q
K Q

T Q
D = JQ’ + K’Q
D = TQ’ + T’Q = T ⊕ Q
Q
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Flip-Flop Characteristic Tables

D Q D Q(t+1)
0 0 Reset
Q 1 1 Set

J K Q(t+1)
J Q 0 0 Q(t) No change
0 1 0 Reset
K Q 1 0 1 Set
1 1 Q’(t) Toggle

T Q T Q(t+1)
0 Q(t) No change
Q 1 Q’(t) Toggle
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Flip-Flop Characteristic Equations

D Q D Q(t+1)
0 0 Q(t+1) = D
Q 1 1

J K Q(t+1)
J Q 0 0 Q(t)
0 1 0 Q(t+1) = JQ’ + K’Q
K Q 1 0 1
1 1 Q’(t)

T Q T Q(t+1)
0 Q(t) Q(t+1) = T ⊕
Q 1 Q’(t) Q
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 Flip-Flop Characteristic Equations

★ Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
0 0 1 1
J. Q
0 1 0
0 1 1
K. Q 1 0 0
1 0 1
1 1 0
1 1 1

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 Flip-Flop Characteristic Equations

★ Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
0 0 1 1
J Q
0 1 0 0
Reset
0 1 1 0
K Q 1 0 0
1 0 1
1 1 0
1 1 1

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 Flip-Flop Characteristic Equations

★ Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
0 0 1 1
J Q
0 1 0 0
Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0
1 1 1

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 Flip-Flop Characteristic Equations

★ Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
No change
0 0 1 1
J Q
0 1 0 0
Reset
0 1 1 0
K Q 1 0 0 1 Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0

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 Flip-Flop Characteristic Equations

★ Analysis / Derivation
J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1 K
J Q
0 1 0 0 0 1 0 0
0 1 1 0 J 1 1 0 1
K Q 1 0 0 1 Q
1 0 1 1
1 1 0 1
1 1 1 0

Q(t+1) = JQ’ + K’Q

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 Flip-Flops with Direct Inputs

★ Asynchronous Reset

R’ D CLK Q(t+1)
D
0 x x 0
Q

Q
R
Rese
t

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 Flip-Flops with Direct Inputs

★ Asynchronous Reset

R’ D CLK Q(t+1)
D
0 x x 0
Q 1 0 ↑ 0
1 1 ↑ 1
Q
R
Rese
t

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 Flip-Flops with Direct Inputs

★ Asynchronous Preset and Clear

Prese
t
P PR’ CLR’ D CLK Q(t+1)
1 0 x x 0
DRQ

Q
CL
R
Rese
t

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 Flip-Flops with Direct Inputs

★ Asynchronous Preset and Clear

Prese
t
P PR’ CLR’ D CLK Q(t+1)
1 0 x x 0
DRQ
0 1 x x 1
Q
CL
R
Rese
t

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 Flip-Flops with Direct Inputs

★ Asynchronous Preset and Clear

Prese
t
P PR’ CLR’ D CLK Q(t+1)
1 0 x x 0
DRQ
0 1 x x 1
Q 1 1 0 ↑ 0
1 1 1 ↑ 1
CL
R
Rese
t

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 Analysis of Clocked Sequential Circuits

★ The State
● State = Values of all Flip-Flops

Example
AB=00

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 Analysis of Clocked Sequential Circuits

★ State Equations
A(t+1) = DA
= A(t) x(t)+B(t) x(t)
=Ax+Bx
B(t+1) = DB
=
A’(t) x(t)
y(t) = [A(t)+=B(t)]
A’ x’(t)
x
= (A + B) x’
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 Analysis of Clocked Sequential Circuits

★ State Table (Transition Table)

Present Input Next Output
State
State
A B x A B y
0 0 0 0 0 0
0 0 1 0 1 0
0 1 0 0 0 1
0 1 1 1 1 0
1 0 0 0 0 1
1 0 1 1 0 0 A(t+1) = A x + B x
1 1 0 0 0 1 B(t+1) = A’ x
1 1 1 1 0 0
y(t) = (A + B)
t t+1 t x’ 41
 Analysis of Clocked Sequential Circuits

★ State Table (Transition Table)

Present Next State Output
State x=0 x=1 x=0 x=1

A B A B A B y y
0 0 0 0 0 1 0 0
0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
1 1 0 0 1 0 1 0
t t+1 t A(t+1) = A x + B x
B(t+1) = A’ x
y(t) = (A + B)
x’ 42
 Analysis of Clocked Sequential Circuits

★ State Diagram Present Next State Output

State x=0 x=1 x=0 x=1

AB input/outpu y y
A B A B A B
t
0 0 0 0 0 1 0 0
0/0 1/0 0 1 0 0 1 1 1 0
1 0 0 0 1 0 1 0
0/1
1 1 0 0 1 0 1 0
00 10

0/1
1/0 0/1 1/0

01 11
1/0 43
 Analysis of Clocked Sequential Circuits

★ D Flip-Flops
Example:
x D Q A
Present Input Next
y
State CLK Q
State
A x y A
0 0 0 0
A(t+1) = DA = A ⊕ x ⊕
0 0 1 1
0 1 0 1 y
0 1 1 0
1 0 0 1 01,10
1 0 1 0 00,11 0 1 00,11
1 1 0 0 01,10
1 1 1 1
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 Analysis of Clocked Sequential Circuits

★ JK Flip-Flops
Example:
Present Next Flip-Flop
I/P
State State Inputs
A B x A B JA JB
KA KB
0 0 0 0 1 0 0 1 0 JA = B KA = B x’
0 0 1 0 0 0 0 0 1 JB = x’ KB = A ⊕ x
0 1 0 1 1 1 1 1 0
1 0 1 0 0 1 A(t+1) = JA Q’A + K’A QA
0 1 1
1 1 0 0 1 1 = A’B + AB’ + Ax
1 0 0
1 0 0 0 0 0
B(t+1) = JB Q’B + K’B QB
1 0 1
0 0 1 1 1 1 = B’x’ + Abx’ +
1 1 0
A’Bx 45
1 1 1 0 0 0
 Analysis of Clocked Sequential Circuits

★ JK Flip-Flops
Example:
Present Next Flip-Flop
I/P
State State Inputs
A B x A B JA JB
KA KB 1 0 1
0 0 0 0 1 0 0 1 0
00 11
0 0 1 0 0 0 0 0 1
0 1 0 1 1 1 1 1 0 0
0 0
0 1 1 1 0 1 0 0 1
1 0 0 1 1 0 0 1 1
01 10
1 0 1 1 0 0 0 0 0 1
1
1 1 0 0 0 1 1 1 1
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1 1 1 0 0 0
 Analysis of Clocked Sequential Circuits

★ T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 1 0 0 0 TA = B x TB = x
0 1 1 1 0 1 1 0 y =AB
1 0 0 1 0 0 0 0
A(t+1) = TA Q’A + T’A QA
1 0 1 1 1 0 1 1
= AB’ + Ax’ + A’Bx
1 1 0 1 1 0 0 1
B(t+1) = TB Q’B + T’B QB
1 1 1 0 0 1 1 0 =x⊕ 4
 Analysis of Clocked Sequential Circuits

★ T Flip-Flops
Example:
Present Next F.F
I/P O/P
State State Inputs
A B x A B TA TB y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 0
0/0 0/0
0 1 0 0 1 0
00 1/0 01
0 1 1 1 0 1 1 0
1 0 0 1 0 0 0 0 1/0 1/0
1 0 1 1 1 0 1 1 11 10
1 1 0 1 1 0 0 1 0/1 0/0
1/1
1 1 1 0 0 1 1 0
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 Mealy and Moore Models

★ The Mealy model: the outputs are functions of

both the present state and inputs.
● The outputs may change if the inputs change during the
clock pulse period.
♦ The outputs may have momentary false values unless
the inputs are synchronized with the clocks.

★ The Moore model: the outputs are functions of the

present state only.
● The outputs are synchronous with the clocks.

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Mealy and Moore Models

Block diagram of Mealy and Moore state machine

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 Mealy and Moore Models

Meal Moor
Present
y Next Present
e Next
I/P O/P I/P O/P
State State
State State
A x A B y A B x A B y
B 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 0 1 0
0 0 1 0 1 0 0 1 0 0 1 0
0 1 0 0 0 1 0 1 1 1 0 0
0 1 1 1 1 0 1 0 0 1 0 0
1 0 0 0 0 1 1 0 1 1 1 0
1 0 1 1 0 0 1 1 0 1 1 1
1 1 0 0 0 1 1 1 1 0 0 1
1 1 1 1 0 0
For the same state, For the same state,
the output changes with the input the output does not change with the input

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Moore State Diagram

State / Output

0 0
1
00/0 01/0

1 1

11/1 10/0
1
0 0