Intel 8086

Microprocessor
Memory Interfacing
Introduction

o 8086 for that matter no general-purpose processor can operate with

out a main memory
o 8086 uses RAM as its main memory
o Many 8086-based computers are also interfaced with ROM where a
rudimentary operating system (called a monitor program) is also
stored
o Thus, even in the absence of segmentation, usually there will not be
instruction corruption in such computers
o Later with the introduction of operating systems (MS DOS), a hard
disc was introduced the secondary storage
o Those systems still uses a ROM (usually a flash chip) for storing the2
Typical RAM (circa 1975 – 1985)

A0
D0

RAM

DM-1
AN-1
WE
CS OE

3
Why Active Low Control Signals?

o The stray capacitances of the control pins can get charged from
noise voltages, and this may cause the signals to cross the
threshold of ‘high’ level as defined for TTL
o Thus, if the control signals are active high, it may cause wrong
triggering
o On the other hand, an active low signal trigger will happen only
when the line is pulled low deliberately by the controller

4
Address Decoding (not 8086 specific)

o Although a processor can address 1MB of physical memory does

not necessitates we should always interface 1MB memory with it
o The total addressable range by a processor is generally referred
as the system address space or physical address space
o In this case it is from 00000H to FFFFFH
o Assume now I need to interface an 8KB memory with the
processor
o It is not mandatory that this memory needs to be mapped to the
first 8K address space of the processor
o It can be mapped to anywhere in its 1MB address space
o In fact, for 8086, some (non-volatile) memory should be always5
mapped at FFFF0H
Address Decoding (not 8086 specific)

o This is where address decoding comes into

picture
o For an 8KB memory, 13 (log2(8K)) address
lines from the processor needs to be
connected to it
o The remaining address lines should be partly
or completely used to generate chip select
(CS)
o This memory chip is enabled only when CS
signal is
6
 Address Decoding (not 8086 specific)

o If we decide the memory should be mapped in 0x00000H to

0x01FFF (first 8K address space)
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

7
 Address Decoding (not 8086 specific)

o In this case we want to find the address

range to which the memory is mapped
o Negation is present only on A11 signal
o Write upper and lower address values
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1

o Address range is 0xFF000 to 0xFF7FF

8
 Address Decoding Concept

o The basic idea of address decoding is to decode the extra unused

address lines of the processor to specify the address range
o When more chips are to be interfaced, decode the extra address
lines to a different range for each group
o Any logic/logic gate can be used to perform address decoding
o In general, address decoders can be built using:
o Basic logic gates
o Block decoders (e.g. 2 × 4, 3 × 8 …)
o Programmable logic (PLAs, CPLDs etc.)

9
 Address Decoding Using Block Decoders: 74LS138
o A very popular decoder is the 3 to 8 decoder (74LS138)
o The output lines are active low and depending on the selection inputs,
one output line will be low Inputs Outputs
Enable Select
G1 G2 C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

A L X X X X H H H H H H H H
Select
B Y0 X H X X X H H H H H H H H
Inputs Y1
C H L L L L L H H H H H H H
Y2
Y3 H L L L H H L H H H H H H
74LS138 Y4 H L L H L H H L H H H H H
Y5
H L L H H H H H L H H H H
G2A Y6
Enable Y7 H L H L L H H H H L H H H
Inputs G2B
H L H L H H H H H H L H H
G1
H L H H L H H H H H H L H
10
H L H H H H H H H H H H L
 Address Decoding Using Block Decoders: 74LS139
o 74LS139 is a dual 2 to 4-line decoder
o The output lines are active low

Inputs Outputs
1A 1Y0
Select
1B 1Y1 Channel-1 Enabl Select
Inputs e
1Y2 Outputs
Enable
1E 1Y3 E B A Y0 Y1 Y2 Y3
Input
74LS139 H X X H H H H
H L L L H H H
2Y0
2A H L H H L H H
Select 2Y1 Channel-2
2B H H L H H L H
Inputs 2Y2 Outputs
Enable
2E 2Y3 H H H H H H L
Input Decoding Table

11
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

A0 – A 9

A10
A11 RAM
A12 D0 – D 7
1K x 8

A13
A14
A15 CS
A16
A17
A18
A19

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 1 1 1 1 1 1 1 1 1
12
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

A0 – A 9

A10
A11 RAM
A12 D0 – D 7
1K x 8

A13
A14
A15 CS
A16
A17
A18
A19

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 1 1 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 0 1 1 1 1 1 1 1 1 1 1 1 1
13
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

A0 – A 9

A10
A11 RAM
A12 D0 – D 7
1K x 8

A13
A14
A15 CS
A16
A17
A18
A19

A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 1 1 1 1 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1
14
Address Range: 0xFEC00 to 0xFE7FF
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For ROM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
15
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For ROM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
16
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For ROM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
17
Address Range: 0x90000 to 0x9FFFF
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For RAM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
18
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For RAM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
19
 Address Decoding Using Block Decoders: 74LS138

o Address range of the RAM

ROM D0 – D 7
A0 – A15
64K x 8
A16
A17
A18 CS

RAM D0 – D 7
A19 A0 – A15 64K x 8

CS
For RAM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Lower 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address
Upper Address 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
20
Address Range: 0xC0000 to 0xCFFFF
Partial Address Decoding

o We find that in all our discussions so far,

the addresses generated are unique
A13 – A0
and create no ambiguity
o This is also called CS exhaustive CS
decoding RAM ROM
16K x 8 16K x 8
o However, sometimes to reduce the
CS CS
hardware used, only some of the upper
address lines are used for decoding and
this is called partial address decoding
A14
o The problem is that it creates multiple-
mapped memory 21
Partial Address Decoding
A0 – A12

RAM ROM
8K x 8 8K x 8

CS CS

A13
A14

For RAM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
X X X X X 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

o Each location is mapped to 32 addresses 22

Partial Address Decoding
A0 – A12

RAM ROM
8K x 8 8K x 8

CS CS

A13
A14

For ROM
A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

X X X X X 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
X X X X X 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

o Each location is mapped to 32 addresses 23

Data lines to Memory

o The number of data lines to main memory usually depends only

word size of the processor
o A 16-bit microprocessor (generally) will have 16-bit data bus to
memory and a 64-bit processor will have 64-bit data bus to
memory
o Exceptions are there such as 8088, which is architecture-wise
exactly same as 8086 (16-bit processor) has an 8-bit data bus
o 8088 will take 2 memory read cycles to read a 16-bit data where
8086 will complete it in one read cycle (provided it is reading from
an even address)
24
Data lines to Memory

o Companies which produce memory chips, faces a challenge

o Since there are processors with different word size available in
market and their market dynamics keep changing, what should be
the data bus width supported by memory chip?
o Also, the number of transistors they can fit in given silicon area is
limited
o A 2MB memory can be organized as 2Mx8 (2M rows each row
8bits) or 1Mx16 (1M rows each row 16bits)
o If there is high demand for 8-bit processors, 1Mx16 memory can be
used with it effectively only 1MB of memory is used (since only 8
bits from memory is connected to the processor)
25
Idea…

o Since quantum of memory is byte, why not produce only memory

chips with each location corresponding to 1 byte?
o Data bus of these modules can be then concatenated to achieve
the required data bus width (data bus width will be always multiple
of 8)

RAM-2 RAM-1
1Kx8 1Kx8

D7 – D 0 D7 – D 0

D15 – D8 D7 – D 0

Data Bus (D15 – D0) 26

Data lines to Memory

o This technique is used till this day

o You might have noticed we are using DDR memory modules

(DIMMs, or SODIMMs) inside computers
o These modules contain discrete chips each with 8-bit row size
o A 64-bit processor computer will have DDR modules with 8
discrete chips (9 also in case ECC feature is available) 27
Data lines to Memory

SODIMM Module

SODIMM with discrete chips on both sides

28
Memory Address

o We already discussed multiple times the basic unit of memory is

byte (from processor/software perspective)
o But that is not true from memory perspective!!
o From memory perspective, addresses of consecutive locations
increment by 1 irrespective of the size of each location

29
Case 1 (Discrete memory with each location 1
Byte)
1 Byte
Address from Address from
processor perspectivememory perspective
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
Memory

30
Case 2 (Discrete memory with each location 2
Bytes)
2 Bytes
Address from Address from
processor perspectivememory perspective
0 0
2 1
4 2
6 3
8 4
10 5
12 6
14 7
Memory

31
Case 2 (Discrete memory with each location 2
Bytes)
2 Bytes
Address from
memory perspective
0
1
2
3
From processor perspective, 4
this is address 0 5
6
7
Memory

32
Case 2 (Discrete memory with each location 2
Bytes)
2 Bytes
Address from
memory perspective
0
1
2
3
and this is address 1 4
5
6
7
Memory

33
 Case 3 (2 Discrete memories with each location 1 Byte concatenated)

1 Byte 1 Byte
Address from Address from Address from Address from
proc pers Mem pers proc pers Mem pers

1 0 0 0
3 1 2 1
5 2 4 2
7 3 6 3
9 4 8 4
11 5 10 5
13 6 12 6
15 7 14 7
Memory 2 Memory 1
D15 – D8 D7 – D 0
Data Bus (D15 – D0) 34
34
Address Bus to 16-bit discrete memory from
Processor
2 Bytes

A0

A12-A1
Processor

Data Bus (D15-D0)

Memory (4K x 16)

Notice that A0 is left unconnected

35
Address Bus to 16-bit discrete memory from
Processor

o If processor reads from address 0,

Eg: mov rx,0
o From memory perspective read is
happening from location 0
o If processor is expecting a 16-bit
data, it can use the 16-bit data
received from memory
o If it is expecting 8-bit data, it can
use the lower 8 bits of received
data
36
Address Bus to 16-bit discrete memory from
Processor
o If processor reads from address 1,
Eg: mov rx,1
o From memory perspective read is
still happening from location 0
(Because A0) is not connected to
memory
o If the processor is expecting an 8-bit
data, it needs to choose the upper 8
bits from the received data
o It can not access 16-bit data from an
odd starting address !!
o How to handle 8-bit write 37
Main takeaways

o From software/processor the quantum of memory is byte, and each

byte has a unique address
o From memory perspective, one memory location has a unique
address, it may be byte, word, dword or qword
o To satisfy the databus width of the processor, discrete memory
chips with sufficient databus width or concatenated discrete
memory chips can be used
o When connecting address bus from processor to memory chip
address lines (discrete or concatenated), do not connect
log2(dataBusWidth/8) lower address lines from the processor
o If a data element (eg: 4-byte int) is stored multiple rows of memory,
38
processor will require multiple read operations to access it
8086 Memory Interfacing

39
8086 Memory Interfacing

o 8086 has a 16-bit memory bus –

which means that data transfer CS CS

(read/write) can occur at a

maximum rate of 16 bits (one Memory 2 Memory 1
word) per bus cycle
o But byte transfer and word transfer
must be possible
o So, the first step is to use discrete (D15 – D8) (D7 – D0)
1-byte wide memories to generate
Data bus (D15 – D0)
16-bit data (refer back to case-3 of
memory interfacing)
o These can be individually enabled 40
Memory Banks

o A 16-bit word is obtained as the concatenation of two bytes in two

‘memory banks’ i.e., memory is organized as two banks
o One, the upper bank or high bank with the data corresponding to
the upper byte D8 – D15, the other, the lower bank or low bank
which has the data lines D0 – D7
o The upper bank is also called the odd memory bank, because it
has the odd addresses mapped to it
o The lower bank is called the even bank

41
 Memory Banks
HIGH/ODD Bank LOW/EVEN Bank
1 Byte 1 Byte

Address from Address from Address from Address from

proc pers Mem pers proc pers Mem pers

1 0 0 0
3 1 2 1
5 2 4 2
7 3 6 3
9 4 8 4
11 5 10 5
13 6 12 6
15 7 14 7

D15 – D8 D7 – D 0

Data Bus (D15 – D0) 42

Memory Banks Access
Case 1 : Byte access
o Notice that whenever a byte of
data is accessed (read/write)
from EVEN bank, A0 line from the
processor will be 0
o The address from memory
perspective is half of that from
the processor (21, 42 etc.)
o That means A0 can be used to
enable the chip (part of
address decoding) and starting
from A1 connect address bus to 43
Memory Banks Access
Case 1 : Byte access
o Whenever a byte of data is
accessed (read/write) from ODD
bank, A0 line from the processor
will be 1 and address from
memory will be
ceil(processor_Addresss/2)
o So can we negate A0 and use it
to enable EVEN bank?
o That would have been possible if
8086 supported only byte
access, but it need support word 44
Memory Banks Access
Case 1 : Byte access
o In order to overcome this issue
was introduced
o Whenever the processor wants to
access data from EVEN bank
(byte/word), is made 0
o Thus, it can be used to enable to
EVEN bank
o Still A0 will not be connected to
address lines of EVEN bank
o A0 is sometimes referred as
45
since it acts as chip enable low
Memory Banks Access
Case 2 : Word access
o When the processor wants to
access 16-bit data starting from
an even address, A0 will be
naturally 0 and is asserted
(made 0)
o This activates both banks and
either 16-bit data gets written to
memory or the processor
receives 16-bit data (depending
on write/read operation)
46
Memory Banks Access
Case 2 : Word access
o When the processor wants to
access 16-bit data starting from
an odd address, A0 will be 1
o This means this operation cannot
be done in single machine cycle
o In the first cycle, is asserted and
ODD bank is activated
o In the second cycle, address is
incremented (A0 becomes 0), is
de-asserted and EVEN bank is
47
accessed
Memory Banks Access

Addre Access Example Instruction A0 Bank #of

ss type accessed machine
cycles

even byte mov al,[0000] 1 0 Low 1

odd byte mov al,[0001] 0 1 High 1
even word mov ax,[0000] 0 0 Both 1
odd word mov ax,[0001] 0 1 High 1 2
1 0 Low 1

48
8086 Example Memory interface

A0
Address
Decoder

(A19 – A16)
CS CS
RAM RAM
32Kx8 32Kx8
(A19 – A0) (A15 – A1) (A15 – A1)

(Odd (Even
Bank) Bank)

(D15 – D8) (D7 – D0)

Data bus (D15 – D0)

49
Odd Addresses Word
o For accessing a word whose address is odd, two machine cycles are
expended
o To avoid this, the EVEN assembly directive can be used to align
memory accesses at even addresses
.data
NUMS db 7 dup(5)
even ;store next data at next even address
WDR DW 2345H
o However, this obviously wastes one byte space, and memory is
fragmented
o This situation cannot be avoided if speed is to be optimized
50
o Note: even not supported in emu8086, but supported in MASM
Example Case
o Interface 4KB ROM starting at address 00000H and 8KB RAM
starting at address 08000H with the 8086 processor.
o The memory chips available are 2Kx8B RAMs and ROMs
o One way to approach the problem is to decide the number of chips
required
o We need 4KB ROM and 2KB ROMs are available. So total 2 ROM
chips we need
o We need 8KB RAM and 2KB RAMs are available. So total 4 RAM
chips we need
o Now remember for 8086 byte-wide memories always grouped as set
of 2
51
Example Case
o So we have one set of ROM and 2 sets of RAM
o Now we need to decide the address mapping
o For the ROM set (ROM-1), starting address : 00000H
ending address (00000H + 4K-1): 00FFFH
For first RAM set (RAM-1), starting address : 08000H
ending address (8000H + 4K-1) : 08FFFH
For second RAM set (RAM-2), startng address (8000H+4K) : 09000H
ending address(9000H+4K-1) : 09FFFH

52
 Example Case
o Now write the address mapping in binary
ROM1: 0000H – 00FFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM1: 08000H – 08FFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
RAM2: 09000H – 09FFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 53
0
0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
Example Case
o Now using decoder generate the enable signals
BHE A0
S ROM1 ROM1E
O0
A16 A E
L O1 ROM1O
A15 B E
A12 C RAM1 RAM1E
C T O2

A17 LS138O3 RAM1O

A18
A19 E O4
G1 N O5 RAM2 RAM2E
A14 G2A A
A13 B RAM2O
G2B L O6
54
E
O7
Example Case
Odd memory Bank Even memory Bank
RAM2O RAM2E
RAM1O
ROM1O RAM1E

A11 A10 D15 –D8 A11 ROM1E

D7 –D0
A10
2K
2K

A1 A0 A1
A17 CS A0
A18 CS
A19

G1
7
A12 C 4 A0
BHE
A15 B 1
3 3
A16 A 2
8
0
G2A G2B
55

A13 A14
 Decoder using discrete gates Even memory Bank
Odd memory Bank
RAM2O RAM2E
RAM1O
ROM1O RAM1E
A11 A10 D15 –D8 A11 ROM1E
D7 –D0
A10
A16 2K
A17 2K
A18 A0 A1
A1
A19
X0
CS A0
CS
A13
A14

A12 RO1
A0
A15
BHE
ROM1
A12 RA1
A15 RAM1

RAM2
A12 RA2
A15 56
Example Case
Memory Requirements
o 128K of ROM from 00000H
o 128K of ROM from E0000H
o Rest of the address for RAM
Chips available:
o 64 KB ROM chip 4 nos.
o 128 KB RAM chip 6 nos.
o LS138 2 nos.
Use Absolute Addressing
Only System Bus Signals available
57
Example Case
Check number of Chips
128K ROM starting from 00000H  2 ROM chips
128K ROM starting from E0000H  2ROM chips
Total 4 ROM chips and enough chips are available
ROM-1 End address 00000H + 128K-1 = 1FFFFH
ROM-2 Start address E0000H
Memory in between = C0000H
Number of RAM chips required = C0000KB/128KB = 6 (3 sets of even
and odd. Each set is 256 KBytes)
ROM-2 End address = E0000H+128K-1 = FFFFFH
That is the end of system memory space. So, no RAM after that
58
Total 6 RAM chips and enough of chips are available
Example Case
Address mapping

Memory Start Address End Address

Banks
ROM1 00000H 1FFFFH
ROM2 E0000H FFFFFH
RAM1 20000H 5FFFFH
RAM2 60000H 9FFFFH
RAM3 A0000H DFFFFH

59
 Example Case
Address mapping
ROM1: 00000H – 1FFFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

ROM2: E0000H – FFFFFH

A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

60
 Example Case
Address mapping
RAM1: 20000H – 5FFFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

o What just happened?

o Memory alignment problem!!
o The starting address of mapped memory is not a multiple of physical
discrete memory chips (Here starting address is 20000H and
memory chip size is 256 KB (8086 size should be the total size of a
set, EVEN and ODD)) 61
 Example Case
Address mapping
RAM1: 40000H – 7FFFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

RAM2: 80000H – BFFFFH

A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
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 Example Case
Address mapping
RAM3: C0000H – FFFFFH
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

o But RAM is encroaching the ROM area now!!

o So, RAM can be mapped (with the available discrete chips) only from
40000H to BFFFFH
o There is a memory gap from 20000H to 3FFFFH and C0000H to
5FFFFH
63
Example Case
Generation of Control signals

o It is possible that some I/O peripheral has the same address as that
of a memory (ROM/RAM)
o So blindly generating CS only based on address may cause issue
o We should also check whether processor is accessing memory or IO
o Based on the memory read/write signals are generated

64
Example Case
Generation of Control signals
M/IO
IORD
RD

WR IOWR

BHE MEMRD_O
MEMRD
A0 MEMRD_E

BHE MEMWR_O
MEMWR

A0 MEMWR_E

65
Example Case
Generation of Chip Select

A18
A19
RAM1
RAM2

Vcc

o We need another decoder to connect the ROM if exhaustive

decoding needs to be used

66
Example Case
Generation of Chip Select

A18
A19 ROM1
RAM1
RAM2
ROM2

Vcc

o What is the implication here?

67
 WR’ RD’ WR’ RD’
WR’ RD’ WR’ RD’
D7 –D0
A18 A16 A15 D15 –D8 A16 A15
A19

ROM2O

ROM2E
ROM1

ROM1O

ROM1E
A17
64K 64K
A0 BHE
ROM2

A1 A0 CS’ A1 A0 CS’
CS’ CS’

Vcc
WR’ RD’ WR’ RD’
WR’ RD’ RD’
A18
WR’
D7 –D0
A17 A16 A17 A16

RAM2E
A19 D15 –D8

RAM1E
RAM2O
RAM1O
RAM1
RAM2
A0 BHE 128
128 K
A1 AK
0
CS’ A1 A0 CS’
CS’ CS’

Vcc
Example Case

Check what happens if you had RAM

and ROM discrete chips both of size
64KB

69
 Thank you
any questions

70