Adder

‫آزمون ميان ترم‬

‫• یکشنبه ‪ 18‬اردیبهشت‪،‬‬
‫ساعت ‪ 10:45‬تا ‪12:15‬‬
‫• کتبی‬

‫‪2‬‬
 Half Adder (HA)
 Add single bits
Ai Bi Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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 Half Adder (HA)
 Add single bits
Ai 0 1 Ai
Ai Bi Sum Carry 0 1
Bi Bi
0 0 0 0 0 0 1 0 0 0
0 1 1 0
1 0 1 0 1 0
1 1 0 1
1 1 0 1

Sum = Ai Bi + Ai Bi Carry = Ai . Bi

= AiBi

Ai
Sum
Bi

Carry

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 Full Adder
 Add multiple bits
A3 B3 A2 B2 A1 B1 A0 B0

+ + + +

S3 C3 S2 C2 S1 C1 S0

5
 Full Adder (FA)
AB
A B CI S CO CI 00 01 11 10
0 0 0 0 0 0 0 1 0 1
0 0 1 1 0 S
0 1 0 1 0 1 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1 AB
1 1 0 0 1 CI 00 01 11 10
1 1 1 1 1 0 0 0 1 0
CO
S = CI xor A xor B 1 0 1 1 1

CO = B CI + A CI + A B = CI (A + B) + A B

A
A
B
B
CI CO
S
CI
A
B

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 Full Adder Using 2 Half Adders

 A full adder can also be realized with two half adders and an OR
gate, since Ci+1 can also be expressed as:
 Ci+1 = AiBi + (Ai  Bi)Ci
and Si = (Ai  Bi)  Ci

Ai
Bi Si

Ci+

Ci 1
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Example: 4-bit Ripple Carry Adder
C4 C3 C2 C1 C0

A3 A2 A1 A0

+B3 B2 B1 B0

--------------
S3 S2 S1 S0

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 Ripple Carry Adder Delay Analysis
@0 A @1 @t+1
late B @0 A
@0
arriving @0 B
@t CI CO
signal S
@0 A @t+2 @t CI @t+1
@0 B
@1
 Ripple Carry Adder Delay Analysis
@0 A @1 @t+1
late B @0 A
@0
arriving @0 B
@t CI CO
signal S
@0 A @t+2 @t CI @t+1
@0 B
@1

@0 A @1 @t+1 A
late @0 B B
arriving @t CI CO CO
signal CI
@0 A A
@0 B B
@1
 Ripple Carry Adder Delay Analysis
@0 A @1 @t+1
late B @0 A
@0
arriving @0 B
@t CI CO
signal S
@0 A @t+2 @t CI @t+1
@0 B
@1

@0 @0 @0 @0 @0 @0 @0 @0

@0

@9 @7 @5 @3

@4 @2

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 Carry Lookahead Adder
• Carry Generate
 Gi = Ai Bi must generate carry when A = B = 1
• Carry Propagate
 Pi = Ai xor Bi carry-in will equal carry-out here

• Sum and Carry can be reexpressed in terms of

generate/propagate:

Si = Ai xor Bi xor Ci = Pi xor Ci

Ci+1 = Ai Bi + Ai Ci + Bi Ci

= Ai Bi + Ci (Ai + Bi)

= Ai Bi + Ci (Ai xor Bi)

= Gi + Ci Pi

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 Carry Lookahead Adder
C1 = G0 + P0 C0

C2 = G1 + P1 C1
= G1 + P1 (G0 + P0 C0)
= G1 + P1 G0 + P1 P0 C0

C3 = G2 + P2 C2
= G2 + P2 (G1 + P1 G0 + P1 P0 C0)
= G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0

C4 = G3 + P3 C3
= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0 + P3 P2 P1 P0 C0

 Each of the carry equations can be implemented in a

two-level logic network

 Variables are the adder inputs and carry in to stage 0!

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 CLA
@0 Ai
Pi @1
@0 Bi

Si @t+1
@t Ci

Gi @1

C0 C0 C0
P0 C1 P0 P0
P1 P1
G0 P2 P2
G0 P3
P1 G0
C0 P2 P1
P0
P2
P1 G1 C3 P3
G0 P2
C2 G1
P1
P2
G2 P3
G1 C4
G2
P3

G3
 Increasingly complex logic
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 Ripple Carry Adder Delay Analysis
@0 C0
P0 @0Ai
P1
P2 @0Bi
Pi @1
G0
@1 Si @t+1
P1
P2 @t Ci
G1 C3 Gi @1
P2
G2

@0 @0 @0 @0 @0 @0 @0 @0

@0

@3 @3 @3 @3

@4 @4 @4 @2

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 Delay Analysis of CLA

 NOTE: This assumes all gate delay are same.

 Not true, delays depend on fan-ins and fan-out

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 Cascaded CLA

CLA CLA CLA

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 Adder/Subtractor
A - B = A + (-B) = A + B’ + 1

A3 B 3 A2 B2 A1 B1 A0 B 0

A B A B A B A B

CO + CI CO + CI CO + CI CO + CI Add/Subtract

S S S S

S3 S2 S1 S0

Overflow

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 Adder/Subtractor
A - B = A + (-B) = A + B’ + 1

A 3 B 3 B3 A 2 B2 B2 A 1 B1 B1 A 0 B 0 B0

0 1 Sel 0 1 Sel 0 1 Sel 0 1 Sel

A B A B A B A B

CO + CI CO + CI CO + CI CO + CI Add/Subtract

S S S S

S3 S2 S1 S0

Overflow

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4-bit Binary Adder/Subtractor (cont.)

S=0

B3 B2 B1 B0
0

S=0 selects addition

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4-bit Binary Adder/Subtractor (cont.)

S=1

B3’ B2’ B1’ B0’

1

S=1 selects subtraction

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 Overflow Detection in
Signed-2’s Complement

V
Cn-1
Cn
C n-bit Adder/Subtractor

• C =1 indicates overflow condition when adding/subtr. unsigned numbers.

• V=1 indicates overflow condition when adding/subtr. signed-2’s
complement numbers

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 4-Bit ALU
• 74181 TTL ALU
 Arithmetic-Logic Unit
Selection M=1 M = 0, Arithmetic Functions
S3 S2 S1 S0 Logic Function Cn = 0 Cn = 1
0 0 0 0 F = not A F = A minus 1 F=A
0 0 0 1 F = A nand B F = A B minus 1 F=AB
0 0 1 0 F = (not A) + B F = A (not B) minus 1 F = A (not B)
0 0 1 1 F=1 F = minus 1 F = zero
0 1 0 0 F = A nor B F = A plus (A + not B) F = A plus (A + not B) plus 1
0 1 0 1 F = not B F = A B plus (A + not B) F = A B plus (A + not B) plus 1
0 1 1 0 F = A xnor B F = A minus B minus 1 F = (A + not B) plus 1
0 1 1 1 F = A + not B F = A + not B F = A minus B
1 0 0 0 F = (not A) B F = A plus (A + B) F = (A + not B) plus 1
1 0 0 1 F = A xor B F = A plus B F = A plus (A + B) plus 1
1 0 1 0 F=B F = A (not B) plus (A + B) F = A (not B) plus (A + B) plus 1
1 0 1 1 F=A+B F = (A + B) F = (A + B) plus 1
1 1 0 0 F=0 F=A F = A plus A plus 1
1 1 0 1 F = A (not B) F = A B plus A F = AB plus A plus 1
1 1 1 0 F=AB F= A (not B) plus A F = A (not B) plus A plus 1
1 1 1 1 F=A F=A F = A plus 1

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4-Bit ALU

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 BCD Addition

Addition:

5 = 0101 5 = 0101
Problem
3 = 0011 8 = 1000 when digit
sum exceeds 9
1000 = 8 1101 = 13!

Solution: add 6 (0110) if sum exceeds 9!

5 = 0101 9 = 1001

8 = 1000 7 = 0111

1101 1 0000 = 16 in binary

6 = 0110 6 = 0110

1 0011 = 1 3 in BCD 1 0110 = 1 6 in BCD

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 ‫اعداد در مبناهاي مختلف‬

Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

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 BCD Adder
A3 B3 A2 B2 A1 B1 A0 B0

CO FA CI CO F A CI CO FA CI CO FA CI Cin

S S S S

Cout S3 S2 S1 S0

Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

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 BCD Adder
A3 B3 A2 B2 A1 B1 A0 B0

CO FA CI CO F A CI CO FA CI CO FA CI Cin

S S S S

11XX
A1

1X1X
A2

CO F A CI CO FA CI 0

S S

Cout S3 S2 S1 S0

Add 0110 to sum whenever it exceeds 1001 (11XX or 1X1X)

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