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03_verilog

The document provides an overview of Hardware Description Languages (HDLs) such as VHDL and Verilog, which describe circuits and systems in text for simulation and synthesis. It explains the processes of simulation, synthesis, and the use of testbenches, along with examples of HDL syntax and constructs. Additionally, it covers Boolean expressions, built-in and user-defined primitives, and mentions ModelSim as a widely used simulator in the industry.

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ahmadshekibhaidari82
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© © All Rights Reserved
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5 views

03_verilog

The document provides an overview of Hardware Description Languages (HDLs) such as VHDL and Verilog, which describe circuits and systems in text for simulation and synthesis. It explains the processes of simulation, synthesis, and the use of testbenches, along with examples of HDL syntax and constructs. Additionally, it covers Boolean expressions, built-in and user-defined primitives, and mentions ModelSim as a widely used simulator in the industry.

Uploaded by

ahmadshekibhaidari82
Copyright
© © All Rights Reserved
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
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Hardware Description

Language

HDL
Hardware Description
Language
• HDL
 Describes circuits and systems in text.
− As a software program.
 Can be processed by computers.
 VHDL, Verilog, AHDL, SystemC.
• Applications:
 Simulation
 Synthesis

2
Simulation and Synthesis
• Simulation
 Input waveform and circuit description -->
Output waveform
 Predicts circuit behavior before fabrication
(debug before physical implementation).

‫برنامه‬ ‫کامپاي‬ ‫اجرا‬


‫نويسي‬ ‫ل‬
‫ويراي‬
‫ش‬

3
Simulation and Synthesis
• Synthesis
 Automatic design.
 Software program takes design description
and tries to find the circuit

‫ورود طرح‬ ‫کامپاي‬ ‫شبيه‬ ‫سنتز‬ ‫شبيه‬


‫ل‬ ‫سازي‬ ‫سازي‬
‫ويراي‬
‫ويراي‬
‫ش‬
‫ش‬

4
Verilog HDL
 Verilog or VHDL?
− Similar concepts, different syntax
 Similar to C/C++ Syntax
− Case sensitive,
− Comments: //
− ; at the end of each statement

5
Example
• module:
 Hardware component
• Ports:
 As function parameters
− But must specify input or output
• wire:
 Intermediate signals

//HDL Example 3-1


x
//--------------------------
module smpl_circuit(A,B,C,x,y);
input A,B,C;
output x,y; y
wire e;
and g1(e,A,B);
not g2(y, C);
or g3(x,e,y);
endmodule • Concurrent Execution
 Order not important.

6
Delays
• Timescale:
 ‘timescale 1ns/100ps
− 1ns: time unit
− 100ps: precision (unit used for rounding)
− Default: 1ns/100ps (0.1 ns)
• Gate Delays:
 Used by simulator to generate correct waveforms

7
Delays
//HDL Example 3-2
//---------------------------------
//Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule

8
Testbench
• Testbench:
 Program written to test the circuit
 Sets the input values,
− Changes them over time.
 Instantiates the module(s).
 Inputs by reg (generally in
sequential constructs)
 Outputs by wire

9
Testbench Example
//HDL Example 3-3
//----------------------
• Testbench:
//Stimulus for simple circuit
module stimcrct;  Doesn’t have port.
reg A,B,C;
wire x,y;  Instantiation.
circuit_with_delay cwd(A,B,C,x,y);
initial  <size>’<base><value>
begin
A = 1'b0; B = 1'b0; C = 1'b0;
− Base: b, o, d, h
#100 − 32’d87
A = 1'b1; B = 1'b1; C = 1'b1;
#100 $finish;  ABC = “000”  “111”
end
endmodule  100ns delay.
 Finishes at 200ns.
//Description of circuit with delay
module circuit_with_delay (A,B,C,x,y);
input A,B,C;
output x,y;
wire e;
and #(30) g1(e,A,B);
or #(20) g3(x,e,y);
not #(10) g2(y,C);
endmodule

10
Testbench Example

11
Boolean Expressions
 & AND
 | OR
 ~ NOT
− assign x = (A & B) | ~C;

//HDL Example 3-4


//------------------------------
//Circuit specified with Boolean equations
module circuit_bln (x,y,A,B,C,D);
input A,B,C,D;
output x,y;
assign x = A | (B & C) | (~B & C);
assign y = (~B & C) | (B & ~C & ~D);
endmodule

12
Primitives
• Built-in Primitives:
 and, or, not, nand, nor, xor, xnor, buf.
• User-Defined Primitives (UDP):
 User can define by truth table.

13
Primitives
• User-Defined Primitives (UDP):
 User can define by truth table.
 Use primitive keyword (instead of module)
 Only one output but many inputs
− first output, then inputs
 Inputs’ order must correspond with the truth table.
 Truth table between table and end table.

14
UDP
//HDL Example 3-5
//-----------------------------------
//User defined primitive(UDP)
primitive crctp (x,A,B,C);
output x;
input A,B,C;
//Truth table for x(A,B,C) = Minterms (0,2,4,6,7)
table
// A B C : x (Note that this is only a comment)
0 0 0 : 1;
0 0 1 : 0;
0 1 0 : 1;
0 1 1 : 0;
1 0 0 : 1;
1 0 1 : 0;
1 1 0 : 1;
1 1 1 : 1;
endtable
endprimitive

15
UDP Usage
 Usage: much the same way as a
system-defined primitives:

crctp #(20) myInstance(w, x, y, z);

16
Simulation
• ModelSim:
 An industrial and widely used
simulator
 $25K

17

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