03_verilog C Examples
03_verilog C Examples
Language
(Examples)
HDL
Majority Circuit
2
Majority Circuit
`timescale 1ns/100ps
module maj3 (a, b, c, y);
input a, b, c;
output y;
wire im1, im2, im3;
and #(4)
(im1, a, b),
(im2, b, c),
(im3, c, a);
or #(3) (y, im1, im2, im3);
endmodule
3
Delays
4
Delays
5
Delays
`timescale 1ns/100ps
module xor3_mtm (a, b, c, y);
input a, b, c;
output y;
wire a_, b_, c_;
wire im1, im2, im3, im4;
not #(2)
( a_, a ),
( b_, b ),
( c_, c );
nand #(3)
( im1, a_, b_, c ),
( im2, a_, b, c_ ),
( im3, a, b_, c_ ),
( im4, a, b, c );
nand #(3) (y, im1, im2, im3, im4);
endmodule