Chapter 8: Memory Management

• Background(8.1)
• Swapping (8.2)
• Contiguous Memory Allocation(8.3)
• Paging(8.4)
• Structure of the Page Table(8.5)
• Segmentation(8.6)
 Objectives

o To provide a detailed description of various ways of

organizing memory hardware
o To discuss various memory-management techniques,
including paging and segmentation
o To provide a detailed description of the Intel Pentium,
which supports both pure segmentation and
segmentation with paging
 8.1 Background

8.1 .1 Basic Hardware

• Program must be brought (from disk) into memory and placed within
a process for it to be run
• Main memory and registers are only storage CPU can access directly
• Memory unit only sees a stream of addresses + read requests, or
address + data and write requests
• Register access in one CPU clock (or less)
• Main memory can take many cycles, causing a stall, since it does not
have the data required to complete the instruction that it is executing.
• Cache sits between main memory and CPU registers. A memory
buffer used to accommodate a speed differential, called cache.
• Protection of memory required to ensure correct operation
 Base and Limit Registers
• A pair of base and limit registers define the logical address space
• CPU must check every memory access generated in user mode to be sure
it is between base and limit for that user.
• The base and limit registers can be loaded only by the operating system,
which uses a special privileged instructions.
• Since privileged instructions can be executed only in kernel mode, only
the OS can load the base and limit registers.
Hardware Address Protection
 8.1.2 Address Binding
● Programs on disk, ready to be brought into memory to execute form an
input queue.
● As the process executed, it access instructions and data from memory.
● The address space of the computer starts at 0000, the first address of the
user process need not be 0000.
● It affects the addresses that the user program can use.
● Further, addresses represented in different ways at different stages of a
program’s life
● Source code addresses usually symbolic
● Compiled code addresses bind to relocatable addresses
4 i.e. “14 bytes from beginning of this module”
● Linker or loader will bind relocatable addresses to absolute addresses
4 i.e. 74014
● Each binding maps one address space to another
 Binding of Instructions and Data to Memory

• Address binding of instructions and data to memory

addresses can happen at three different stages
• Compile time: If memory location known a priori,
absolute code can be generated; if starting location
changes we must recompile the code.
• Load time: Must generate relocatable code if
memory location is not known at compile time
• Execution time: Binding delayed until run time if
the process can be moved during its execution from
one memory segment to another
• Need hardware support for address maps (e.g.,
base and limit registers)
Multistep Processing of a User Program
 8.1.3 Logical vs. Physical Address Space

● The concept of a logical address space that is bound to a separate

physical address space is central to proper memory management
● Logical address – generated by the CPU; also referred to as
virtual address
● Physical address – address seen by the memory unit
● Logical and physical addresses are the same in compile-time and load-
time address-binding schemes; logical (virtual) and physical addresses
differ in execution-time address-binding scheme
● Logical address space is the set of all logical addresses generated by a
program
● Physical address space is the set of all physical addresses generated by
a program
Memory-Management Unit (MMU)

•Hardware device that maps virtual to physical address

•In MMU scheme, the value in the relocation register is added to
every address generated by a user process at the time it is sent to
memory
•The user program deals with logical addresses; it never sees the
real physical addresses
Dynamic relocation using a relocation register
8.1.4 Dynamic Loading
•Routine is not loaded until it is called
•Better memory-space utilization; unused routine is never loaded
•Useful when large amounts of code are needed to handle
infrequently occurring cases
•No special support from the operating system is required
implemented through program design
8.1.5 Dynamic Linking and Shared Libraries
•Linking postponed until execution time
•Small piece of code, stub, used to locate the appropriate memory-
resident library routine
•Stub replaces itself with the address of the routine, and executes the
routine
•Operating system needed to check if routine is in processes’
memory address
•Dynamic linking is particularly useful for libraries
•System also known as shared libraries
 8.2 Swapping
● A process can be swapped temporarily out of memory to a backing store,
and then brought back into memory for continued execution
● Total physical memory space of processes can exceed physical
memory
● Backing store – fast disk large enough to accommodate copies of all
memory images for all users; must provide direct access to these memory
images
● Roll out, roll in – swapping variant used for priority-based scheduling
algorithms; lower-priority process is swapped out so higher-priority
process can be loaded and executed
● Major part of swap time is transfer time; total transfer time is directly
proportional to the amount of memory swapped
● System maintains a ready queue of ready-to-run processes which have
memory images on disk
• Does the swapped out process need to swap back in to same
physical addresses?
• Depends on address binding method
• Plus consider pending I/O to or from process memory space.
• Ex : Let us assume the user process is 100MB in size and
the backing store is a standard hard disk with a transfer rate
of 50MB per second.

• Modified versions of swapping are found on many systems (i.e.,

UNIX, Linux, and Windows)
• Swapping normally disabled
• Started if more than threshold amount of memory allocated
• Disabled again once memory demand reduced below
threshold
Schematic View of Swapping
 Context Switch Time including Swapping

• If next processes to be put on CPU is not in memory, need to

swap out a process and swap in target process
• Context switch time in such a swapping system is very high.
• 100MB process swapping to hard disk with transfer rate of
50MB/sec
• Swap out time of 2000 ms
• Plus swap in of same sized process
• Total context switch swapping component time of 4000ms
(4 seconds)
• Can reduce if reduce size of memory swapped – by knowing
how much memory really being used
• System calls to inform OS of memory use via
request_memory() and release_memory()
 Context Switch Time and Swapping

● Other constraints as well on swapping

● Pending I/O – can’t swap out as I/O would occur to
wrong process
● Or always transfer I/O to kernel space, then to I/O
device
4 Known as double buffering, adds overhead
● Standard swapping is not used in modern operating
systems
● But modified version common
4 Swap only when free memory extremely low
 8.3 Contiguous Memory Allocation
● Main memory must support both OS and various user processes.
● Limited resource, must allocate efficiently.
● Contiguous allocation is one of the early method
● Main memory usually into two partitions:
● Resident operating system, usually held in low memory with
interrupt vector
● User processes then held in high memory
● Each process contained in single contiguous section of
memory
 8.3.1 Memory Mapping and Protection
• It can provide these features by using a relocation register, together with a limit register.
• The relocation register contains the value of the smallest physical address, the limit
register contains the range of logical addresses.
• Example :Relocation=100040 and limit=74600
• With relocation and limit registers, each logical address must be less than the limit
register, the MMU maps logical address dynamically by adding the value in the
relocation register.
• This mapped address is sent to memory.
• When CPU scheduler select a process fro execution, the dispatcher loads the relocation
and limit registers with the correct values as part of the context switch.
• The relocation register scheme provides an effective way to allow the OS size to change
dynamically.
• If the device drivers is not commonly used, we do not keep the code and data in
memory, as we can’t be able use that space for other purposes.
• Such code is sometimes called transient OS code.
● Relocation registers used to protect user processes from each other, and
from changing operating-system code and data
● Base register contains value of smallest physical address
● Limit register contains range of logical addresses – each logical
address must be less than the limit register
● MMU maps logical address dynamically
● Can then allow actions such as kernel code being transient and
kernel changing size
 8.3.2 Memory Allocation
• The main memory has to accommodate both the operating system and userspace.
Now, here the userspace has to accommodate various user processes.
• We also want these several user processes must reside in the main memory at the
same time.
• Contiguous memory allocation, when the process arrives from the ready queue to the
main memory for execution, the contiguous memory blocks are allocated to the
process according to its requirement.
• Now, to allocate the contiguous space to user processes, the memory can be divide
either in the fixed-sized partition or in the variable-sized partition.
• Static and Dynamic Partition

• Fixed-Sized Partition(Static)
• In the fixed-sized partition, the memory is divided into fixed-sized blocks and each
block contains exactly one process.
• But, the fixed-sized partition will limit the degree of multiprogramming as the number
of the partition will decide the number of processes.
• Variable-Size Partition(Dynamic)
• In the variable size partition method, the operating system maintains a table that
contains the information about all memory parts that are occupied by the processes
and all memory parts that are still available for the processes.
• Initially, the whole memory space is available for the user processes as a large block,
a hole. Eventually, when the processes arrive in the memory, executes, terminates and
leaves the memory you will see the set of holes of variable sizes.
• EX: when file A and file C release the memory allocated to them, creates the holes in
the memory of variable size.
Multiple-partition allocation
● Hole – block of available memory; holes of various size are scattered
throughout memory
● When a process arrives, it is allocated memory from a hole large enough to
accommodate it
● Operating system maintains information about:
a) allocated partitions b) free partitions (hole)
Hardware Support for Relocation and Limit Registers
• In the variable size partition method, the operating system analyses the
memory requirement of the process and see whether it has a memory block
of the required size.
• If it finds the match, then it allocates that memory block to the process. If
not, then it searches the ready queue for the process that has a smaller
memory requirement.
• The operating system allocates the memory to the process until it cannot
satisfy the memory requirement of the next process in the ready queue.
• It stops allocating memory to the process if it does not have a memory block
(hole) that is large enough to hold that process.
• . If the memory block (hole) is too large for the process it gets spilt into two
parts. One part of the memory block is allocated to the arrived process and
the other part is returned to the set of holes.
• When a process terminates and releases the memory allocated to it, the
released memory is then placed back to the set of holes.
• The two holes that are adjacent to each other, in the set of holes, are
merged to form one large hole.
• Now, at this point, the operating system checks whether this newly formed
free large hole is able to satisfy the memory requirement of any process
waiting in the ready queue. And the process goes on.
• The operating system uses either the block allocation list or the bit map to
select the hole from the set of holes.
• Block Allocation List
• Block allocation list maintains two tables. One table contains the entries of
the blocks that are allocated to the various files. The other table contains the
entries of the holes that are free and can be allocated to the process in the
waiting queue.
• Now, as we have entries of free blocks which one must be chosen can be
decided using either of these strategies: first-fit, best-fit, worst-fit strategies.
.
 Dynamic Storage Allocation problem
1. First-fit
•Here, the searching starts either at the beginning of the table or from where the
previous first-fit search has ended. While searching, the first hole that is found to
be large enough for a process to accommodate is selected.
2. Best-fit
•This method needs the list of free holes to be sorted according to their size.
Then the smallest hole that is large enough for the process to accommodate is
selected from the list of free holes. This strategy reduces the wastage of memory
as it does not allocate a hole of larger size which leaves some amount of
memory even after the process accommodates the space.
3. Worst-fit
•This method requires the entire list of free holes to be sorted. Here, again the
largest hole among the free holes is selected. This strategy leaves the largest
leftover hole which may be useful for the other process.
 8.3.3 Fragmentation
• Fragmentation can either be external fragmentation or internal
fragmentation.
• External fragmentation is when the free memory blocks available
in memory are too small and even non-contiguous
• Internal fragmentation occurs when the process does not fully
utilize the memory allocated to it.
• The solution to the problem of external fragmentation is memory
compaction.
• Here, all the memory contents are shuffled to the one area of
memory thereby creating a large block of memory which can be
allocated to one or more new processes.
• In the below figure, the last process C, B, D are moved downwards
to make a large hole.
Fragmentation (Cont.)
 Fragmentation

Advantages and Disadvantages

•The main disadvantage of contiguous memory allocation is memory
wastage and inflexibility. As the memory is allocated to a file or a
process keeping in mind that it will grow during the run. But until a
process or a file grows many blocks allocated to it remains unutilized.
And they even they cannot be allocated to the other process leading to
wastage of memory.
•In case, the process or the file grows beyond the expectation i.e.
beyond the allocated memory block, then it will abort with the message
“No disk space” leading to inflexibility.
•The advantage of contiguous memory allocation is it increases the
processing speed. As the operating system uses the buffered I/O and
reads the process memory blocks consecutively it reduces the head
movements. This speed ups the processing.
 8.4 Paging
• Physical address space of a process can be noncontiguous; process is
allocated physical memory whenever the latter is available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
• Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
• Divide logical memory into blocks of same size called pages
• Keep track of all free frames
• To run a program of size N pages, need to find N free frames and load
program
• Set up a page table to translate logical to physical addresses
• Backing store likewise split into pages
• Still have Internal fragmentation
• Paging is a memory-management scheme that permits the physical
address space of a process to be noncontiguous.
• If there are noncontiguous program size then we combine those
noncontiguous holes into single hole by using compaction technique
and then perform the allocation.
• We know that compaction is a time consuming process, to overcome
this, paging concept is introduced.
• In paging, memory allocation is done without actually combining
them i.e., the program is stored in the memory noncontiguously.
• The problem arises because, when some code fragments or data
residing in main memory need to be swapped out, space must be
found on the backing store.
• The backing store also has the fragmentation problems discussed in
connection with main memory ,except that access is much slower , so
compaction is impossible.
• 8.4.1 Basic Method

• The main idea behind the paging is to divide each process in the form
of pages. The main memory will also be divided in the form of
frames.
• One page of the process is to be stored in one of the frames of the
memory. The pages can be stored at the different locations of the
memory but the priority is always to find the contiguous frames or
holes.
• Pages of the process are brought into the main memory only when
they are required otherwise they reside in the secondary storage.
• Different operating system defines different frame sizes. The sizes of
each frame must be equal.
• Considering the fact that the pages are mapped to the frames in
Paging, page size needs to be as same as frame size.
• Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
• Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

• For given logical address space 2m and page size 2n

Paging Hardware
Paging Model of Logical and Physical Memory
 Paging Example

n=2 and m=4 32-byte memory and 4-byte pages

 Paging (Cont.)

• Let us consider the main memory size 16 Kb and Frame size is 1 KB

therefore the main memory will be divided into the collection of 16 frames
of 1 KB each.
• There are 4 processes in the system that is P1, P2, P3 and P4 of 4 KB each.
Each process is divided into pages of 1 KB each so that one page can be
stored in one frame.
• Initially, all the frames are empty therefore pages of the processes will get
stored in the contiguous way.
• Frames, pages and the mapping between the two is shown in the image
below.
Paging (Cont.)
 Paging (Cont.)

● Let us consider that, P2 and P4 are moved to waiting state after some time.
Now, 8 frames become empty and therefore other pages can be loaded in
that empty place. The process P5 of size 8 KB (8 pages) is waiting inside
the ready queue.
● Given the fact that, we have 8 non contiguous frames available in the
memory and paging provides the flexibility of storing the process at the
different places. Therefore, we can load the pages of process P5 in the place
of P2 and P4.
Paging (Cont.)
 Free Frames

Before After
allocation allocation
 8.4.2 Hardware Support

• Implementation of Page Table

• Page table is kept in main memory

• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the
page table
• In this scheme every data/instruction access requires two
memory accesses
• One for the page table and one for the data / instruction
• The two memory access problem can be solved by the use of
a special fast-lookup hardware cache called associative
memory or translation look-aside buffers (TLBs)
 Implementation of Page Table (Cont.)

• Some TLBs store address-space identifiers (ASIDs) in each

TLB entry – uniquely identifies each process to provide
address-space protection for that process
• Otherwise need to flush at every context switch
• TLBs typically small (64 to 1,024 entries)
• On a TLB miss, value is loaded into the TLB for faster access
next time
• Replacement policies must be considered
• Some entries can be wired down for permanent fast
access
 Associative Memory

● Associative memory – parallel search

● Address translation (p, d)

● If p is in associative register, get frame # out
● Otherwise get frame # from page table in memory
Paging Hardware With TLB
 Effective Access Time
• Associative Lookup = ε time unit
• Can be < 10% of memory access time
• Hit ratio = α
• Hit ratio – percentage of times that a page number is found in the
associative registers; ratio related to number of associative registers
• Consider α = 80%, ε = 20ns for TLB search, 100ns for memory access
• Effective Access Time (EAT)
• EAT = (1 + ε) α + (2 + ε)(1 – α)
• =2+ε–α
• Consider α = 80%, ε = 20ns for TLB search, 100ns for memory access
• EAT = 0.80 x 100 + 0.20 x 200 = 120ns
• Consider more realistic hit ratio -> α = 99%, ε = 20ns for TLB search, 100ns
for memory access
• EAT = 0.99 x 100 + 0.01 x 200 = 101ns
 8.4.3 Memory Protection
• Memory protection implemented by associating protection bit
with each frame to indicate if read-only or read-write access is
allowed
• Can also add more bits to indicate page execute-only, and
so on
• Valid-invalid bit attached to each entry in the page table:
• “valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
• “invalid” indicates that the page is not in the process’
logical address space
• Or use page-table length register (PTLR)
• Any violations result in a trap to the kernel
Valid (v) or Invalid (i) Bit In A Page Table
 8.4.4 Shared Pages
• Shared code
• One copy of read-only (reentrant) code shared among
processes (i.e., text editors, compilers, window systems)
• Similar to multiple threads sharing the same process space
• Also useful for interprocess communication if sharing of
read-write pages is allowed
• Private code and data
• Each process keeps a separate copy of the code and data
• The pages for the private code and data can appear
anywhere in the logical address space
Shared Pages Example
 8.5 Structure of the Page Table
• Memory structures for paging can get huge using straight-forward
methods
• Consider a 32-bit logical address space as on modern computers
• Page size of 4 KB (212)
• Page table would have 1 million entries (2 32 / 212)
• If each entry is 4 bytes -> 4 MB of physical address space /
memory for page table alone
• That amount of memory used to cost a lot
• Don’t want to allocate that contiguously in main memory
• Hierarchical Paging
• Hashed Page Tables
• Inverted Page Tables
 Hierarchical Page Tables

● Break up the logical address space into

multiple page tables
● A simple technique is a two-level page table
● We then page the page table
Two-Level Page-Table Scheme
 Two-Level Paging Example
• A logical address (on 32-bit machine with 1K page size) is divided into:
• a page number consisting of 22 bits
• a page offset consisting of 10 bits

• Since the page table is paged, the page number is further divided into:
• a 12-bit page number
• a 10-bit page offset

• Thus, a logical address is as follows:

• where p1 is an index into the outer page table, and p2 is the displacement within
the page of the inner page table
• Known as forward-mapped page table
Address-Translation Scheme
 64-bit Logical Address Space

• Even two-level paging scheme not sufficient

• If page size is 4 KB (212)
• Then page table has 252 entries
• If two level scheme, inner page tables could be 2 10 4-byte entries
• Address would look like

• Outer page table has 242 entries or 244 bytes

• One solution is to add a 2nd outer page table
• But in the following example the 2nd outer page table is still 234 bytes in size
• And possibly 4 memory access to get to one physical memory location
Three-level Paging Scheme
 Hashed Page Tables
• Common in address spaces > 32 bits
• The virtual page number is hashed into a page table
• This page table contains a chain of elements hashing to the same
location
• Each element contains (1) the virtual page number (2) the value of the
mapped page frame (3) a pointer to the next element
• Virtual page numbers are compared in this chain searching for a match
• If a match is found, the corresponding physical frame is extracted
• Variation for 64-bit addresses is clustered page tables
• Similar to hashed but each entry refers to several pages (such as 16)
rather than 1
• Especially useful for sparse address spaces (where memory references
are non-contiguous and scattered)
Hashed Page Table
 Inverted Page Table
• Rather than each process having a page table and
keeping track of all possible logical pages, track all
physical pages
• One entry for each real page of memory
• Entry consists of the virtual address of the page stored
in that real memory location, with information about the
process that owns that page
• Decreases memory needed to store each page table, but
increases time needed to search the table when a page
reference occurs
• Use hash table to limit the search to one — or at most a
few — page-table entries
• TLB can accelerate access
• But how to implement shared memory?
• One mapping of a virtual address to the shared
physical address
Inverted Page Table Architecture
 8.6 Segmentation

● Memory-management scheme that supports user view of memory

● A program is a collection of segments. A segment is a logical unit
such as:
main program,
procedure,
function,
method,
object,
local variables, global variables,
common block,
stack,
symbol table, arrays
User’s View of a Program
Logical View of Segmentation
● Logical address consists of a two tuple:
<segment-number, offset>,
● Segment table – maps two-dimensional physical addresses; each
table entry has:
● base – contains the starting physical address where the
segments reside in memory
● limit – specifies the length of the segment
● Segment-table base register (STBR) points to the segment
table’s location in memory
● Segment-table length register (STLR) indicates number of
segments used by a program;
segment number s is legal if s < STLR
● Protection
● With each entry in segment table associate:
4 validation bit = 0 ⇒ illegal segment
4 read/write/execute privileges
● Protection bits associated with segments; code sharing occurs at
segment level
● Since segments vary in length, memory allocation is a dynamic
storage-allocation problem
● A segmentation example is shown in the following diagram
Segmentation Hardware
Example of Segmentation
Segmentation with Paging:
•The disadvantage with segmentation was external segmentation and in addition to
that searching for the allocation of a segment using any of the algorithm such as
first fit or best fit etc., would take more time.
•Hence wastage of memory due to external fragmentation and wastage of time are
the disadvantage or drawbacks with segmentation.
•To overcome, this we use a technique called as segmentation with paging.
•In segmentation with paging we page the segments.
•Paging eliminates external fragmentation here any empty frame can be used for a
desired page.
•CPU generates a logical address which consists of segment number ‘s’ and
displacement ‘d’.
•This segment limit or segment length is compared with displacement, if segment
length is not greater than displacement then a trap is send to OS.
•Other wise the displacement is divided into two parts page number(p)and
displacement(d) and segment table is divided into two parts segment length and
page table base.
 Chp-9 Virtual Memory
● Background
● Demand Paging(9.2 as per textbook)
● Page Replacement(9.4 as per textbook)
● Thrashing(9.6 as per textbook)
● Virtual memory – separation of user logical memory from
physical memory.
● Only part of the program needs to be in memory for execution
● Logical address space can therefore be much larger than
physical address space
● Allows address spaces to be shared by several processes
● Allows for more efficient process creation

● Virtual memory can be implemented via:

● Demand paging
● Demand segmentation
 9.2 Demand Paging
● Bring a page into memory only when it is needed
● Less I/O needed
● Less memory needed
● Faster response
● More users

● Page is needed ⇒ reference to it

● invalid reference ⇒ abort
● not-in-memory ⇒ bring to memory
● Lazy swapper – never swaps a page into memory unless page
will be needed
● Swapper that deals with pages is a pager
Transfer of a Paged Memory to Contiguous
Disk Space
 9.2.1 Valid-Invalid Bit
● With each page table entry a valid–invalid bit is associated
v ⇒ in-memory, i ⇒ not-in-memory)
● Initially valid–invalid bit is set to i on all entries
● Example of a page table snapshot:

● During address translation, if valid–invalid bit in page table entry

is I ⇒ page fault
Page Table When Some Pages Are Not in Main
Memory
 Page Fault
● If there is a reference to a page, first reference to that page will
trap to operating system:
page fault
1. Operating system looks at another table to decide:
● Invalid reference ⇒ abort
● Just not in memory
2. Get empty frame
3. Swap page into frame
4. Reset tables
5. Set validation bit = v
6. Restart the instruction that caused the page fault
● Restart instruction
● block move

● auto increment/decrement location

Steps in Handling a Page Fault
 9.4 What happens if there is no free
frame?

● Page replacement – find some page in memory, but not really in

use, swap it out
● algorithm
● performance – want an algorithm which will result in minimum
number of page faults
● Same page may be brought into memory several times
● Prevent over-allocation of memory by modifying page-fault service
routine to include page replacement

● Use modify (dirty) bit to reduce overhead of page transfers –

only modified pages are written to disk

● Page replacement completes separation between logical memory

and physical memory – large virtual memory can be provided on a
smaller physical memory
Need For Page Replacement
 Basic Page Replacement
1. Find the location of the desired page on disk

2. Find a free frame:

- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm
to select a victim frame

3. Bring the desired page into the (newly) free frame; update the
page and frame tables

4. Restart the process

Page Replacement
 Page Replacement Algorithms
● Want lowest page-fault rate

● Evaluate algorithm by running it on a particular string of memory

references (reference string) and computing the number of page
faults on that string

● In all our examples, the reference string is

1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
Graph of Page Faults Versus The Number of
Frames
 First-In-First-Out (FIFO) Algorithm

● Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
● 3 frames (3 pages can be in memory at a time per process)
FIFO Page Replacement
 Optimal Algorithm
● Replace page that will not be used for longest period of time
● 4 frames example
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

● How do you know this?

● Used for measuring how well your algorithm performs
Optimal Page Replacement
 Least Recently Used (LRU) Algorithm

● Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

● Counter implementation
● Every page entry has a counter; every time page is referenced
through this entry, copy the clock into the counter
● When a page needs to be changed, look at the counters to
determine which are to change
LRU Page Replacement
 Counting Algorithms

● Keep a counter of the number of references that have been made to

each page

● LFU Algorithm: replaces page with smallest count

● MFU Algorithm: based on the argument that the page with the
smallest count was probably just brought in and has yet to be used
 9.6 Thrashing

If a process does not have “enough” pages, the page-fault rate is

very high. This leads to:
● low CPU utilization
● operating system thinks that it needs to increase the degree of
multiprogramming
● another process added to the system

Thrashing ≡ a process is busy swapping pages in and out