Unit 3 Interrupt Sources
Unit 3 Interrupt Sources
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Sr No. Maskable Interrupt Non Maskable Interrupt
Maskable interrupt is a hardware Interrupt A non-maskable interrupt is a hardware interrupt
1 that can be disabled or ignored by the that cannot be disabled or ignored by the
instructions of CPU. instructions of CPU.
When maskable interrupt occur, it can be When non-maskable interrupts occur, the current
2 handled after executing the current instructions and status are stored in stack for the
instruction. CPU to handle the interrupt.
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Maskable interrupts help to handle lower Non-maskable interrupt help to handle higher
priority tasks. priority tasks such as watchdog timer.
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Maskable interrupts used to interface with Non maskable interrupt used for emergency
peripheral device. purpose e.g power failure, smoke detector etc .
5 In maskable interrupts, response time is high. In non maskable interrupts, response time is low.
7 Operation can be masked or made pending. Operation Cannot be masked or made pending.
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RST6.5, RST7.5, and RST5.5 of 8085 are some Trap of 8085 microprocessor is an example for non-
common examples of maskable Interrupts.
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maskable interrupt. 2
Hardware Sources of interrupts
• Hardware device sources of interrupts
• Hardware sources can be internal or external for interrupt of ongoing routine and thereby
diversion to corresponding ISR.
• The internal sources from devices differ in different processor or microcontroller or device and
their versions and families
• External sources and ports also differ in different processors or micro controllers
• Each of the interrupt sources (or groups of interrupt sources) demands a temporary transfer
of control from the presently executed routine to the ISR corresponding to the source (when a
source not masked)
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Internal Hardware Device Sources
1 Parallel Port
2. UART Serial Receiver Port -[Noise, Over run, Frame-Error, IDLE, RDRF in 68HC11]
3. Synchronous Receiver byte Completion
4. UART Serial Transmit Port-Transmission Complete, [For example, TDRE (transmitter data
register Empty]
5. Synchronous Transmission of byte completed
6. ADC Start of Conversion
7.ADC End of Conversion
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Internal Hardware Device Sources Cont.…
8. Pulse-Accumulator overflow
9. Real Time Clock time-outs
10. Watchdog Timer Reset
11. Timer Overflow on time-out
12. Timer comparison with Output compare Registers
13. Timer capture on inputs
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THANK YOU
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