Unit 1
Unit 1
1
UNIT 1
Microprocessor Architecture:
Introduction to Microprocessors, Architecture of
8085, Pin Configuration and Function; internal register & flag
register, Generation of Control Signals: Bus Timings:
Demultiplexing of address / data bus; Fetch Cycle, Execute
Cycle, Instruction Cycle, Instruction Timings and Operation
Status, Timing Diagram.
MICROPROCESSOR 2
UNIT 2
Instruction Set and Programming with 8085:
Instruction for Data Transfer. Arithmetic and Logical Operations.
Branching Operation: Machine Cycle Concept; Addressing Modes;
Instructions Format: Stacks. Subroutine and Related Instructions.
Elementary Concepts of Assemblers, Assembler Directives, Looping
and Counting: Software Counters with Time Delays: Simple
Programs using Instruction Set of 8085: Debugging: Programs
Involving Subroutines. Programs for Code Conversion e.g. BCD to
Binary, Binary to BCD. Binary to Seven-Segment LED Display. Binary
to ASCII. ASCII to Binary: Program for Addition Subtraction:
Programs for Multiplication and Division of Unsigned Binary
Numbers.
MICROPROCESSOR 3
UNIT 3
MICROPROCESSOR 4
UNIT 4
Interrupts:
Restart Instruction; Hardware Implementation: Interrupt
Processing; Multiple Interrupts and Priority Concepts: Interrupt
Structure of 8085: Instructions related to interrupts: Pending
Interrupts: Use of Interrupt and Handshaking Signals in Interfacing:
Application of Interrupts and Illustrative Programs.
MICROPROCESSOR 5
UNIT 5
MICROPROCESSOR 6
Microprocessor Architecture
• The microprocessor can be programmed to
perform functions on given data by writing
specific instructions into its memory.
– The microprocessor reads one instruction at a
time, matches it with its instruction set, and
performs the data manipulation specified.
– The result is either stored back into memory or
displayed on an output device.
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The 8085 Architecture
• The 8085 uses three separate busses to
perform its operations
– The address bus.
– The data bus.
– The control bus.
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The Address Bus
– 16 bits wide (A0 A1…A15)
• Therefore, the 8085 can access locations with numbers from 0
to 65,536. Or, the 8085 can access a total of 64K addresses.
– “Unidirectional”.
• Information flows out of the microprocessor and into the
memory or peripherals.
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The Data Bus
– 8 bits wide (D0 D1…D7)
– “Bi-directional”.
• Information flows both ways between the
microprocessor and memory or I/O.
– Since the data bus has 8-bits only, then the 8085
can manipulate data 8 bits at-a-time only.
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The Control Bus
– There is no real control bus. Instead, the control
bus is made up of a number of single bit control
signals.
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Example: Instruction Fetch Operation
The 8085 Bus Structure
The 8-bit 8085 CPU (or MPU – Micro Processing Unit) communicates with the other units using a
16-bit address bus, an 8-bit data bus and a control bus.
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8085 Functional Block Diagram
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The 8085 Microprocessor
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8085 Notes
• The 8085 microprocessor has 2
differentiators
The low order address bus of 8085
is multiplexed with the data bus.
The bus need to be Demultiplexed
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8085 Notes
• All signals can be classified in to 6 groups:
Address bus
Data bus
Control and Status signals
Power supply & Frequency signals
Externally initiated signals
Serial I/O ports
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8085 Notes
• Multiplexed Address/Data bus
The signal lines AD7 – AD0 are bidirectional, they are used as low
order address bus as well as the data bus
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8085 Notes
• Control & Status signals
ALE - This positive pulse is generated every time the 8085 begins an operation. It
indicates that the bits on AD7 – AD0 are address bits. This signal latches the low order
address from the multiplexed bus and generates a separate set of eight address lines
A7 – A0.
RD - This is active low control signal, this signal indicates a “read” data from I/O or
memory
WR - This is active low control signal, this signal indicate that the data on the data bus
will be written onto the I/O or memory
IO/M - This status signal is used to differentiate between the IO and memory. When it
is high IO will be selected. If low, then memory is selected. This signal is combined
with RD & WR for read or write operation
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8085 Notes
• Power supply and Clock frequency:-
Vcc = + 5v
Vss = Ground/Gnd/0 Volts
• X1, X2: with RC/LC network to operate
system - 3MHz to 6MHz
• CLK - Clock output, used as system clock for
other devices
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8085 Notes - Externally initiated Signals
including Interrupts
• INTR (input) - INTerrupt Request, used as a general purpose
interrupt.
• RST 7.5, RST 6.5, RST 5.5 (inputs) - ReSTart interrupts - have higher
priorities than the INTR interrupt
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8085 Notes – other signals
• HLDA (output) - HoLD Acknowledge - signal to acknowledge the
assertion of HOLD signal
• RESET IN - When this signal goes low, the PC is set to zero, the buses
are tri-stated & mP is reset
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8085 Bus Architecture
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8085 programmable Registers
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Another View of the 8085 System Bus
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Memory Read Operation
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Demultiplexing the Bus AD7 – AD0
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Timing :Transfer of byte from memory to MPU
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Data Flow from Memory to the mP
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Cycles and States
Instruction
(opcode)
reaches the
instruction
decoder now !
It takes four
clock cycles
to get one
instruction
into the CPU.
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Execution of an Instruction
Now consider the execution of a simple instruction:
Two-byte instruction !
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Execution of an Instruction
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Execution of an Instruction
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Execution of an Instruction
Get the
instruction
(opcode)
byte from
memory
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Execution of an Instruction
Interpret the
instruction:
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Execution of an Instruction
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Execution of an Instruction
Put into
accumulator
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Basic DMA Operation
02/25/2025 39
DMA
device device
CPU CPU
memory memory
02/25/2025 EIE311-CSF-int-dma 40
DMA (cont.)
• The direct memory access (DMA) I/O technique
provides direct access to the memory while the
microprocessor is temporarily disabled.
• A DMA controller temporarily
– borrows the address bus, data bus, and control bus from the
microprocessor and
– transfers the data bytes directly between an I/O port and a
series of memory locations.
• The DMA transfer is also used to do high-speed
memory-to-memory transfers.
02/25/2025 EIE311-CSF-int-dma 41
DMA (cont.)
• Two control signals are used to request and
acknowledge a DMA transfer in the microprocessor-
based system.
• The HOLD signal is a bus request signal which asks the
microprocessor to release control of the buses after
the current bus cycle.
• The HLDA signal is a bus grant signal which indicates
that the microprocessor has indeed released control of
its buses by placing the buses at their high-impedance
states.
• The HOLD input has a higher priority than the INTR or
NMI interrupt inputs.
02/25/2025 EIE311-CSF-int-dma 42
When DMA does not operate
02/25/2025 EIE311-CSF-int-dma 43
When DMA does not operate
02/25/2025 EIE311-CSF-int-dma 44
When DMA operates
02/25/2025 EIE311-CSF-int-dma 45
Example: memory-to-device transfer
02/25/2025 EIE311-CSF-int-dma 46
8237A DMA Block Diagram
1
PC 2003
FFFB
FFFC
FFFD 03
FFFE 20
FFFF SP
The CALL Instruction 16
PC 2003
FFFB
4014 FFFC
4015 RET FFFD 03 SP
FFFE 20
FFFF
The Stack 3
PUSH B
PUSH D
POP D
POP B
A Flag
12 80
FFFB
FFFC
FFFD 80 SP
FFFE 12
FFFF
Interrupts
• Interrupt is a process where an external device can get
the attention of the microprocessor.
– The process starts from the I/O device
– The process is asynchronous.
• Classification of Interrupts
– Interrupts can be classified into two types:
• Maskable Interrupts (Can be delayed or Rejected)
• Non-Maskable Interrupts (Can not be delayed or Rejected)
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Interrupts
• An interrupt is considered to be an emergency signal
that may be serviced.
– The Microprocessor may respond to it as soon as possible.
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Responding to Interrupts
• Responding to an interrupt may be immediate or
delayed depending on whether the interrupt is
maskable or non-maskable and whether interrupts are
being masked or not.
• There are two ways of redirecting the execution to the
ISR depending on whether the interrupt is vectored or
non-vectored.
– Vectored: The address of the subroutine is already known
to the Microprocessor
– Non Vectored: The device will have to supply the address of
the subroutine to the Microprocessor
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The 8085 Interrupts
• When a device interrupts, it actually wants the
MP to give a service which is equivalent to asking
the MP to call a subroutine. This subroutine is
called ISR (Interrupt Service Routine)
• The ‘EI’ instruction is a one byte instruction and is
used to Enable the non-maskable interrupts.
• The ‘DI’ instruction is a one byte instruction and
is used to Disable the non-maskable interrupts.
• The 8085 has a single Non-Maskable interrupt.
– The non-maskable interrupt is not affected by the
value of the Interrupt Enable flip flop.
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The 8085 Interrupts
• The 8085 has 5 interrupt inputs.
– The INTR input.
• The INTR input is the only non-vectored interrupt.
• INTR is maskable using the EI/DI instruction pair.
– RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
• RST 5.5, RST 6.5, and RST 7.5 are all maskable.
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The 8085 Interrupts
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8085 Interrupts
TRAP
RST7.5
RST6.5
RST 5.5
8085
INTR
INTA
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The 8085 Non-Vectored Interrupt Process
– The vectors for these interrupt fall in between the vectors for the RST
instructions. That’s why they have names like RST 5.5 (RST 5 and a
half).
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