8086 Architecture

Features of 8086 Microprocessor

• It is a 16-bit µp.
• 8086 has a 20 bit address bus can access up to 220
memory locations (1 MB).
• It can support up to 64K I/O ports.
• It provides 14, 16 -bit registers.
• It has multiplexed address and data bus AD0- AD15 and
A16 – A19.
• It requires single phase clock with 33% duty cycle to
provide internal timing. (5 MHz)
• 8086 is designed to operate in two modes, Minimum and
Maximum.
• It can prefetches upto 6 instruction bytes from memory
and queues them in order to speed up instruction
execution.
• It requires +5V power supply.
• It supports multiprogramming.

Contd..
• It is possible to perform bit, byte, word and block operations in
8086.
• A 40 pin dual in line package Minimum and Maximum Modes

• The minimum mode is selected by applying logic 1 to the MN /

MX input pin. This is a single microprocessor configuration.

• The maximum mode is selected by applying logic 0 to the MN /

MX input pin. This is a multi micro processors configuration.
 Architecture contd..

• There are two functional units

– Bus Interfacing Unit (BIU)
– Execution Unit (EU)
 Bus Interfacing Unit (BIU)

• It sends address of the memory or I/O

• It fetches instruction from memory.
• It reads data from memory and I/O ports.
• It writes data to memory and I/ O ports.
• It supports instruction queuing.
• It provides the address relocation facility.
• It contains Instruction Queue, Segment
registers, instruction pointer, address summer
and bus control logic.
 Instruction Queue
• To increase the execution speed, BIU fetches
as many as six instruction bytes ahead to time
from memory.
• All six bytes are then held in FIFO 6-byte
register called instruction queue.
• Then all bytes are given to EU one by one.
• This pre-fetching operation of BIU may be in
parallel with execution operation of EU, which
improves the execution speed of the instruction.
 Pipelining
• While EU executes instructions, BIU
fetches instructions from memory and
stores them in the QUEUE.
• BIU and EU operate in parallel
independent of each other.
• This type of overlapped operation of the
functional units of a MP is called
Pipelining
 Execution Unit
Execution Unit contains:
• General Purposes Registers
• Stack Pointer
• Base Pointer
• Index Registers
• ALU
• Flag Register
• Instruction Decoder
• Timing & Control Unit
 Functions of EU
• It receives opcode of an instruction from the
QUEUE.
• It decodes it and then executes it.
• It tells BIU where to fetch the instructions or
data from.
• It contains the control circuitry to perform various
internal operations.
• It has 16-bit ALU, which can perform arithmetic
and logical operations on 8-bit as well as 16-bit
data
 Registers
• General Purpose Registers
• Pointer and Index Registers
• Segment Registers
• Instruction Pointer
• Status Flags
 General Purpose Register
• There are four 16-bit general purpose
registers:
–AX
–BX
–CX
–DX
• AX Register: AX register is also known as
accumulator register that stores operands
for arithmetic operation like divided, rotate.
• BX Register: This register is mainly used as
a base register. It holds the starting base
location of a memory region within a data
segment.
• CX Register: It is defined as a counter. It is
primarily used in loop instruction to store
loop counter.
• DX Register: DX register is used as IN and
OUT Instruction to contain I/O port address
for I/O instruction.
 Segment Registers
• A segment register points to the starting address of a
memory segment.
• The maximum capacity of a segment may be up to 64 KB.
• The instructions of 8086 specify 16-bit address.
• But the actual physical addresses are of 20-bit.
• 1 MB Memory can be divided into 16 parts which are called
segments.
There are four segment registers
• Code Segment Register (CS)
• Data Segment Register (DS)
• Stack Segment Register (SS)
• Extra Segment Register (ES)
Code Segment (CS)
• The CS register is used for addressing a
memory location in the Code Segment of the
memory, where the executable program is
stored.
Data Segment (DS)
• The DS contains most data used by program.
Data are accessed in the Data Segment by
an offset address or the content of other
register that holds the offset address.
Stack Segment (SS)
SS defined the area of memory used for the
stack.
Extra Segment (ES)
ES is additional data segment that is used by
some of the string to hold the destination
data.
 Pointer & Index Registers
• Stack Pointer (SP)
• Base Pointer (BP)
• Source Index (SI)
• Destination Index (DI)
Stack Pointer (SP)
• The function of SP is same as the function of SP
in Intel 8085.
• It stores the address of top of element in the stack.
• BP, SI & DI are used in memory address
computation.
 Pointer and Index Register
Stack Pointer (SP)
Hold the offset address of the data stored at top
of the stack segment, It is used along with SS to
decide the address at which the data is pushed
or popped during the execution of Instruction.

Base Pointer (BP)

It is used to hold the offset address of the data to
be read from or written into the stack
segment.
Source Index(SI)
It is used to hold the offset address of the
source data in the data segment, while
executing string instruction.
Destination Index(DI)
It is used to hold the offset address of the
destination data in the extra segment, while
executing string instruction.
 Instruction Pointer
• The Instruction Pointer (IP) acts as a Program
Counter.
• It points to the address of the next
instruction to be executed.
• Its content is automatically incremented
when the execution of a program proceeds
further.
• The contents of the IP and Code Segment
Register are used to compute the memory
address of the instruction code to be fetched.
• This is done during the Fetch Cycle.
 Status Register
• 16-bit status register.
• It is also called Flag Register or Program
Status Word (PSW).
• There are nine status flags and seven bit
positions remain unused.
9 flags and they are divided into two categories
• Condition Flags
• Control Flags
 Auxiliary Carry Flag
This flag can be used for internally for Carry Flag
Flag Register BCD Operation. User cannot change
This flag is set, when there is
the sequence. We use Jump
instruction. a carry out of MSB in case of
This is set, if there is a carry from the addition or a borrow in case of
lowest nibble, subtraction.
Sign Flag
Zero Flag Parity Flag
If set 1, when the result of This flag is set to 1, if the lower
any computation is This flag is set, if the result of byte of the result contains even
negative the computation or comparison number of 1’s ;
If set 0: indicates positive performed by an instruction is If flag is set to 0, for odd number
number. zero of 1’s .

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Tarp Flag
Over flow Flag One way to debug a program is to run program
This flag is set, if an overflow occurs, i.e, if the result of a signed one instruction at a time used for register and
operation is large enough to accommodate in a destination memory variables.
register. The result is of more than 7-bits in size in case of 8-bit If this flag is set, the processor enters the single
signed operation and more than 15-bits in size in case of 16-bit step execution mode by generating internal
sign operations, then the overflow will be set. interrupts after the execution of each instruction

Direction Flag
Interrupt Flag
This is used by string manipulation instructions. If DF bit is ‘0’,
It is used to allow/prohibit the
the string is processed beginning from the lowest address
to the highest address, i.e., auto incrementing mode. interruption of a program.
If DF=1 the string is processed from the highest address If set: interrupt can be recognized
towards the lowest address, i.e., auto Decrementing mode. If 0 : interrupt disabled25
 Control Flags
Trap Flag (TP)
 It is used for single step control.
 It allows user to execute one instruction of a program at a time for debugging.
 When trap flag is set, program can be run in single step mode.

Interrupt Flag (IF)

 It is an interrupt enable/disable flag.
 If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is disabled.
 It can be set by executing instruction set and can be cleared by executing CLI
instruction.

Direction Flag (DF)

 It is used in string operation.
 If it is set, string bytes are accessed from higher memory address to lower
memory address.
 When it is reset, the string bytes are accessed from lower memory address to
higher memory address.
Pins and signals
of 8086
 8086
Common signals
Microprocessor

AD0-AD15 (Bidirectional)

Address/Data bus
Low order address bus; these are multiplexed
with data.

When AD lines are used to transmit memory

address the symbol A is used instead of AD,
for example A0-A15.

When data are transmitted over AD lines the

symbol D is used in place of AD, for example
D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are multiplexed

with status signals.
ALE =1 pin carry Address ALE-0 Carry status
S4 S3 Segment
Accessed
0 0 ES
0 1 SS
1 0 CS 28
1 1 DS
 8086
Common signals
Microprocessor

BHE (Active Low)/S7 (Output)

Bus High Enable/Status

* It is used to enable most significant data

bus, D8-D15 during read/write operation.
* It is multiplexed with status signal S7 is
always logic 1

MN/ MX
MINIMUM / MAXIMUM
This pin signal indicates what mode the
processor is to operate in.
MN/MX is 5V (Minimum Mode)
MN/MX is GND (Maximum Mode)

RD (Read) (Active Low)

The signal is used for read data from memory

or I/O device through data bus.

29
 8086
Common signals
Microprocessor

TEST

•It is a input pin tested by WAIT instruction.

•If Logic 0 it become No Operation
•If Logic 1 it will WAIT instruction wait for
TEST become logic 0.
•This offen used for floating point operations

READY
* The signal is active high.
•If Logic 1 No operation in
Microprocessor.
•If Logic 0 8086 enter WAIT states and
remain idle.
•It is used to interface slow operating
peripherals.

30
 8086
Common signals
Microprocessor

RESET (Input)
The signal must be active HIGH for at
least four clock cycles.
Causes the processor to immediately
terminate its present activity.
CS & IP are initialized to 0000H and
FFFFH.

CLK
*The clock input provides the basic timing for
processor operation and bus control activity.
•Its an 33% duty cycle .
•It Max Frequency 5 MHz

INTR Interrupt Request

•This signal is active high and internally
synchronized.
•IF=1 if INTR is held high (logic 1)
•IF=0 if INTR is disabled. (logic 0)

NMI (Non Maskable Interrupt)

It is an hardware interrupt. It cannot be
disabled by software. 31
 8086
Microprocessor
Min/ Max Pins

The 8086 microprocessor can work in two

modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

32
 8086
Minimum mode signals
Microprocessor

DT/R (Data Transmit/Receive) Used to indicate Transmitting data.

DT/R =1 Transmit Data , DT/R=0 Receive Data

DEN (Data Enable) Used to indicate Data bus signal.

DEN =1 Transmit Data through data bus,
DEN=0 No Data in Data Bus

ALE (Address Latch Enable) Used to demultiplex the address

and data lines using external latches

M/IO (Memory read/write operation)

M/IO=1 indicate Memory read/write operation.
M/IO =0 indicate I/O read/write operation.

33
 8086
Minimum mode signals
Microprocessor

HOLD Input signal to the processor form the bus masters as a request
to grant the control of the bus.
Logic =1 complete the execution of current instruction and place
it Address, Data and Control bus in High impedance state.
Logic==0 Execute instruction Normally.

HLDA (Hold Acknowledge) Acknowledge signal by the processor

to the bus master requesting the control of the bus through
HOLD.

The acknowledge is asserted high, when the processor

accepts HOLD.

34
 8086
Maximum mode signals
Microprocessor

35
 8086
Maximum mode signals
Microprocessor

36
 8086
Maximum mode signals
Microprocessor

37
Memory Segmentation
Rules for Memory Segmentation
• The four segments can overlap for small
programs. In a Minimum System all four
segments can start at the address 00000H
• The segment can begin/start at any
memory address which is divisible by 16.
 20 bit Physical Address
• To access a specific memory location from
any segment we need 20 bit physical
address.
 Access Memory Location
Each address in physical memory(ROM/EPROM)
is called physical address.

Segment Register Default Offset Register

CS IP
DS BX,SI,DI 8 or 16 bit displacement.
SS SP,BP
ES DI for string operation
 Generation of Physical Address
MOV AL,[BP]
SS : 3000H 3000x10=30000H
BP : 0010 H 0010H
Physical Address: 30010H
MOV CX,[BX]
MOV AL,[BP+SI]
MOV AX,[SP]
ADDRESSING
MODES
 8086
Microprocessor Addressing Modes
Every instruction of a program has to operate on a data.
The different ways in which a source operand is denoted
in an instruction are known as addressing modes.

1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing

8. String Addressing

9. Direct I/O port Addressing

Group III : Addressing modes for
10. Indirect I/O port Addressing I/O ports

11. Relative Addressing Group IV : Relative Addressing mode

12. Implied Addressing Group V : Implied Addressing mode

44
 8086 Group I : Addressing modes for
Microprocessor register and immediate data

1. Register Addressing The instruction will specify the name of the

register which holds the data to be operated by
2. Immediate Addressing the instruction.
3. Direct Addressing Example:
4. Register Indirect Addressing
MOV CL, DH
5. Based Addressing
The content of 8-bit register DH is moved to
6. Indexed Addressing another 8-bit register CL

7. Based Index Addressing (CL)  (DH)

8. String Addressing

9. Direct I/O port Addressing

10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

45
 8086 Group I : Addressing modes for
Microprocessor register and immediate data

1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL

7. Based Index Addressing (DL)  08H

8. String Addressing

9. Direct I/O port Addressing

MOV AX, 0A9FH

10. Indirect I/O port Addressing The 16-bit data (0A9FH) given in the instruction is
moved to AX register
11. Relative Addressing
(AX)  0A9FH
12. Implied Addressing

46
 8086
Microprocessor Addressing Modes : Memory Access

20 Address lines  8086 can address up to 2 20 =

1M bytes of memory

However, the largest register is only 16 bits

Physical Address will have to be calculated Physical

Address : Actual address of a byte in memory. i.e. the
value which goes out onto the address bus.

Memory Address represented in the form – Seg :

Offset (Eg - 89AB:F012)

Each time the processor wants to access memory, it

takes the contents of a segment register, shifts it one
hexadecimal place to the left (same as multiplying by
1610), then add the required offset to form the 20- bit
16 bytes of contiguous
address memory

89AB : F012  89AB  89AB0 (Paragraph to byte  89AB x 10 = 89AB0)

F012  0F012 (Offset is already in byte unit)
+ -------
98AC2 (The absolute address)
48
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing

2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.

5. Based Addressing The effective address is just a 16-bit number

written directly in the instruction.
6. Indexed Addressing
Example:
7. Based Index Addressing
MOV BX, [1354H]
8. String Addressing MOV BL, [0400H]
9. Direct I/O port Addressing
The square brackets around the 1354H denotes
10. Indirect I/O port Addressing the contents of the memory location. When
executed, this instruction will copy the contents
11. Relative Addressing of the memory location into BX register.

12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.

50
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing In Register indirect addressing, name of the

register which holds the effective address (EA)
2. Immediate Addressing will be specified in the instruction.

3. Direct Addressing Registers used to hold EA are any of the following

registers:
4. Register Indirect Addressing
BX, BP, DI and SI.
5. Based Addressing
Content of the DS register is used for base
6. Indexed Addressing
address calculation.
7. Based Index Addressing
Example:
8. String Addressing Note : Register/ memory
MOV CX, [BX] enclosed in brackets refer to
9. Direct I/O port Addressing content of register/ memory
Operations:
10. Indirect I/O port Addressing
EA = (BX)
11. Relative Addressing BA = (DS) x 1610
MA = BA + EA
12. Implied Addressing
(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA +1)
51
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing In Based Addressing, BX or BP is used to hold the

base value for effective address and a signed 8-
2. Immediate Addressing bit or unsigned 16-bit displacement will be
specified in the instruction.
3. Direct Addressing
In case of 8-bit displacement, it is sign extended
4. Register Indirect Addressing to 16-bit before adding to the base value.

5. Based Addressing When BX holds the base value of EA, 20-bit

physical address is calculated from BX and DS.
6. Indexed Addressing
When BP holds the base value of EA, BP and SS is
7. Based Index Addressing
used.
8. String Addressing
Example:
9. Direct I/O port Addressing
MOV AX, [BX + 08H]
10. Indirect I/O port Addressing
Operations:
11. Relative Addressing
0008H  08H (Sign extended)
12. Implied Addressing EA = (BX) + 0008H
BA = (DS) x 1610
MA = BA + EA

(AX)  (MA) or,

(AL)  (MA) 52
(AH)  (MA + 1)
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing SI or DI register is used to hold an index value for

memory data and a signed 8-bit or unsigned 16-
2. Immediate Addressing bit displacement will be specified in the
instruction.
3. Direct Addressing
Displacement is added to the index value in SI or
4. Register Indirect Addressing DI register to obtain the EA.

5. Based Addressing In case of 8-bit displacement, it is sign extended

to 16-bit before adding to the base value.
6. Indexed Addressing

7. Based Index Addressing

Example:
8. String Addressing
MOV CX, [SI + 0A2H]
9. Direct I/O port Addressing
Operations:
10. Indirect I/O port Addressing
FFA2H  A2H (Sign extended)
11. Relative Addressing
EA = (SI) + FFA2H
12. Implied Addressing BA = (DS) x 1610
MA = BA + EA

(CX)  (MA) or,

(CL)  (MA)
(CH)  (MA + 1)
53
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing In Based Index Addressing, the effective address

is computed from the sum of a base register (BX
2. Immediate Addressing or BP), an index register (SI or DI) and a
displacement.
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DX, [BX + SI + 0AH]
5. Based Addressing
Operations:
6. Indexed Addressing
000AH  0AH (Sign extended)
7. Based Index Addressing

8. String Addressing EA = (BX) + (SI) + 000AH

BA = (DS) x 1610
9. Direct I/O port Addressing MA = BA + EA
10. Indirect I/O port Addressing
(DX)  (MA) or,
11. Relative Addressing
(DL)  (MA)
12. Implied Addressing (DH)  (MA + 1)

54
 8086 Group II : Addressing modes
Microprocessor for memory data

1. Register Addressing Employed in string operations to operate on

string data.
2. Immediate Addressing
The effective address (EA) of source data is
3. Direct Addressing stored in SI register and the EA of destination is
stored in DI register.
4. Register Indirect Addressing
Segment register for calculating base address of
5. Based Addressing source data is DS and that of the destination data
is ES
6. Indexed Addressing

7. Based Index Addressing

Example: MOVS BYTE
8. String Addressing
Operations:
9. Direct I/O port Addressing
Calculation of source memory location:
10. Indirect I/O port Addressing EA = (SI) BA = (DS) x 1610 MA = BA + EA

11. Relative Addressing Calculation of destination memory location:

EAE = (DI) BAE = (ES) x 1610 MAE = BAE + EAE
12. Implied Addressing

Note : Effective address of the (MAE)  (MA)

Extra segment register
If DF = 1, then (SI)  (SI) – 1 and (DI) = (DI) - 1
If DF = 0, then (SI)  (SI) +1 and (DI) = (DI) +55 1
 8086 Group III : Addressing
Microprocessor modes for I/O ports

1. Register Addressing These addressing modes are used to access data

from standard I/O mapped devices or ports.
2. Immediate Addressing
In direct port addressing mode, an 8-bit port
3. Direct Addressing address is directly specified in the instruction.

4. Register Indirect Addressing Example: IN AL, [09H]

5. Based Addressing Operations: PORTaddr = 09H

(AL)  (PORT)
6. Indexed Addressing

7. Based Index Addressing Content of port with address 09H is

moved to AL register
8. String Addressing
In indirect port addressing mode, the instruction
9. Direct I/O port Addressing will specify the name of the register which holds
the port address. In 8086, the 16-bit port address
10. Indirect I/O port Addressing is stored in the DX register.
11. Relative Addressing
Example: OUT [DX], AX
12. Implied Addressing
Operations: PORTaddr = (DX)
(PORT)  (AX)

Content of AX is moved to port

whose address is specified by DX
register. 56
 8086 Group IV : Relative
Microprocessor Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing In this addressing mode, the effective address of

a program instruction is specified relative to
4. Register Indirect Addressing Instruction Pointer (IP) by an 8-bit signed
displacement.
5. Based Addressing
Example: JZ 0AH
6. Indexed Addressing
Operations:
7. Based Index Addressing

8. String Addressing 000AH  0AH (sign extend)

9. Direct I/O port Addressing If ZF = 1, then

10. Indirect I/O port Addressing EA = (IP) + 000AH

BA = (CS) x 1610
11. Relative Addressing
MA = BA + EA
12. Implied Addressing
If ZF = 1, then the program control jumps to
new address calculated above.

If ZF = 0, then next instruction of the

program is executed.
57
 8086 Group IV : Implied
Microprocessor Addressing mode

1. Register Addressing

2. Immediate Addressing

3. Direct Addressing

4. Register Indirect Addressing

5. Based Addressing

6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing

11. Relative Addressing

12. Implied Addressing

58
INSTRUCTION SET
 8086
Microprocessor Instruction Set
8086 supports 6 types of instructions.

1. Data Transfer Instructions

2. Arithmetic Instructions

3. Logical Instructions

4. String manipulation Instructions

5. Process Control Instructions

6. Control Transfer Instructions

61
 8086
Microprocessor Instruction Set
1. Data Transfer Instructions

Instructions that are used to transfer data/ address in to

registers, memory locations and I/O ports.

Generally involve two operands: Source operand and

Destination operand of the same size.

Source: Register or a memory location or an immediate data

Destination : Register or a memory location.

The size should be a either a byte or a word.

A 8-bit data can only be moved to 8-bit register/ memory

and a 16-bit data can be moved to 16-bit register/ memory.

62
 8086
Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

MOV reg2/ mem, reg1/ mem

MOV reg2, reg1 (reg2)  (reg1)

MOV mem, reg1 (mem)  (reg1)
MOV reg2, mem (reg2)  (mem)

MOV reg/ mem, data

MOV reg, data (reg)  data

MOV mem, data (mem)  data

XCHG reg2/ mem, reg1

XCHG reg2, reg1 (reg2)  (reg1)

XCHG mem, reg1 (mem)  (reg1)

63
 8086
Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

PUSH reg16/ mem

PUSH reg16 (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (reg16)

PUSH mem (SP)  (SP) – 2

MA S = (SS) x 1610 + SP
(MA S ; MA S + 1)  (mem)

POP reg16/ mem

POP reg16 MA S = (SS) x 1610 + SP

(reg16)  (MA S ; MA S + 1)
(SP)  (SP) + 2

POP mem MA S = (SS) x 1610 + SP

(mem)  (MA S ; MA S + 1)
64
(SP)  (SP) + 2
 8086
Microprocessor Instruction Set
1. Data Transfer Instructions

Mnemonics: MOV, XCHG, PUSH, POP, IN, OUT …

IN A, [DX] OUT [DX], A

IN AL, [DX] PORTaddr = (DX) OUT [DX], AL PORTaddr = (DX)

(AL)  (PORT) (PORT)  (AL)

IN AX, [DX] PORTaddr = (DX) OUT [DX], AX PORTaddr = (DX)

(AX)  (PORT) (PORT)  (AX)

IN A, addr8 OUT addr8, A

IN AL, addr8 (AL)  (addr8) OUT addr8, AL (addr8)  (AL)

IN AX, addr8 (AX)  (addr8) OUT addr8, AX (addr8)  (AX)

65
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADD reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)

ADC reg2, mem (reg2)  (reg2) + (mem)
ADC mem, reg1 (mem)  (mem)+(reg1)

ADD reg/mem, data

ADD reg, data (reg)  (reg)+ data

ADD mem, data (mem)  (mem)+data

ADD A, data

ADD AL, data8 (AL)  (AL) + data8

ADD AX, data16 (AX)  (AX) +data16

66
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

ADC reg2/ mem, reg1/mem

ADC reg2, reg1 (reg2)  (reg1) + (reg2)+CF

ADC reg2, mem (reg2)  (reg2) + (mem)+CF
ADC mem, reg1 (mem)  (mem)+(reg1)+CF

ADC reg/mem, data

ADC reg, data (reg)  (reg)+ data+CF

ADC mem, data (mem)  (mem)+data+CF

ADDC A, data

ADD AL, data8 (AL)  (AL) + data8+CF

ADD AX, data16 (AX)  (AX) +data16+CF

67
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SUB reg2/ mem, reg1/mem

SUB reg2, reg1 (reg2)  (reg1) - (reg2)

SUB reg2, mem (reg2)  (reg2) - (mem)
SUB mem, reg1 (mem)  (mem) - (reg1)

SUB reg/mem, data

SUB reg, data (reg)  (reg) - data

SUB mem, data (mem)  (mem) - data

SUB A, data

SUB AL, data8 (AL)  (AL) - data8

SUB AX, data16 (AX)  (AX) - data16

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 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

SBB reg2/ mem, reg1/mem

SBB reg2, reg1 (reg2)  (reg1) - (reg2) - CF

SBB reg2, mem (reg2)  (reg2) - (mem)- CF
SBB mem, reg1 (mem)  (mem) - (reg1) –CF

SBB reg/mem, data

SBB reg, data (reg)  (reg) – data - CF

SBB mem, data (mem)  (mem) - data - CF

SBB A, data

SBB AL, data8 (AL)  (AL) - data8 - CF

SBB AX, data16 (AX)  (AX) - data16 - CF

69
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

INC reg/ mem

INC reg8 (reg8)  (reg8) + 1

INC reg16 (reg16)  (reg16) + 1

INC mem (mem)  (mem) + 1

DEC reg/ mem

DEC reg8 (reg8)  (reg8) - 1

DEC reg16 (reg16)  (reg16) - 1

DEC mem (mem)  (mem) - 1

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 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

MUL reg/ mem

MUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

MUL mem For byte : (AX)  (AL) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

IMUL reg/ mem

IMUL reg For byte : (AX)  (AL) x (reg8)

For word : (DX)(AX)  (AX) x (reg16)

IMUL mem For byte : (AX)  (AX) x (mem8)

For word : (DX)(AX)  (AX) x (mem16)

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 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

DIV reg/ mem

DIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

DIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

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 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

IDIV reg/ mem

IDIV reg For 16-bit :- 8-bit :

(AL)  (AX) :- (reg8) Quotient
(AH)  (AX) MOD(reg8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (reg16) Quotient
(DX)  (DX)(AX) MOD(reg16) Remainder

IDIV mem For 16-bit :- 8-bit :

(AL)  (AX) :- (mem8) Quotient
(AH)  (AX) MOD(mem8) Remainder

For 32-bit :- 16-bit :

(AX)  (DX)(AX) :- (mem16) Quotient
(DX)  (DX)(AX) MOD(mem16) Remainder

73
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg2/mem, reg1/ mem

CMP reg2, reg1 Modify flags  (reg2) – (reg1)

If (reg2) > (reg1) then CF=0, ZF=0, SF=0

If (reg2) < (reg1) then CF=1, ZF=0, SF=1
If (reg2) = (reg1) then CF=0, ZF=1, SF=0

CMP reg2, mem Modify flags  (reg2) – (mem)

If (reg2) > (mem) then CF=0, ZF=0, SF=0

If (reg2) < (mem) then CF=1, ZF=0, SF=1
If (reg2) = (mem) then CF=0, ZF=1, SF=0

CMP mem, reg1 Modify flags  (mem) – (reg1)

If (mem) > (reg1) then CF=0, ZF=0, SF=0

If (mem) < (reg1) then CF=1, ZF=0, SF=1
If (mem) = (reg1) then CF=0, ZF=1, SF=0

74
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP reg/mem, data

CMP reg, data Modify flags  (reg) – (data)

If (reg) > data then CF=0, ZF=0, SF=0

If (reg) < data then CF=1, ZF=0, SF=1
If (reg) = data then CF=0, ZF=1, SF=0

CMP mem, data Modify flags  (mem) – (mem)

If (mem) > data then CF=0, ZF=0, SF=0

If (mem) < data then CF=1, ZF=0, SF=1
If (mem) = data then CF=0, ZF=1, SF=0

75
 8086
Microprocessor Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…

CMP A, data

CMP AL, data8 Modify flags  (AL) – data8

If (AL) > data8 then CF=0, ZF=0, SF=0

If (AL) < data8 then CF=1, ZF=0, SF=1
If (AL) = data8 then CF=0, ZF=1, SF=0

CMP AX, data16 Modify flags  (AX) – data16

If (AX) > data16 then CF=0, ZF=0, SF=0

If (mem) < data16 then CF=1, ZF=0, SF=1
If (mem) = data16 then CF=0, ZF=1, SF=0

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 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

77
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

78
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

79
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

80
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

81
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

82
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

83
 8086
Microprocessor Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …

84
 8086
Microprocessor Instruction Set
4. String Manipulation Instructions

 String : Sequence of bytes or words

 8086 instruction set includes instruction for string movement, comparison,

scan, load and store.

 REP instruction prefix : used to repeat execution of string instructions

 String instructions end with S or SB or SW.

S represents string, SB string byte and SW string word.

 Offset or effective address of the source operand is stored in SI register

and that of the destination operand is stored in DI register.

 Depending on the status of DF, SI and DI registers are automatically

updated.

 DF = 0  SI and DI are incremented by 1 for byte and 2 for word.

 DF = 1  SI and DI are decremented by 1 for byte and 2 for word.

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 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

REP

REPZ/ REPE While CX  0 and ZF = 1, repeat execution of string

instruction and
(Repeat CMPS or SCAS until ZF = (CX)  (CX) – 1
0)

REPNZ/ REPNE While CX  0 and ZF = 0, repeat execution of string

instruction and
(Repeat CMPS or SCAS until ZF = (CX)  (CX) - 1
1)

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 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

MOVS

MOVSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE)  (MA)

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1

If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

MOVSW MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1)  (MA; MA + 1)

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2

If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
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 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Compare two string byte or string word

CMPS

CMPSB MA = (DS) x 1610 + (SI)

MAE = (ES) x 1610 + (DI)

Modify flags  (MA) - (MAE)

If (MA) > (MAE), then CF = 0; ZF = 0; SF = 0

If (MA) < (MAE), then CF = 1; ZF = 0; SF = 1
CMPSW
If (MA) = (MAE), then CF = 0; ZF = 1; SF = 0

For byte operation

If DF = 0, then (DI)  (DI) + 1; (SI)  (SI) + 1
If DF = 1, then (DI)  (DI) - 1; (SI)  (SI) - 1

For word operation

If DF = 0, then (DI)  (DI) + 2; (SI)  (SI) + 2
If DF = 1, then (DI)  (DI) - 2; (SI)  (SI) - 2
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 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS
Scan (compare) a string byte or word with accumulator
SCAS

SCASB MAE = (ES) x 1610 + (DI)

Modify flags  (AL) - (MAE)

If (AL) > (MAE), then CF = 0; ZF = 0; SF = 0

If (AL) < (MAE), then CF = 1; ZF = 0; SF = 1
If (AL) = (MAE), then CF = 0; ZF = 1; SF = 0

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

SCASW
MAE = (ES) x 1610 + (DI)
Modify flags  (AL) - (MAE)

If (AX) > (MAE ; MAE + 1), then CF = 0; ZF = 0; SF = 0

If (AX) < (MAE ; MAE + 1), then CF = 1; ZF = 0; SF = 1
If (AX) = (MAE ; MAE + 1), then CF = 0; ZF = 1; SF = 0
89
If DF = 0, then (DI)  (DI) + 2
 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Load string byte in to AL or string word in to AX

LODS

LODSB MA = (DS) x 1610 + (SI)

(AL)  (MA)

If DF = 0, then (SI)  (SI) + 1

If DF = 1, then (SI)  (SI) – 1

LODSW MA = (DS) x 1610 + (SI)

(AX)  (MA ; MA + 1)

If DF = 0, then (SI)  (SI) + 2

If DF = 1, then (SI)  (SI) – 2

90
 8086
Microprocessor Instruction Set
4. String Manipulation Instructions
Mnemonics: REP, MOVS, CMPS, SCAS, LODS, STOS

Store byte from AL or word from AX in to string

STOS

STOSB MAE = (ES) x 1610 + (DI)

(MAE)  (AL)

If DF = 0, then (DI)  (DI) + 1

If DF = 1, then (DI)  (DI) – 1

STOSW MAE = (ES) x 1610 + (DI)

(MAE ; MAE + 1 )  (AX)

If DF = 0, then (DI)  (DI) + 2

If DF = 1, then (DI)  (DI) – 2

91
 8086
Microprocessor Instruction Set
5. Processor Control Instructions
Mnemonics Explanation
STC Set CF  1

CLC Clear CF  0

CMC Complement carry CF  CF/

STD Set direction flag DF  1

CLD Clear direction flag DF  0

STI Set interrupt enable flag IF  1

CLI Clear interrupt enable flag IF  0

NOP No operation

HLT Halt after interrupt is set

WAIT Wait for TEST pin active

ESC opcode mem/ reg Used to pass instruction to a coprocessor which

shares the address and data bus with the 8086

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LOCK Lock bus during next instruction
 8086
Microprocessor Instruction Set
6. Control Transfer Instructions

Transfer the control to a specific destination or target instruction

Do not affect flags

 8086 Unconditional transfers

Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine

RET Return from subroutine

JMP reg/ mem/ disp8/ disp16 Unconditional jump

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 8086
Microprocessor Instruction Set
6. Control Transfer Instructions
 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Checks flags

If conditions are true, the program control is

transferred to the new memory location in the same
segment by modifying the content of IP

94
 8086
Microprocessor Instruction Set
6. Control Transfer Instructions
 8086 signed conditional  8086 unsigned conditional
branch instructions branch instructions

Name Alternate name Name Alternate name

JE disp8 JZ disp8 JE disp8 JZ disp8
Jump if equal Jump if result is 0 Jump if equal Jump if result is 0

JNE disp8 JNZ disp8 JNE disp8 JNZ disp8

Jump if not equal Jump if not zero Jump if not equal Jump if not zero
JG disp8 JNLE disp8 JA disp8 JNBE disp8
Jump if greater Jump if not less or Jump if above Jump if not below or
equal equal
JGE disp8 JNL disp8 JAE disp8 JNB disp8
Jump if greater than Jump if not less Jump if above or Jump if not below
or equal equal
JL disp8 JNGE disp8 JB disp8 JNAE disp8
Jump if less than Jump if not greater Jump if below Jump if not above or
than or equal equal
JLE disp8 JNG disp8
Jump if less than or Jump if not greater JBE disp8 JNA disp8
equal Jump if below or Jump if not above
95
equal
 8086
Microprocessor Instruction Set
6. Control Transfer Instructions

 8086 conditional branch instructions affecting individual

flags
Mnemonics Explanation

JC disp8 Jump if CF = 1

JNC disp8 Jump if CF = 0

JP disp8 Jump if PF = 1

JNP disp8 Jump if PF = 0

JO disp8 Jump if OF = 1

JNO disp8 Jump if OF = 0

JS disp8 Jump if SF = 1

JNS disp8 Jump if SF = 0

JZ disp8 Jump if result is zero, i.e, Z = 1

JNZ disp8 Jump if result is not zero, i.e, Z = 1

96