Synchronous and Asynchronous

Data-Transfer
What we have seen in last class-----
 I/O Interface Overview
 Key Components of I/O Interface
 I/O Commands
 Control and Status Register
 Address Decoder
 Buffering Mechanism
 I/O Mapping and its types
 How data transfer?
Synchronous Data Transfer
•Two units involved in data transfer share a common clock.

•Data transfer between the sender and receiver is synchronized with the same clock pulse.

•Synchronous data transfer is typically used between devices that operate at matching speeds.

•Bits are continuously transmitted to maintain frequency synchronization between both units.

•Synchronous, in this context, means occurring at the same time, thanks to the presence of a
common clock.

•This method is fast, ensuring efficient and timely data transmission.

•However, it can be costly to implement due to the requirement for a synchronized clock system.
Asynchronous Data Transfer in I/O Interface
Asynchronous data transfer is a mode of communication between input/output (I/O) devices and
the central processing unit (CPU) where the transfer occurs without a fixed timing relationship,
unlike synchronous transfer which relies on a shared clock. This method allows devices with
different speeds to communicate effectively.
Key Features
1.Independent Timing: Data transfer is controlled by handshaking signals rather than a shared
clock, ensuring flexibility between devices operating at different speeds.
2.No Clock Dependency: Both sender and receiver operate independently, which simplifies the
interface design.
3.Handshaking Mechanism: Communication involves control signals (like ACK and REQ) that
coordinate the flow of data.
Strobe Controlled Asynchronous Data Transfer

Strobe control is a method of asynchronous data transfer that uses a single control signal, called
the strobe signal, to coordinate the communication between a sender (e.g., CPU) and a receiver
(e.g., peripheral device).

How Strobe Control Works

The strobe signal is used to indicate that data is available or has been received. Depending on
which component initiates the transfer, strobe control can be classified into two types:
1.Source-Initiated Strobe Transfer
2.Destination-Initiated Strobe Transfer
1. Source-Initiated Strobe Transfer
In this type, the source (sender) generates the strobe signal to indicate that it has placed data on
the bus.
Steps:
1.Data Placement:
1. The source (e.g., CPU) places data on the data bus.
2.Strobe Signal Activation:
1. The source activates the strobe signal to inform the destination that data is ready.
3.Data Reading:
1. The destination (e.g., peripheral) detects the strobe signal and reads the data from the bus.
4.Strobe Signal Deactivation:
1. After a predefined time or when the destination completes the read, the source deactivates
the strobe signal.
|-------|--------------- ---|----------------------|
| Time | Strobe Signal | Data Bus Status |
|-------|-------------------|----------------------|
| T1 | LOW | Data Idle |
| T2 | HIGH (Active) | Data Placed |
| T3 | LOW | Data Read |
Source-Initiated Strobe Transfer

|-------|--------------- ---|----------------------|
| Time | Strobe Signal | Data Bus Status |
|-------|-------------------|----------------------|
| T1 | LOW | Data Idle |
| T2 | HIGH (Active) | Data Placed |
| T3 | LOW | Data Read |
2. Destination-Initiated Strobe Transfer
In this type, the destination (receiver) generates the strobe signal to request data from the source.

Steps:
1.Strobe Signal Activation:
1. The destination sends the strobe signal to request data.
2.Data Placement:
1. The source places data on the bus in response to the strobe signal.
3.Data Reading:
1. The destination reads the data from the bus.
4.Strobe Signal Deactivation:
1. The destination deactivates the strobe signal
once the data is read.
Destination-Initiated Strobe Transfer
Advantages of Strobe Control
1.Simplicity: Uses only one control signal, reducing hardware complexity.
2.Faster Setup: Fewer control lines compared to two-wire handshaking.

Disadvantages of Strobe Control

1.Lack of Feedback: The sender and receiver have no explicit confirmation of each
other’s readiness.
2.Timing Sensitivity: The transfer must occur within a strict time window, making it
less reliable when there are delays.
3.Limited Scalability: As systems grow, strobe control may not efficiently handle
communication with multiple devices.
Handshaking Method in Asynchronous Data Transfer

• The handshaking method is a widely used technique in asynchronous data transfer. It

ensures reliable communication between a sender (source) and a receiver (destination) by
using control signals for coordination.

• Unlike strobe control, which relies on a single signal, the handshaking method uses a two-
wire mechanism (request and acknowledgment signals) to synchronize data transfer.

The process of handshaking can be divided into

two types:
1.Source-Initiated Handshaking
2.Destination-Initiated Handshaking
Key Concepts

1.Two-Wire Control:
1. Request Signal (REQ): Sent by the sender to indicate that data is ready.
2. Acknowledge Signal (ACK): Sent by the receiver to confirm that data has been
received.
2.Mutual Synchronization: Both the sender and receiver wait for appropriate signals before
proceeding, ensuring that data is neither lost nor overwritten.
3.Bidirectional Communication: The method can support data transfer in both directions
using separate handshaking signals for each direction.
1. Source-Initiated Handshaking
In this type, the sender initiates the data transfer.
Steps:
1.Request Signal: The sender places data on the data bus and activates the REQ signal.
2.Acknowledge Signal: The receiver detects the REQ signal and reads the data. It then
activates the ACK signal to confirm receipt.
3.Request Deactivation: Once the acknowledgment is received, the sender deactivates the
REQ signal.
4.Acknowledge Deactivation: The receiver deactivates the ACK signal, indicating readiness
for the next data.
Source-Initiated Handshaking
2. Destination-Initiated Handshaking
In this type, the receiver initiates the data transfer.
Steps:
1.Acknowledge Signal: The receiver activates the ACK signal to request data from the
sender.
2.Request Signal: The sender places data on the data bus and activates the REQ signal to
indicate data availability.
3.Acknowledge Deactivation: The receiver deactivates the ACK signal after reading the data.
4.Request Deactivation: The sender deactivates the REQ signal, indicating the completion of
the transfer.
Destination-Initiated Handshaking
 Modes of Data Transfer

modes of transfer define how data is

transferred between a processor and
peripheral devices or memory.

There are three main types of data transfer modes used in computer
systems to facilitate communication between the processor, memory,
and I/O devices:
 Programmed I/O
 Interrupt Initiated I/O
 Direct Memory Access (DMA) I/O
Programmed I/O

Description:
•In this mode, the CPU is responsible for all aspects of data
transfer.
•The CPU executes specific instructions to communicate with the
I/O device.
•It continuously checks the device's status to see if it is ready for
data transfer, a process called polling.

Working:
1.The CPU issues a command to the I/O device, such as a read or
write operation.
2.The CPU repeatedly checks the device status register until the
device signals it is ready.
3.Once ready, the CPU performs the data transfer (read or write).
4.This process is repeated for every word of data.
Read and Write Mode in
Programmed I/O
Advantages:
1.Simple implementation as no additional hardware is needed.
2.Direct control by the CPU ensures compatibility with various devices.

Disadvantages:
3.Inefficient: The CPU spends significant time polling the device instead of performing
other tasks.
4.Low performance: Not suitable for high-speed or high-volume data transfer.

Applications:
•Systems with low-speed peripherals like keyboards, mice, or printers.
•Early computing systems.
Interrupt-Initiated I/O

Concept:

• Interrupt-Initiated I/O uses hardware signals, known as interrupts, to inform the CPU
when a device is ready to transfer data or requires attention.

• This mechanism allows the CPU to perform other tasks while the I/O device is preparing
for communication, thus improving overall system efficiency.
How It Works

1.CPU Sends Command via I/O Interface:

•The CPU communicates with the I/O device through the I/O interface, which includes
device controllers and ports.
•The interface decodes the CPU's commands (e.g., Read, Write) and sends them to the
respective device.
2.I/O Device Prepares for Operation:
•The I/O interface manages the device’s status and ensures the device is ready to process the
command.
•If the device is not ready, the CPU can continue other tasks until an interrupt is generated.
3.Device Generates Interrupt:
•Once the device completes its task (e.g., data is ready for transfer), the I/O interface
generates an interrupt signal to notify the CPU.
4.Interrupt Handled by CPU:
•The CPU acknowledges the interrupt through the I/O interface.
•The I/O interface directs the CPU to the appropriate Interrupt Service Routine (ISR) for
handling the device.
How It Works

5. Data Transfer via I/O Interface:

•The I/O interface facilitates data
exchange between the CPU and
the device.
•Data is moved using control
signals, address decoding, and
data lines managed by the
interface.
6. Completion and Resume:
•After servicing the interrupt, the
CPU resumes its previous tasks.
Advantage’s
•Efficiency
Interrupt-initiated I/O is more efficient than polling I/O because it avoids unnecessary
checks.
•Responsiveness
Interrupt-initiated I/O allows devices to be serviced immediately when they have data to
transfer, resulting in faster response times
Disadvantage’s
•Complexity
Writing and managing interrupt service routines (ISRs) can add complexity and overhead to
code.
•Conflicts and errors
If multiple I/O devices share the same interrupt line or priority level, conflicts and errors can
arise.
 Direct Memory Access (DMA)
• Direct Memory Access (DMA) is a data transfer technique that allows hardware devices
(e.g., disk drives, graphics cards, or network cards) to transfer data directly to and from the
main memory without involving the CPU for each step of the transfer.
• DMA is commonly used in high-speed data transfer scenarios to improve system efficiency
and performance.
• CPU grants an authority to I/O interface to read from and write to main memory without its
involvement.
• DMA itself control data transfer between main memory and I/O devices.
• CPU only involved in beginning and end of the transfer and interrupt only when complete
data has been transferred.
• DMA increases the “Data Transfer Rate”.
 The process involves the CPU initiating the DMA
controller to transfer data between a device and
main memory, allowing the CPU to proceed with
other tasks.
 The DMA controller issues a request to the
relevant I/O device, manages the data transfer
between the device and main memory, and waits
for its completion.
 Upon the conclusion of the data transfer, the
DMA controller interrupts the CPU.
 Between I/O devices and the CPU, there exists an
interface, but between memory and I/O devices, the
DMA controller (or DMA channel) acts as the
intermediary, creating a channel between main
memory and I/O devices.

 Devices such as magnetic disks, USB drives,

network cards, graphics cards, and sound cards,
when connected via DMA, can achieve faster data
transfer rates.
Within the system bus, comprising address lines, data lines, and control lines connected to
the CPU, memory, and DMA controller, during DMA transfers, the CPU is temporarily
disabled. While the CPU typically controls the system bus, in DMA transfers, the DMA
controller temporarily borrows control of the system bus from the CPU to facilitate efficient
data transfer between I/O devices and memory.
How DMA makes CPU to go in idle state?

 To facilitate DMA's control over the bus system

from the CPU, two signals are employed: Bus
Request (BR) and Bus Grant (BG).

 When DMA desires full control of the bus system, it initiates the process by sending a Bus
Request (BR) signal through the bus request line.

 Upon receiving the Bus Request (BR) signal, the CPU interrupts its ongoing tasks, relinquishes
control of all three components—data lines, address lines, and control lines—and enters a high-
impedance state. In this state, the bus behaves like an open circuit, disabling all signals and
buses.
 To signal to the DMA that control has been transferred, the CPU sends a Bus Grant (BG) signal
through the bus grant line, indicating that the DMA now has authority over the buses. This
communication allows the DMA to use the buses to transfer data directly to memory.
DMA Working (Steps)

1. DMA Controller Requests Bus Access:

 The DMA controller signals the CPU with a Bus Request (BR) signal when it needs access
to the system bus.
 This signal indicates that the DMA controller wants control over the address, data, and
control lines of the bus.

2. CPU Relinquishes the Bus:

 On receiving the BR signal, the CPU completes its current operation and enters an idle
state.
 The CPU responds by sending a Bus Grant (BG) signal to the DMA controller, allowing it
to take control of the bus.
DMA Working (Steps) Cont….

3 DMA Controller Gains Bus Mastership:

 After receiving the BG signal, the DMA controller assumes control of the bus and
disconnects the CPU from it.
 The CPU is effectively "idle" during this period and cannot access the bus.
4. DMA Controller Communicates with I/O Device:
 The DMA controller provides an acknowledgment signal to the I/O device, informing it
that the system bus is now available for data transfer.
DMA Working (Steps) Cont. …

5. Data Transfer Between Device and Memory:

 The I/O device transfers data directly to/from the memory through the DMA controller,
bypassing the CPU.
 The DMA controller uses memory addresses and control signals to facilitate the transfer.
6. Transfer Completion:
 After the data transfer is complete, the DMA controller releases the bus by deactivating the
BR signal.
7. CPU Resumes Control:
 Once the BR signal is deactivated, the CPU regains control of the bus and resumes its
normal operations.
Types of DMA Transfers
1.Burst Mode:
1. The DMA controller takes full control of the system bus and transfers large data in one
continuous burst at high speed. This can temporarily block CPU access to the bus.
2. In this, the process is not stop in the middle till completion of transfer process.
2.Cycle Stealing Mode:
1. The DMA controller transfers one word of data at a time, relinquishing the bus to the CPU
after each word. This reduces bus contention but slows down data transfer.
DMA Working
• DS (DMA Select): The processor sets DS = 1 to activate DMA, initiating the DMA process.

• RS (Register Select): The CPU uses this signal to select DMA registers for storing values,
such as the starting address and the number of words to be transferred.

• RD (Read) & WR (Write): These signals, Iri is used for reading and writing purposes during
the DMA operation.

• BR (Bus Request): DMA employs this line to send a request to the processor to release the
BUS system, indicating its need for control over the system bus.

• BG (Bus Grant): When the processor relinquishes control of the bus to DMA, it sets BG = 1,
signifying that the bus is now granted to the DMA controller.
• Interrupt: DMA uses this line to send a signal when data transfer is completed. The processor
can also use this line to check whether data transfer has been successfully completed.

• DMA Request: I/O devices utilize this line to send a request to the DMA controller, signaling
the need for data transfer.

• DMA Acknowledgement: The DMA controller responds to I/O devices through this line,
acknowledging the receipt of the request and preparing for data transfer.

• Address Register: The processor stores the starting address of data in this register, providing
the necessary information for the DMA controller to locate the data.

• Word Count Register: The processor stores the total number of words to be transferred in this
register, allowing the DMA controller to determine the extent of the data transfer operation.
• Control Register: The processor stores control signals in this register, dictating various
aspects of the DMA operation, such as the transfer mode and direction.

• Data Bus Buffer: This component is employed to temporarily store data during the DMA
transfer process, ensuring efficient and synchronized data movement.

• Data Bus: DMA utilizes this bus for the actual transfer of data between memory and
peripheral devices, facilitating high-speed and direct communication.
Summary
 Initiation of Data Transfer Request: When an I/O device wishes to transfer data, it sends a
request to the DMA through the DMA request line.
 Bus Request to Processor: DMA, in response to the request, sends a bus request (BR = 1) to
the processor, requesting it to release control of the bus system (utilizing the BR line).
 Processor's Response: Upon receiving the bus request, the processor stores its current work,
and then transmits essential information, such as the starting address and the number of words
to be transferred, to DMA. Subsequently, the processor relinquishes control of the bus system
and notifies DMA by setting the BG line to 1.
 DMA Acknowledgement and Data Transfer: Upon receiving the BG signal, DMA activates
the DMA acknowledgement line, informing the I/O device that it can commence data transfer.
The DMA controller initiates the actual data transfer process.
Summary Cont……

 Decrementing Word Count: With each data transfer, the value of the Word Count (WC)
register is decremented by 1, keeping track of the progress of the data transfer operation.
 Data Transfer Completion: When the WC register reaches 0, DMA sets BR = 0 and sends an
interrupt signal to the CPU, signaling the completion of the data transfer.
 CPU's Post-Transfer Actions: The CPU, upon receiving the interrupt, checks the WC register.
Since it is now 0, the CPU sets BG = 0, reclaiming control of the bus system for its own
operations.
Thank you for your patience.

Any Question!!!!!!