Unit III MIPS Processor

• A microprocessor is an integrated circuit that

performs computing tasks.
• It acts as the brain of a computer, executing
instructions from memory.
• Evolution: Started from 4-bit processors to
modern multi-core processors.
• Applications: Used in PCs, embedded systems,
industrial automation, and more.
 Microprocessor

• Basic Components:
- ALU (Arithmetic Logic Unit): Performs mathematical and
logical operations.
- CU (Control Unit): Directs operations within the processor.
- Registers: Small storage units for temporary data.
• Data Flow: Instructions fetched from memory, decoded, and
executed.
• Instruction Set Architecture (ISA): Defines supported operations
and formats.
 Instruction Set and Execution

• Types of Instructions:
- Data transfer (MOV, LOAD, STORE)
- Arithmetic & logical (ADD, SUB, AND, OR)
- Control (JUMP, CALL, RETURN)
• Addressing Modes:
- Immediate, Register, Direct, Indirect
• Execution Cycle:
- Fetch → Decode → Execute → Store
 Memory and I/O Interface

• Memory Hierarchy:
- Registers → Cache → RAM → Hard Disk
• I/O Interfacing:
- Parallel and Serial communication
- Memory-mapped and I/O-mapped addressing
• Bus Architecture:
- Address Bus (selects memory locations)
- Data Bus (transfers data)
- Control Bus (manages operations)
 Advanced Microprocessor Features

• Pipelining: Overlapping instruction execution to

enhance speed.
• Parallel Processing: Multi-core processors for
improved performance.
• Cache Memory: Stores frequently used data to
reduce latency.
• Power Optimization: Efficient power
management techniques in modern processors.
 Load–store architecture (or a register–register architecture) is an
instruction set architecture that divides instructions into two
categories: memory access (load and store between memory and
registers) and ALU operations (which only occur between registers.

Reduced instruction set computer (RISC) is a

computer architecture designed to simplify the individual instructions
given to the computer to accomplish tasks.

Compared to the instructions given to a

complex instruction set computer (CISC), a RISC computer might
require more instructions (more code) in order to accomplish a task
because the individual instructions are written in simpler code.
MIPS Data Path Operation

1. Instruction Fetch (IF): PC fetches instruction from instruction

memory.
2. Instruction Decode (ID): Instruction is decoded, and register
values are read.
3. Execution (EX): ALU processes the instruction.
4. Memory Access (MEM): Data memory is accessed if
required.
5. Write Back (WB): The computed value is written back to the
register file.
In the MIPS processor architecture, the data path elements are the key
components responsible for instruction execution. These elements work together
to fetch, decode, execute, and store results efficiently. Below are the major
elements of the MIPS processor data path:
1. Program Counter (PC)
•Stores the address of the next instruction to be fetched.
•Updates sequentially (PC + 4) unless a branch/jump occurs.
2. Instruction Memory
•Stores the program instructions.
•Fetches the instruction based on the value in the PC.
3. Instruction Decoder / Control Unit
•Decodes the fetched instruction.
•Generates control signals for various components.
4. Register File
•Contains 32 general-purpose registers
•Reads two registers (Rs and Rt) and writes the result to a destination register
(Rd).
5. ALU (Arithmetic Logic Unit)
•Performs arithmetic and logic operations (e.g., addition, subtraction, AND,
OR).
•Supports comparison operations (e.g., branch decisions).
6. Sign Extender
•Converts 16-bit immediate values into 32-bit format for processing.
7.Data Memory
•Used for lw (load word) and sw (store word) instructions.
•Loads/stores data between registers and memory.
8. Multiplexers (MUX)
•Select between different inputs based on control signals.
•Used to choose between ALU inputs, write destinations, and
branch/jump addresses.
9. Branch Logic
•Determines the next PC value for branch/jump instructions.
•Compares register values to decide if branching is required.
10. Pipeline Registers (For Pipelined MIPS)
•Stores intermediate values between instruction stages.
•Helps achieve instruction parallelism.
 Control Implementation Schemes
Load word & Store word – ALU addition (to compute memory address)
Arithmetic and logical instructions – Add, sub, and, or, set on less than (for R type instruction)
Branch – beq & bne – ALU subtraction
ALU Control lines & its functions:
0000 – AND
0001 – OR
0010 – Add
0110 – Sub
0111 – slt
1100 – NOR
 Pipelining
Pipelining is a technique used in MIPS (Microprocessor without Interlocked
Pipeline Stages) to improve instruction throughput by overlapping the
execution of multiple instructions.
Instead of executing instructions sequentially, pipelining allows multiple
instructions to be in different stages of execution simultaneously.
Each segment consists of input along with combinational circuits.
Each execution has 5 subtasks in MIPS -IF ID OF IE OS

PIPELINE SPEEDUP:
If the stages are perfectly balanced, then the time interval between the
instructions in the pipelined processor assuming ideal condition:
Time between instruction pipelined = Time between instruction non
pipelined / No of Pipelined stages
 Pipeline Performance Improvement

• Without pipelining: A single instruction

completes in 5 clock cycles.

• With pipelining: New instructions start every

cycle, achieving one instruction per cycle
throughput (ideal case).
 Pipeline Hazards
Pipelining introduces potential issues called hazards, which can cause stalls or
incorrect execution.

Hazards occur when the next instruction cannot execute the following clock
cycles.

Types of hazards:

Structural hazard
Data hazard
Control Hazard

a) Structural Hazards
•Occurs when two instructions try to use the same hardware resource
simultaneously.
•Solution: Use separate instruction and data memory or multi-port registers.
b) Data Hazards
•Occurs when an instruction depends on the result of a previous instruction
that has not yet completed.

• Unavailability of data in an instruction then the pipeline must be stalled, one

instruction must wait for another to be completed.

•When a planned instruction cannot be executed in proper clock cycle because

data needed to execute an instruction is not available.

•In a computer pipeline data hazard arise from the dependency of one
instruction on the previous instruction that is still in the pipeline.
•Example:

ADD $t1, $t2, $t3

SUB $t4, $t1, $t5

# Data hazard: $t1 is not yet updated

The add instruction writes the result in the fifth stage of clock cycle. Sub
instruction must wait – Stall (bubble) for three clock cycles.
Data forwarding:

• Forwarding (Bypassing): Use the result from EX/MEM stage instead

of waiting for WB. (resolving a data hazard)

• As soon as ALU creates sum for the ADD instruction it can be given as
input for SUB instruction.

• If the first instruction is (lw) loaded instead of ADD, then the desired
data is available only after the fourth stage of the first instruction.

• Hence even with the forwarding we must stall for one clock cycle.

• Pipeline stall is also known as bubble.

• Pipeline Stall (NOP insertion): Delay execution until data is available.

Reordering of code:

Conside the code segement c

a=b+e
c=b+f

Lw $t1, 0($t0)
Lw $t2, 4($t0)
ADD $t3, $t1, $t2
sw $t3, 12($t0)
Lw $t4, 8($t0)
ADD $t5, $t1, $t4
sw $t5, 16($t0)
Reordering of code:

Conside the code segement c

a=b+e
c=b+f

Lw $t1, 0($t0)
Lw $t2, 4($t0)
Lw $t4, 8($t0)
ADD $t3, $t1, $t2
sw $t3, 12($t0)
ADD $t5, $t1, $t4
sw $t5, 16($t0)
Control Hazards
•Occurs due to branch (jump) instructions when the next instruction is
unknown

•It arises from the need to make decision based on the result of the
instruction while the others are executing.

•Example:

BEQ $t1, $t2, LABEL

•Solution:
• Branch Prediction (guess the branch outcome).
• Branch Delay Slot (reorder instructions to minimize stalls).

• If TRUE instead of moving to OR instruction it moves to ADD –

control hazard.
Example of MIPS Pipeline Execution

Consider the following instruction sequence:

assembly
LOAD $t1, 0($t2)
ADD $t3, $t1, $t4
SUB $t5, $t3, $t6
Cycle IF ID EX MEM WB

1 LOAD

2 ADD LOAD

3 SUB ADD LOAD

4 SUB ADD LOAD

5 SUB ADD LOAD

6 SUB ADD

Pipeline execution:
7 SUB

•Without stalls, one instruction completes per cycle after the pipeline fills.
•Data hazards might require forwarding or stalling to resolve dependencies.
 MIPS Pipeline Optimizations

•Forwarding: Reduces stalls by using ALU results before WB.

•Branch Prediction: Reduces control hazard delays.
•Delayed Branching: Executes an instruction in the branch
Cycle IF ID EX MEM WB

1 LOAD

2 ADD LOAD

3 SUB ADD LOAD

4 SUB ADD LOAD

5 SUB ADD LOAD

6 SUB ADD

7 SUB

delay slot.
•Multiple Issue (Superscalar Execution): Executes multiple
instructions per cycle.
 Branch Prediction:

It is the method of predicting the branch outcome:

Static branch prediction

Dynamic branch prediction

Static branch prediction: Cycle

7
IF

LOAD

ADD

SUB
ID

LOAD

ADD

SUB
EX

LOAD

ADD

SUB
MEM

LOAD

ADD

SUB
WB

LOAD

ADD

SUB

It is used to predict always that the branches are not taken NT

When the prediction is right the pipeling proceeds at full speed.

When the branches are taken the pipeline stalls- when there is misprediction
Dynamic branch prediction:

The dynamic prediction hardware guesses depending on the behaviour of each branch
and may change the prediction for a branch over the life of a program using runtime
information.

Prediction of branches at runtime using runtime information.

It is based on the recent past behaviour to predict the future.

Types:
Cycle IF ID EX MEM WB

1 LOAD

2 ADD LOAD

3 SUB ADD LOAD

One bit branch prediction:

4 SUB ADD LOAD

5 SUB ADD LOAD

6 SUB ADD

7 SUB

After one-bit wrong prediction, predicted bit is inverted. Implementation of this approach
is that contains branch prediction buffer ( small memory indexed by the lower portion of
the address of the branch instruction).

The memory contains a bit 1 or 0 ( depending on this whether the branch is recently taken
or not)
Ex:

NT T T T T NT

Perform bit inversion NT as T

Even if the branch is almost T we can predict incorrectly twice rather than
ones when it is NT. Prediction accuracy is 80%

Two bit branch prediction: Cycle IF ID EX MEM WB

1 LOAD

2 ADD LOAD

3 SUB ADD LOAD

4 SUB ADD LOAD

5 SUB ADD LOAD

6 SUB ADD

7 SUB

The prediction changes according to the history of the individual branch

instruction.

00 – Strongly NT
11 – Strongly T
10 – Weakly T
01 – Weakly NT
Cycle IF ID EX MEM WB

1 LOAD

2 ADD LOAD

3 SUB ADD LOAD

4 SUB ADD LOAD

5 SUB ADD LOAD

6 SUB ADD

7 SUB