Advanced architecture

Edited
By
Fehmida Sadaf Bhatti
Reading from memory
• Multiple machine cycles are required when reading from
memory, because it responds much more slowly than the
CPU. The four steps are:
– address placed on address bus
– Read Line Cycle
(RD) 1
set lowCycle 2 Cycle 3 Cycle 4

– CPU waits one cycle for memory to respond

– CLK
Read Line (RD) goes to 1, indicating that the data is on
the data bus
Address
ADDR

RD

Data
DATA
Reading from memory
• Multiple machine cycles are required when reading from
memory, because it responds much more slowly than the
CPU. The four steps are:
– address placed on address bus
– Read Line (RD) set low
– CPU waits one cycle for memory to respond
– Read Line (RD) goes to 1, indicating that the data is on
the data bus
Cache memory
• High-speed expensive static RAM both
inside and outside the CPU.
– Level-1 cache: inside the CPU
– Level-2 cache: outside the CPU
• Cache hit: when data to be read is already
in cache memory
• Cache miss: when data to be read is not in
cache memory. When? compulsory,
capacity and conflict.
• Cache design: cache size, n-way, block
size, replacement policy
How a program runs
Multitasking
• OS can run multiple programs at the same
time.
• Multiple threads of execution within the
same program.
• Scheduler utility assigns a given amount of
CPU time to each running program.
• Rapid switching of tasks
– gives illusion that all programs are running at
once
– the processor must support task switching
– scheduling policy, round-robin, priority
IA-32 architecture
• From 386 to the latest 32-bit processor, P4
• From programmer’s point of view, IA-32
has not changed substantially except the
introduction of a set of high-performance
instructions
Modes of operation
• Protected mode
– native mode (Windows, Linux), full features,
separate memory

• Virtual-8086 mode
• hybrid of Protected
• each program has its own 8086 computer

• Real-address mode
– native MS-DOS
• System management mode
– power management, system security,
diagnostics
Addressable memory

• Protected mode
– 4 GB
– 32-bit address
• Real-address and Virtual-8086
modes
– 1 MB space
– 20-bit address
General-purpose registers
Named storage locations inside the CPU, optimized for
speed.

32-bit General-Purpose Registers

EAX EBP
EBX ESP
ECX ESI
EDX EDI

16-bit Segment Registers

EFLAGS CS ES
SS FS
EIP
DS GS
Accessing parts of registers
• Use 8-bit name, 16-bit name, or 32-bit name
• Applies to EAX, EBX, ECX, and EDX
Index and base registers
• Some registers have only a 16-bit name
for their lower half. The 16-bit registers
are usually used only in real-address
mode.
Some specialized register uses (1
of 2)
• General-Purpose
– EAX – accumulator (automatically used by
division and multiplication)
– ECX – loop counter
– ESP – stack pointer (should never be used
for arithmetic or data transfer)
– ESI, EDI – index registers (used for high-
speed memory transfer instructions)
– EBP – extended frame pointer (stack)
Some specialized register uses (2
of 2)
• Segment
– CS – code segment
– DS – data segment
– SS – stack segment
– ES, FS, GS - additional segments
• EIP – instruction pointer
• EFLAGS
– status and control flags
– each flag is a single binary bit (set or clear)
Status flags
• Carry
– unsigned arithmetic out of range
• Overflow
– signed arithmetic out of range
• Sign
– result is negative
• Zero
– result is zero
• Auxiliary Carry
– carry from bit 3 to bit 4
• Parity
– sum of 1 bits is an even number
Assembler

NASM

The Netwide Assembler

Or
MASM
Linker

ALINK
Debugger

AFD

Advanced Full Screen Debug

EX01.ASM
[ORG 0X100]

mov ax,5
mov bx,10
Add ax,bx
Mov bx,15
Add ax,bx

Mov ax,0x4c00
Int 0x21
EX01.LST
Word Representation
• 4 Byte Word
• Representation in Memory

MSB LSB

Representation 1
Little Endian Notation MSB LSB
0 1 2 3
Representation 2
Big Endian Notation LSB MSB
0 1 2 3
IA-32 Memory
Management
Real-address mode
• 1 MB RAM maximum addressable (20-bit
address)
• Application programs can access any area
of memory
• Single tasking
• Supported by MS-DOS operating system
Segmented memory
Segmented memory addressing: absolute (linear)
address is a combination of a 16-bit segment value
added to a 16-bit offset
linear addresses

one segment
Segmented memory
Segmented memory addressing: absolute (linear)
address is a combination of a 16-bit segment value
added to a 16-bit offset
Overlapping
Physical Address
Calculation
16-bit segment 16-bit offset

0000 0000
20-bit segment 20-bit offset
+

20-bit Physical Address

Address Calculation

1 D D D 0
+ 0 0 1 0 0
1 D E D 0

20 –Bit Physical Address Calculation

Segment Base

16 – Bit Segment Register Value

0 0 0 0

0 0 0 0 0
20 – Bit Segment = 0 Decimal
Segment Base

16 – Bit Segment Register Value

0 0 0 1

0 0 0 1 0
20 – Bit Physical Address = 16 Decimal
Calculating linear addresses
• Given a segment address, multiply it by 16 (add
a hexadecimal zero), and add it to the offset
• Example: convert 08F1:0100 to a linear address

Adjusted Segment value: 0 8 F 1 0

Add the offset: 0 1 0 0
Linear address: 0 9 0 1 0

• A typical program has three segments: code,

data and stack. Segment registers CS, DS
and SS are used to store them separately.
Example

What linear address corresponds to the segment/offset

address 028F:0030?

028F0 + 0030 = 02920

Always use hexadecimal notation for addresses.

Example

What segment addresses correspond to the linear

address 28F30h?

Many different segment-offset addresses can produce

the linear address 28F30h. For example:
28F0:0030, 28F3:0000, 28B0:0430, . . .
Protected mode (1 of 2)
• 4 GB addressable RAM (32-bit address)
– (00000000 to FFFFFFFFh)
• Each program assigned a memory
partition which is protected from other
programs
• Designed for multitasking
• Supported by Linux & MS-Windows
Protected mode (2 of 2)
• Segment descriptor tables
• Program structure
– code, data, and stack areas
– CS, DS, SS segment descriptors
– global descriptor table (GDT)
• MASM Programs use the Microsoft flat
memory model
Multi-segment model
• Each program has a local descriptor table (LDT)
– holds descriptor for each segment used by the program

multiplied by
1000h
Flat segmentation model
• All segments are mpped to the entire 32-bit physical
address space, at least two, one for data and one for code
• global descriptor table (GDT)
Paging
• Virtual memory uses disk as part of the
memory, thus allowing sum of all programs
can be larger than physical memory
• Divides each segment into 4096-byte
blocks called pages

• Page fault (supported directly by the CPU) –

issued by CPU when a page must be loaded
from disk
• Virtual memory manager (VMM) – OS utility
that manages the loading and unloading of
pages