Central Processing Unit

Introduction to COA
Computer architecture is concerned with the structure and
behavior of the computer as seen by the user.
It includes the information formats, the instruction set,
and techniques for addressing memory, I/O mechanisms,
number of bits used for data representation, etc...

The architectural design of a computer system is

concerned with the specifications of the various functional

modules, such as processors and memories, and
structuring them together into a computer system.
Computer organization is concerned with the way the
hardware components operate and the way they are connected
together to form the computer system.
Computer Organization is how the features are
implemented, and will include Control signals, interfaces,
memory technology, etc........
It is an architectural design issue whether a
computer is having a multiply instruction or not.

It is an organizational issue whether that instruction is

implemented by a special multiply unit or by a
mechanism

that makes repeated use of the add unit of the system.

The top level Structure of a Computer System

The CPU – Structure

The part of computer that does data processing operations is
called central processing unit (CPU)
The CPU is made of 3 major parts:
 Registers: stores intermediate data generated during
execution.

 ALU: performs required micro operations

 Control Unit: Decodes the instructions and controls
transfer of data among registers and instruct ALU to
perform correct operation
 BUS: a transfer medium in which all transfer of data
takes place through it.
The CPU – Structure
General Register Organization

Intermediate data are needed to be stored like pointers,

counters, temp results, and partial products.

It cannot be saved in main memory because their access

is time consuming.

It is more efficient and faster to be stored inside the

processor itself.

 So the solution is designing multiple registers inside

processor and connects them through a common bus.

 Registers are fast memories, but limited in storage

capacity.
 The data register (DR) acts as a buffer between the
CPU and main memory.

It is used as an input operand register with the

accumulator.
 The address register (AR) holds the address of the
memory in which the operand resides.

 The instruction register (IR) holds the opcode of the

current instruction.

 The program counter (PC) holds the address of the next

instruction to be fetched for execution.

 Additional addressable registers can be provided for

storing operands and address.

This can be viewed as replacing the single accumulator

by a set of registers.

If the registers are used for many purposes, the resulting

computer is said to have general purpose register
organization.

In the case of processor registers, a register is selected

by the multiplexers that form the buses as shown in the
figure below.
Stack Organization

Stack is a storage device that stores information in a way

Of (LIFO).
Stack in computers is a memory unit with address
register called as stack pointer (SP).

SP value always points at top item in stack.

The two operations done on stack are:

PUSH (Push Down) - operation of insertion of items into
stack.
POP (Pop Up) - operation of deletion of item from stack.

These operations are simulated by Incrementing and

Decrementing stack register (SP) value.
In digital computers, stack can be implemented in two ways:

 Register Stack

 Memory Stack

Register Stack
A standalone unit that consists of collection of finite number
of registers.

The below given example shows 64 location stack unit with

SP that stores address of the word that is currently on the top

of stack.
The one-bit register FULL is set to 1 when the stack is
full;
similarly, one-bit register EMPTY is 1 when the stack is
empty.

The data register DR holds the data to be written into or

read from the stack.

Stack Limits
Check for stack overflow (full) / underflow (empty)

 Checked by using two register

Upper Limit and Lower Limit Register

 After PUSH Operation

SP compared with the upper limit register

 After POP Operation

SP compared with the lower limit register

 Procedures for PUSH ing Stack

Initially, SP = 0, EMPTY = 1, FULL =0

Note that:
1. Always we use DR to pass word into stack

2. M[SP] memory word specified by address currently in SP

3. First item stored in stack is at address 1

4. Last item stored in stack is at address 0. That is FULL = 1

 Procedures for POP ing Stack

Note That:

1. Top of stack is read into DR

2. If SP reached 0 then stack is EMPTY = 1. No more

pops can happen from here.

3. Any pop from stacks means FULL = 0

 Memory Stack

A stack can also be implemented in a random access

memory attached to CPU.

The implementation of a memory stack is done by assigning

a portion of memory to a stack operation and using a

processor register (SP) as a stack pointer.

A new item is inserted (PUSH operation) as follows:-

SP← SP+1
M [SP] ← DR

The stack pointer is incremented so that it points at the

address of the next word and the word from DR will be
written onto the top of the stack.

A new item is deleted (POP operation) follows:-

DR← M [SP]
SP←SP - 1
The top item is read from the stack in to DR. The stack
pointer is then decremented to point at the next item in the
stack.

Difference between register stack & memory stack

• Register stack is generally on the CPU and

Memory stack is on the RAM.

• So we can say that access to register stack is faster when

compared to memory stack.

• Memory stack can be large in size wise where as register

stack is limited in size.
 Instruction Formats

The machine instruction has an opcode (operation code)

and zero or more operands.

An opcode :-specifies what operation should carry out

An operand :-specifies the parties (registers, memory

location, etc…) those are involved in that operation.

Example : ADD R1 , R2

This is an instruction where ADD is the opcode and R1 and

R2 are the two operands.

Operands are separated by a coma.

 INSTRUCTION FORMATS
• A computer will usually have a variety of instruction
code formats.
• It is the function of the control unit within the CPU to
interpret each instruction code and provide the
necessary control functions needed to process the
instruction.
• The most common fields found in instruction formats
are:
• An operation code field: that specifies the operation
to be performed.
• The operation code field of an instruction is a group
of bits that define various processor operations,
such as add, subtract, complement, and shift
• An address field: that designates a memory address
or a processor registers.
• A mode field: that specifies the way the operand or
the effective address is determined.
• The bits that define the mode field of an instruction
code specify a variety of alternatives for choosing
the operands from the given address.
 INSTRUCTION FORMATS

• Computers may have instructions of

several different lengths containing
varying number of addresses.
• The number of address fields in the
instruction format of a computer
depends on the internal organization of
its registers.
• Most computers fall into one of three
types of CPU organizations:
• Single accumulator organization.
• General register organization.
• Stack organization.
 Single accumulator organization

• In this type of CPU organization all operations are

performed with an implied accumulator register.
• The instruction format in this type of computer uses
one address field.
• For example, the instruction that specifies an
arithmetic addition is defined by an assembly
language instruction as ADD X.
• Where X is the address of the operand.
• The ADD instruction in this case results in the
operation
• AC ← AC + M[X].
• AC is the accumulator register and M[X]
symbolizes the memory word located at address
X.
 General register organization.
• The instruction format in this type of computer
needs three register address fields.
• Thus, the instruction for an arithmetic addition may
be written in an assembly language as:
• ADD R1, R2, R3
• To denote the operation R1 ← R2 + R3. The number
of address fields in the instruction can be reduced
from three to two if the destination register is the
same as one of the source registers.
• Thus the instruction ADD R1, R2 Would denote the
operation R1 ← R1 + R2. Only register addresses for
R1 and R2 need be specified in this instruction.
• Computers with multiple processor registers use the
move instruction with a mnemonic MOV to symbolize
a transfer instruction.
 Stack organization.
• Computers with stack organization would have
PUSH and POP instructions which require an address
field.
• Thus, the instruction PUSH X Will push the word at
address X to the top of the stack.
• The stack pointer is updated automatically.
• Operation-type instructions do not need an address
field in stack-organized computers. This is because
the operation is performed on the two items that
are on top of the stack.
• The instruction ADD In a stack computer consists of
an operation code only with no address field.
• This operation has the effect of popping the two top
numbers from the stack, adding the numbers, and
pushing the sum into the stack.
• There is no need to specify operands with an
address field since all operands are implied to be in
the stack.
 THREE-ADDRESS INSTRUCTIONS
• Computers with three-address
instruction formats can use each
address field to specify either a
processor register or a memory
operand.
• The program in assembly language
that evaluates X = (A + B) ∗ (C + D)
is shown below.
• ADD R1, A, B R1 ← M [A] + M [B]
• ADD R2, C, D R2 ← M [C] + M [D]
• MUL X, R1, R2 M [X] ← R1 ∗ R2

• It is assumed that the computer has

two processor registers, R1 and R2.
The symbol M [A] denotes the
operand at memory address
symbolized by A.
• The advantage of the three-address
format is that it results in short
 TWO-ADDRESS INSTRUCTIONS

• Two address instructions are the most common

in commercial computers. Here again each
address field can specify either a processor
register or a memory word.
• The program to evaluate X = (A + B) ∗ (C +
D) is as follows:
• MOV R1, A R1 ← M [A]
• ADD R1, B R1 ← R1 + M [B]
• MOV R2, C R2 ← M [C]
• ADD R2, D R2 ← R2 + M [D]
• MUL R1, R2 R1 ← R1∗R2
• MOV X, R1 M [X] ← R1
• The MOV instruction moves or transfers the
operands to and from memory and processor
registers.
• The first symbol listed in an instruction is
assumed to be both a source and the
destination where the result of the operation is
transferred.
 One Address Instructions

• One-address instructions use an implied

accumulator (AC) register for all data
manipulation.
• For multiplication and division there is a
need for a second register. However,
here we will neglect the second and
assume that the AC contains the result
of tall operations.
• The program to evaluate X = (A + B) ∗ (C + D) is
• LOAD A AC ← M [A]
• ADD B AC ← A C + M [B]
• STORE T M [T] ← AC
• LOAD C AC ← M [C]
• ADD D AC ← AC + M [D]
• MUL T AC ← AC ∗ M [T]
• STORE X M [X] ← AC
• All operations are done between the AC register and a
memory operand
• T is the address of a temporary memory location
required for storing the intermediate result.
 Zero Address Instructions
• A stack-organized computer does not use an
address field for the instructions ADD and MUL.

• The PUSH and POP instructions, however, need an

address field to
specify the operand that communicates with the
stack.

• The following program shows how X = (A + B) ∗ (C

+ D) will be written for a stack organized computer.
(TOS stands for top of stack)

• PUSH A TOS ← A
• PUSH B TOS ← B
• ADD TOS ← (A + B)
• PUSH C TOS ← C
• PUSH D TOS ← D
• ADD TOS ← (C + D)
• MUL TOS ← (C + D) ∗ (A + B)
• POP X M [X] ← TOS

• The name “zero-address” is given to this type of

computer because of the absence of an address
field in the computational instructions.
Addressing Modes

Addressing mode specifies the way how the address of an

operand is specified in an instruction.

Also, it specifies how the bits of an instruction are

organized to define the operand addresses and operation

of that instruction.

The most common addressing techniques are;

 Immediate Addressing Mode
 Direct Addressing Mode
 Indirect Addressing Mode
 Register Addressing Mode
 Register Indirect Addressing Mode
 Based Addressing Mode
 Indexed Addressing mode
 Based indexed Addressing Mode
 Relative Addressing Mode
 Implied Addressing Mode
Instruction Types
Majorly instruction types are classified into 3

Data Transfer Instructions

Data Manipulation Instructions
Logical and Bit manipulation instructions
 Shift instructions

Program Control instructions

 CISC (Complex Instruction Set Computer)
A computer with large number of instructions is called
complex instruction set computer or CISC.
Complex instruction set computer is mostly used in scientific

computing applications requiring lots of floating point

arithmetic.
Although there is no precise definition for a CISC processor,
most of them share the following characteristics:-
 A large number of instructions - typically from 100 to 250
instructions.
 Some instructions that perform specialized tasks and are
used rarely.
 A large variety of addressing modes - typically 5 to 20
different modes.
 Instructions that manipulate operands in memory.
 Instructions that perform specialized tasks together with
the instructions that support memory-to-memory
operations.
 A range of variable length instructions with variable
execution times.
• A micro-programmed control unit
 RISC (Reduced Instruction Set Computers) Characteristics

Increasing the power of the instruction set allows shorter and more

efficient code to be generated;

because shorter code reduces the number of memory fetches and also
occupies less memory.

A computer with few instructions and simple construction is called

reduced instruction set computer or RISC.

RISC architecture is simple and efficient.

The major characteristics of RISC architecture are,

 Relatively few addressing modes

 All operations are done within the registers of the CPU

 Relatively few instructions, with single-cycle instruction execution.

 Easily decodable fixed-length instruction formats

 Memory access is limited to a few instructions like STORE and

LOAD
 Relatively large general purpose register sets
 Instructions that operate upon operands are stored in registers rather
than in main memory. ie; Register-to-Register operation
THANK YOU!!!
THE END!