DEC Alpha

Course : CS 420
Student : Narith Kun
Instructor : Dr. Chi-
cheng Lin

Date : April 26, 2010

 History

Alpha was born out of an earlier RISC project

named PRISM but it was cancelled. The
decision was also made to upgrade the design
to a full 64-bit implementation from PRISM's
32-bit, a conversion all of the major RISC
vendors were undertaking
The primary Alpha instruction set architects
were Richard L. Sites and Richard T. Witek.
Instruction Set Architecture
The Alpha Approach to RISC Architecture
Alpha is a 64-bit architecture that is designed
with particular emphasis on the three
elements that most affect performance: clock
speed, multiple instruction issue, and
multiple processors.
 What is ISA (alpha DEC)
Aspects of the computer visible to the
programmer:
Data Types
Registers
Instruction format
Addressing
 Data format
Alpha is a load/store RISC architecture with the following data
characteristics:
• All operations are done between 64-bit registers.
• Memory is accessed via 64-bit virtual byte addresses, using the
little-endian or, optionally, the big-endian byte numbering
convention.
• There are 32 integer registers and 32 floating-point registers.
• Longword (32-bit) and quadword (64-bit) integers are supported.
• Five floating-point data types are supported:
– VAX F_floating (32-bit)
– VAX G_floating (64-bit)
– IEEE single (32-bit)
– IEEE double (64-bit)
– IEEE extended (128-bit)
 Instruction
commone
Instruction
 Instruction Format
31-26 25-21 20-16 15-5 4-0

Op code Number PAL format

Op code RA Disp Branch

format
Op code RA RB Disp Memory
format
Op code RA RB Function RC Operate
format
Op code FA FB Function FC Floating Op
 Instruction format
• PAL code (Privileged Architecture Library)
use to specify extended processor function. It
specify in the function code field, one of a few
dozen complex
• Conditional branch instructions test register
Ra and specify a signed 21-bit PC-relative
longword target displacement. Subroutine calls
put the return address in register Ra.
• Load and store instructions move bytes,
words, longwords, or quadwords between
register Ra and memory, using Rb plus a signed
16-bit displacement as the memory address.
 Instruction Format

31-26 25-21 20-16 15-13 12 11-5 4-0

Op code Ra Rb SBZ 0 Functio Rc

n
Op code Ra Lit 1 Functio Rc
n
 Instruction format
• Operate instructions for floating-point and integer
operations
-Word and byte sign-extension operators.
-Floating-point operations use Ra and Rb as source
registers and write the result in register Rc. There is
an 11-bit extended opcode in the function field.
- Integer operations use Ra and Rb or an 8-bit literal
as the source operand, and write the result in
register Rc.
-Integer operate instructions can use the Rb field and
part of the function field to specify an 8-bit literal.
There is a 7-bit extended op code in the function field.
 Operand Notation
 Ra An integer register operand in the Ra field of the
instruction
 Rb An integer register operand in the Rb field of the
instruction
 #b An integer literal operand in the Rb field of the
instruction
 Rc An integer register operand in the Rc field of the
instruction
 Fa A floating-point register operand in the Ra field of the
instruction
 Fb A floating-point register operand in the Rb field of the
instruction
 Fc A floating-point register operand in the Rc field of the
instruction
 Load Address
 Format: LDAx Ra.wq , disp.ab (Rb.ab) !Memory format
 Operation:
 Ra  Rbv + SEXT(disp) !LDA
 Ra  Rbv + SEXT(disp*65536) (sign extension) !LDAH
 Exceptions: None
 Instruction mnemonics:
 LDA Load Address
 LDAH Load Address High
 Qualifiers: None
 Description:
The virtual address is computed by adding register Rb to the sign
extended 16-bit displacement for LDA, and 65536 times the sign-
extended 16-bit displacement for LDAH. The 64-bit result is written
to register Ra.
 Addressing Mode
 Register direct
 Immediate
 Register indirect with displacement
 PC-relative

 Operands in the Alpha can be 1, 2, 4 or 8 bytes in length.

 Processor Design
Alpha 21264:
 Pipelining Stages
DEC Alpha 21264: 9 stages pipeline
Decod
Addres Addres e Addres Addres
s s instruc s s
Write Write
transla transla tion Execut transla transla Tag
registe Memo
te and te and and ion te and te and check
r file ry
cache cache read cache cache
access access registe access access
r
Data path
 Data path
0 1 2 3 4 5
ALU
Shifter

Bran I I ALU
predictio resiste
r issu I Shifter
n renam e regi Mutiplier
e map Que ster
ue File

Data
Cach
e
F-Add,
Instructio Fp FP
divide,
n Cache FP issu regi square root
resiste
e ster
r
renam
Que
e map ue File

F- Multiply
 Conclusion
Design Policies
Design Principle 1: Simplicity favors regularity
 32 register
Design Principle 2: Smaller is faster
Design Principle 3: Make the common case fast
 Immediate operand avoids a load instruction
Design Principle 4: Good design demands good
compromises
 Different formats complicate decoding, but allow 32-bit
instructions uniformly
 Keep formats as similar as possible
 Bi-endian
 Conclusion
 Memory mapped file can be more difficult to
implement in 32-bit architectures. A large
files cannot be memory mapped easily to 32-
bit architectures
 data encryption software can benefit greatly
from 64-bit registers
the same data occupies more space in
memory
x86-based 64-bit systems sometimes lack
equivalents to software that is written for 32-
bit architectures
 this architecture should be more developing
 Work cited
The Alpha architecture handbook, version 4
http://www.comms.scitech.susx.ac.uk/fft/program
ming/alphaahb.pdf
Patterson and Hennessy .Computer
Organization and Design, 4 ed ,
Chapter Six Pipelined Processor Pipelining

http://www.csc.gatech.edu/~copeland/3055-0
0/pdf/lec_04_notes.pdf