Chapter Three

Memory and I/O Interfacing

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 Outline
 Memory Classifications

 Flip-Flop or Latch as a storage Element Memory Map and Addresses

Memory Instruction Fetch

 Memory Interfacing: Memory Structure & it’s Requirements Basic

Concepts in Memory Interfacing and Interfacing Circuits

 Address Decoding & Memory Address

 Input & Output Devices: I/O with 8-Bit Addresses, I/O with 16-Bit Addresses

 Logic Devices for Interfacing Tri-State Devices buffer

 Encoders & Decoders Interfacing of I/O Devices: Basic Interfacing

Concepts Interfacing Output Displays Interfacing Input Devices

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 Memory Classification
 The memory is made up of semiconductor material used
to store the programs and data
 The memory is used to store information used by the
CPU.
 The information may be in the form of program or data.
 Memory can be classified into two groups.
1.Primary Memory
2.Secondary Memory
1. Primary memory
 It is constituted by memory blocks within the address
space of the processor.
 They are implemented by using read only memory(ROM) which
are not volatile memories and read write memories3 or
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1-Primary Memory
 It is a storage which can be directly accessed by the CPU.
 It can be viewed as a stack of words, each word be
associated with a unique address. These words may be
instruction or data.
 A CPU having n address line can access 2n memory
location.
 The total primary memory area is partition into two
separate sections called the ROM area and the
read/write area.
A. ROM
 It is implemented by using a special kind of memory 4
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 For example CPU may initialize the display driver
display outputs, a key-board to accept the certain
commands.

 The data in this selection cannot be written over and

can only the read.
 The ROM is used to store information that should not
change.
 ROMs are available into 4 types. There are
i. Masked ROM ii. PROM iii. EPROM iv.
EEPROM
i-Masked ROM : The instructions in such ROMs are
permanently installed by the manufacturer as for the 5
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iii-EPROM (Erasable PROM)
 It uses most charge storage technology.
 It is also programmable by the user.
 The information stored in the EPROM can be erased by
exposing the memory to ultraviolet light which erase
the data stored the data in total memory area.
 Then the memory can be reprogrammable by the user by
using EPROM burning circuit.
iv-EEPROM (Electrically Erasable PROM)
 This is similar to EPROM except that the erasing done
by electrical signal instead of ultraviolet light and
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B. RAM(Read/Write Memory)
 It’s working area of CPU
 The CPU can access any memory location by specifying its
address.
 RAMs are two types.
i-Static RAM
 In the case of static RAM once the data is written into a memory
location, the data remain unchanged unless on same memory
location is written into again.
 It uses flip-flops for storage elements.
ii-Dynamic RAM
 In case of dynamic RAM the basic storage elements is a capacitor.
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 This element contains a 1or a 0 depending on the presence or
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The advantages of dynamic RAM over static RAM are
 It consumes less power than static RAM.
 It has about 5 times more storage element per unit area.
Disadvantages are that DRAMS have slower access times
and need special circuitry to periodically refresh memory.
2-Secondary Memory
 The maximum capacity of primary memory 2n location. Each
of 2n location where n is the number of CPU address lines.
 Sometimes it is necessary to handle more data than
allowed by the primary memory. In such cases secondary
memory is used.
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 The CPU cannot directly access memory but can access
 Memory Mapping
 8085 has 16-bit Address Bus
 The complete address space is given by the range of
addresses 0000H –FFFFH
 The range of addresses allocated to a memory device
is known as its memory map
Memory map: 64K memory device
I. Address lines required: 16 (A0 – A15)
II. Memory map: 0000H – FFFFH
Memory map: 32K memory device
 Address lines required: 15 (A0 – A14)
 Memory map: depends on how address line A15 is
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ROM Model:
 A Read Only Memory (ROM) has an encoder to select a
word in an encoder, only one of the inputs must be made
active.
 But to save lines, the CPU directly puts out the address
of the word it wants to access.
 So, it is necessary to insert a device between the
address put out by the CPU and the ROM inputs
which enables a unique input to the ROM.
 This device must be a decoder.
 This is an example with an address bus of
 n=3 bits and a memory of 8 bytes (23=8 words).
 The CPU puts out the address 111
on the address lines
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A2 A1 A0 to access the 8 word B7.
th
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RAM Or Read/Write Model:
 The internal organization of a Random Access Memory
(RAM) is similar to that of ROM.
 But RAM has input which is made active when data is to be
written into RAM.
 The figure shows a 3 bit = 8 words RAM.
 One of the outputs of the decoder is made active depending on
the address which is input to it.
 This active output is fed to the encoder to generate the output
W, which is directly connected to the data bus of the system.

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 Interface
 Interface is the path for communication between two
components.
 Interfacing is two types,
1. memory interfacing and
2. I/O interfacing.
Memory Interfacing:
 When we are executing any instruction, we need the
microprocessor to access the memory for reading instruction
codes and the data stored in the memory.
 For this, both the memory and the microprocessor requires some
signals to read from and write to registers.
 The interfacing process includes some key factors to match
with the memory requirements and microprocessor signals.
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 Accessing memory can be summarized into the following
three steps:
 Select the chip.
 Identify the memory register.
 Enable the appropriate buffer.

Translating this to microprocessor domain:

 The microprocessor places a 16-bit address on the
address bus.
 Part of the address bus will select the chip and the other
part will go through the address decoder to select the
register. 14
 Memory structure & its requirements

 The way of interfacing bellow two chips to the

microprocessor is the same.
However, the ROM does not have a WR signal.

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Overall Interface

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 Memory Interfacing and Address
Memory Interfacing : Decoding:
 An address decoding circuit is employed to select the
required I/O device or a memory chip.
 When IO/M……. is high, decoder is to active and the require IO
device is selected.
 If IO/M….. is low, the decoder 1 is activated the required
memory chip is selected.
 A few MSB(most significant bit) of address line is applied to the
decoder to select the memory chip or an I/O device.

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A13 A14 A15 OUTPUT

0 0 0

Y0
0 0 1 Y1

0 1 0 Y2

0 1 1 Y3

1 0 0 Y4

1 0 1 Y5

1 1 0 Y6

1 1 1 Y7

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 II. I/O Interfacing
There are various communication devices like the keyboard, mouse,
printer, etc
 So, we need to interface the keyboard and other devices with the
microprocessor by using latches and buffers.
 In memory interfacing: 8 bit data line, 16 bit address line ,
control signals are connected to corresponding lines of memory IC.
 In I/O device interfacing: 8 bit data line, only 8 bit address
line , control signals are connected to corresponding lines of I/O
devices.

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 8085 I/O addressing
 I/O devices can be interfaced using addresses from memory space
 8085 treats such an I/O device as a memory location
 This is called Memory-mapped I/O
 8085 has a separate 8-bit addressing scheme for I/O devices
 I/O address space: 00H to FFH
 This is called Peripheral-mapped I/O or I/O-mapped I/O

8085 Communication with I/O device

Involves the following three steps
1. Identify the I/O device (with address)
2. Generate Timing & Control signals
3. Data transfer takes place
8085 communicates with a I/O device only if there is a Program
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1. Identify the I/O device (with address)
a) Memory-mapped I/O (16-bit address)
b) Peripheral-mapped I/O (8-bit address)
2. Generate Timing & Control signals
 Memory-mapped I/O
 Reading Input: IO/M = 0, RD = 0
 Write to Output: IO/M = 0, WR = 0
 Peripheral-mapped I/O
 Reading Input: IO/M = 1, RD = 0
 Write to Output: IO/M = 1, WR = 0

3. Data transfer takes place

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Address Space Partitioning: Intel 8085 uses a 16-bit wide
address bus or addressing memory and I/O devices. It
can access 216=64k bytes of memory and I/O devices.
 Input/output devices can be interfaced with microprocessor
systems in two ways:
1. Memory mapped I/O scheme
2. I/O mapped I/O scheme
1. Memory Mapped I/O Scheme
I/O devices are identified by 16-bit addresses
8085 communicates with an I/O device as if it were one of the
memory Locations
Address space is defined as set of all possible addresses that
a microprocessor can generate.
Some address are assigned to memories and some address to I/O
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2. I/O Mapped I/O Scheme
 In this scheme the address are assigned to memory
locations can also be assigned to I/O devices.
 To distinguish whether the address on an address bus is for
memory location or I/O devices. The Intel 8085 issues
IO/M…… signal for this purpose.
 When the signal is high , the address of an address bus
is for I/O device.
 When low, the address is for a memory location.
 Two extra instructions IN and OUT are used to address I/O
device.
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 The IN instruction is used to read data from an input
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 The interfacing of Output Devices
 Output devices are usually slow. Also, the output is
usually expected to continue appearing on the output device
for a long period of time.
 Given that the data will only be present on the data lines for a
very short period (microseconds), it has to be latched
externally.
 To do this the external latch should be enabled when the
port’s address is present on the address bus, the IO/M signal
is set high and WR is set low.
 The resulting signal would be active when the output device is
being accessed by the microprocessor.
 Decoding the address bus (for memory-mapped devices)
follows the same techniques discussed in interfacing memory.
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 The interfacing of Input Devices
 The basic concepts are similar to interfacing of output
devices.
 The address lines are decoded to generate a signal that is
active when the particular port is being accessed.
 An IORD signal is generated by combining the IO/M and the
RD signals from the microprocessor.
 A tri-state buffer is used to connect the input device to the
data bus.
 The control (Enable) for these buffers is connected to the
result of combining the address signal and the signal IOR.D.

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End of chapter Three
Any Question???

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